[mirror_qemu.git] / hw / xtensa / xtfpga.c

/*
 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of the Open Source and Linux Lab nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include "sysemu/sysemu.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "elf.h"
#include "exec/memory.h"
#include "exec/address-spaces.h"
#include "hw/char/serial.h"
#include "net/net.h"
#include "hw/sysbus.h"
#include "hw/block/flash.h"
#include "sysemu/blockdev.h"
#include "sysemu/char.h"
#include "qemu/error-report.h"
#include "bootparam.h"

typedef struct LxBoardDesc {
    hwaddr flash_base;
    size_t flash_size;
    size_t flash_boot_base;
    size_t flash_sector_size;
    size_t sram_size;
} LxBoardDesc;

typedef struct Lx60FpgaState {
    MemoryRegion iomem;
    uint32_t leds;
    uint32_t switches;
} Lx60FpgaState;

static void lx60_fpga_reset(void *opaque)
{
    Lx60FpgaState *s = opaque;

    s->leds = 0;
    s->switches = 0;
}

static uint64_t lx60_fpga_read(void *opaque, hwaddr addr,
        unsigned size)
{
    Lx60FpgaState *s = opaque;

    switch (addr) {
    case 0x0: /*build date code*/
        return 0x09272011;

    case 0x4: /*processor clock frequency, Hz*/
        return 10000000;

    case 0x8: /*LEDs (off = 0, on = 1)*/
        return s->leds;

    case 0xc: /*DIP switches (off = 0, on = 1)*/
        return s->switches;
    }
    return 0;
}

static void lx60_fpga_write(void *opaque, hwaddr addr,
        uint64_t val, unsigned size)
{
    Lx60FpgaState *s = opaque;

    switch (addr) {
    case 0x8: /*LEDs (off = 0, on = 1)*/
        s->leds = val;
        break;

    case 0x10: /*board reset*/
        if (val == 0xdead) {
            qemu_system_reset_request();
        }
        break;
    }
}

static const MemoryRegionOps lx60_fpga_ops = {
    .read = lx60_fpga_read,
    .write = lx60_fpga_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static Lx60FpgaState *lx60_fpga_init(MemoryRegion *address_space,
        hwaddr base)
{
    Lx60FpgaState *s = g_malloc(sizeof(Lx60FpgaState));

    memory_region_init_io(&s->iomem, NULL, &lx60_fpga_ops, s,
            "lx60.fpga", 0x10000);
    memory_region_add_subregion(address_space, base, &s->iomem);
    lx60_fpga_reset(s);
    qemu_register_reset(lx60_fpga_reset, s);
    return s;
}

static void lx60_net_init(MemoryRegion *address_space,
        hwaddr base,
        hwaddr descriptors,
        hwaddr buffers,
        qemu_irq irq, NICInfo *nd)
{
    DeviceState *dev;
    SysBusDevice *s;
    MemoryRegion *ram;

    dev = qdev_create(NULL, "open_eth");
    qdev_set_nic_properties(dev, nd);
    qdev_init_nofail(dev);

    s = SYS_BUS_DEVICE(dev);
    sysbus_connect_irq(s, 0, irq);
    memory_region_add_subregion(address_space, base,
            sysbus_mmio_get_region(s, 0));
    memory_region_add_subregion(address_space, descriptors,
            sysbus_mmio_get_region(s, 1));

    ram = g_malloc(sizeof(*ram));
    memory_region_init_ram(ram, OBJECT(s), "open_eth.ram", 16384);
    vmstate_register_ram_global(ram);
    memory_region_add_subregion(address_space, buffers, ram);
}

static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
{
    XtensaCPU *cpu = opaque;

    return cpu_get_phys_page_debug(CPU(cpu), addr);
}

static void lx60_reset(void *opaque)
{
    XtensaCPU *cpu = opaque;

    cpu_reset(CPU(cpu));
}

static void lx_init(const LxBoardDesc *board, MachineState *machine)
{
#ifdef TARGET_WORDS_BIGENDIAN
    int be = 1;
#else
    int be = 0;
#endif
    MemoryRegion *system_memory = get_system_memory();
    XtensaCPU *cpu = NULL;
    CPUXtensaState *env = NULL;
    MemoryRegion *ram, *rom, *system_io;
    DriveInfo *dinfo;
    pflash_t *flash = NULL;
    QemuOpts *machine_opts = qemu_get_machine_opts();
    const char *cpu_model = machine->cpu_model;
    const char *kernel_filename = qemu_opt_get(machine_opts, "kernel");
    const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
    int n;

    if (!cpu_model) {
        cpu_model = XTENSA_DEFAULT_CPU_MODEL;
    }

    for (n = 0; n < smp_cpus; n++) {
        cpu = cpu_xtensa_init(cpu_model);
        if (cpu == NULL) {
            error_report("unable to find CPU definition '%s'\n",
                         cpu_model);
            exit(EXIT_FAILURE);
        }
        env = &cpu->env;

        env->sregs[PRID] = n;
        qemu_register_reset(lx60_reset, cpu);
        /* Need MMU initialized prior to ELF loading,
         * so that ELF gets loaded into virtual addresses
         */
        cpu_reset(CPU(cpu));
    }

    ram = g_malloc(sizeof(*ram));
    memory_region_init_ram(ram, NULL, "lx60.dram", machine->ram_size);
    vmstate_register_ram_global(ram);
    memory_region_add_subregion(system_memory, 0, ram);

    system_io = g_malloc(sizeof(*system_io));
    memory_region_init(system_io, NULL, "lx60.io", 224 * 1024 * 1024);
    memory_region_add_subregion(system_memory, 0xf0000000, system_io);
    lx60_fpga_init(system_io, 0x0d020000);
    if (nd_table[0].used) {
        lx60_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
                xtensa_get_extint(env, 1), nd_table);
    }

    if (!serial_hds[0]) {
        serial_hds[0] = qemu_chr_new("serial0", "null", NULL);
    }

    serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0),
            115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    if (dinfo) {
        flash = pflash_cfi01_register(board->flash_base,
                NULL, "lx60.io.flash", board->flash_size,
                dinfo->bdrv, board->flash_sector_size,
                board->flash_size / board->flash_sector_size,
                4, 0x0000, 0x0000, 0x0000, 0x0000, be);
        if (flash == NULL) {
            error_report("unable to mount pflash\n");
            exit(EXIT_FAILURE);
        }
    }

    /* Use presence of kernel file name as 'boot from SRAM' switch. */
    if (kernel_filename) {
        rom = g_malloc(sizeof(*rom));
        memory_region_init_ram(rom, NULL, "lx60.sram", board->sram_size);
        vmstate_register_ram_global(rom);
        memory_region_add_subregion(system_memory, 0xfe000000, rom);

        /* Put kernel bootparameters to the end of that SRAM */
        if (kernel_cmdline) {
            size_t cmdline_size = strlen(kernel_cmdline) + 1;
            size_t bp_size = sizeof(BpTag[4]) + cmdline_size;
            uint32_t tagptr = (0xfe000000 + board->sram_size - bp_size) & ~0xff;

            env->regs[2] = tagptr;

            tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
            if (cmdline_size > 1) {
                tagptr = put_tag(tagptr, BP_TAG_COMMAND_LINE,
                        cmdline_size, kernel_cmdline);
            }
            tagptr = put_tag(tagptr, BP_TAG_LAST, 0, NULL);
        }
        uint64_t elf_entry;
        uint64_t elf_lowaddr;
        int success = load_elf(kernel_filename, translate_phys_addr, cpu,
                &elf_entry, &elf_lowaddr, NULL, be, ELF_MACHINE, 0);
        if (success > 0) {
            env->pc = elf_entry;
        }
    } else {
        if (flash) {
            MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
            MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));

            memory_region_init_alias(flash_io, NULL, "lx60.flash",
                    flash_mr, board->flash_boot_base,
                    board->flash_size - board->flash_boot_base < 0x02000000 ?
                    board->flash_size - board->flash_boot_base : 0x02000000);
            memory_region_add_subregion(system_memory, 0xfe000000,
                    flash_io);
        }
    }
}

static void xtensa_lx60_init(MachineState *machine)
{
    static const LxBoardDesc lx60_board = {
        .flash_base = 0xf8000000,
        .flash_size = 0x00400000,
        .flash_sector_size = 0x10000,
        .sram_size = 0x20000,
    };
    lx_init(&lx60_board, machine);
}

static void xtensa_lx200_init(MachineState *machine)
{
    static const LxBoardDesc lx200_board = {
        .flash_base = 0xf8000000,
        .flash_size = 0x01000000,
        .flash_sector_size = 0x20000,
        .sram_size = 0x2000000,
    };
    lx_init(&lx200_board, machine);
}

static void xtensa_ml605_init(MachineState *machine)
{
    static const LxBoardDesc ml605_board = {
        .flash_base = 0xf8000000,
        .flash_size = 0x02000000,
        .flash_sector_size = 0x20000,
        .sram_size = 0x2000000,
    };
    lx_init(&ml605_board, machine);
}

static void xtensa_kc705_init(MachineState *machine)
{
    static const LxBoardDesc kc705_board = {
        .flash_base = 0xf0000000,
        .flash_size = 0x08000000,
        .flash_boot_base = 0x06000000,
        .flash_sector_size = 0x20000,
        .sram_size = 0x2000000,
    };
    lx_init(&kc705_board, machine);
}

static QEMUMachine xtensa_lx60_machine = {
    .name = "lx60",
    .desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")",
    .init = xtensa_lx60_init,
    .max_cpus = 4,
};

static QEMUMachine xtensa_lx200_machine = {
    .name = "lx200",
    .desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")",
    .init = xtensa_lx200_init,
    .max_cpus = 4,
};

static QEMUMachine xtensa_ml605_machine = {
    .name = "ml605",
    .desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")",
    .init = xtensa_ml605_init,
    .max_cpus = 4,
};

static QEMUMachine xtensa_kc705_machine = {
    .name = "kc705",
    .desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")",
    .init = xtensa_kc705_init,
    .max_cpus = 4,
};

static void xtensa_lx_machines_init(void)
{
    qemu_register_machine(&xtensa_lx60_machine);
    qemu_register_machine(&xtensa_lx200_machine);
    qemu_register_machine(&xtensa_ml605_machine);
    qemu_register_machine(&xtensa_kc705_machine);
}

machine_init(xtensa_lx_machines_init);
Commit	Line	Data
0200db65 MF	1	/*
	2	* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions are met:
	7	* * Redistributions of source code must retain the above copyright
	8	* notice, this list of conditions and the following disclaimer.
	9	* * Redistributions in binary form must reproduce the above copyright
	10	* notice, this list of conditions and the following disclaimer in the
	11	* documentation and/or other materials provided with the distribution.
	12	* * Neither the name of the Open Source and Linux Lab nor the
	13	* names of its contributors may be used to endorse or promote products
	14	* derived from this software without specific prior written permission.
	15	*
	16	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	17	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	20	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	21	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	22	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	23	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	24	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	25	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	26	*/
	27
9c17d615	28	#include "sysemu/sysemu.h"
83c9f4ca PB	29	#include "hw/boards.h"
83c9f4ca PB	30	#include "hw/loader.h"
0200db65	31	#include "elf.h"
022c62cb PB	32	#include "exec/memory.h"
022c62cb PB	33	#include "exec/address-spaces.h"
0d09e41a	34	#include "hw/char/serial.h"
1422e32d	35	#include "net/net.h"
83c9f4ca	36	#include "hw/sysbus.h"
0d09e41a	37	#include "hw/block/flash.h"
9c17d615	38	#include "sysemu/blockdev.h"
dccfcd0e	39	#include "sysemu/char.h"
8488ab02	40	#include "qemu/error-report.h"
b707ab75	41	#include "bootparam.h"
82b25dc8 MF	42
82b25dc8 MF	43	typedef struct LxBoardDesc {
e0db904d	44	hwaddr flash_base;
82b25dc8	45	size_t flash_size;
37ed7c4b	46	size_t flash_boot_base;
82b25dc8 MF	47	size_t flash_sector_size;
	48	size_t sram_size;
	49	} LxBoardDesc;
0200db65 MF	50
	51	typedef struct Lx60FpgaState {
	52	MemoryRegion iomem;
	53	uint32_t leds;
	54	uint32_t switches;
	55	} Lx60FpgaState;
	56
	57	static void lx60_fpga_reset(void *opaque)
	58	{
	59	Lx60FpgaState *s = opaque;
	60
	61	s->leds = 0;
	62	s->switches = 0;
	63	}
	64
a8170e5e	65	static uint64_t lx60_fpga_read(void *opaque, hwaddr addr,
0200db65 MF	66	unsigned size)
	67	{
	68	Lx60FpgaState *s = opaque;
	69
	70	switch (addr) {
	71	case 0x0: /build date code/
556ba668	72	return 0x09272011;
0200db65 MF	73
	74	case 0x4: /processor clock frequency, Hz/
	75	return 10000000;
	76
	77	case 0x8: /LEDs (off = 0, on = 1)/
	78	return s->leds;
	79
	80	case 0xc: /DIP switches (off = 0, on = 1)/
	81	return s->switches;
	82	}
	83	return 0;
	84	}
	85
a8170e5e	86	static void lx60_fpga_write(void *opaque, hwaddr addr,
0200db65 MF	87	uint64_t val, unsigned size)
	88	{
	89	Lx60FpgaState *s = opaque;
	90
	91	switch (addr) {
	92	case 0x8: /LEDs (off = 0, on = 1)/
	93	s->leds = val;
	94	break;
	95
	96	case 0x10: /board reset/
	97	if (val == 0xdead) {
	98	qemu_system_reset_request();
	99	}
	100	break;
	101	}
	102	}
	103
	104	static const MemoryRegionOps lx60_fpga_ops = {
	105	.read = lx60_fpga_read,
	106	.write = lx60_fpga_write,
	107	.endianness = DEVICE_NATIVE_ENDIAN,
	108	};
	109
	110	static Lx60FpgaState lx60_fpga_init(MemoryRegion address_space,
a8170e5e	111	hwaddr base)
0200db65 MF	112	{
	113	Lx60FpgaState *s = g_malloc(sizeof(Lx60FpgaState));
	114
2c9b15ca	115	memory_region_init_io(&s->iomem, NULL, &lx60_fpga_ops, s,
556ba668	116	"lx60.fpga", 0x10000);
0200db65 MF	117	memory_region_add_subregion(address_space, base, &s->iomem);
	118	lx60_fpga_reset(s);
	119	qemu_register_reset(lx60_fpga_reset, s);
	120	return s;
	121	}
	122
	123	static void lx60_net_init(MemoryRegion *address_space,
a8170e5e AK	124	hwaddr base,
	125	hwaddr descriptors,
	126	hwaddr buffers,
0200db65 MF	127	qemu_irq irq, NICInfo *nd)
	128	{
	129	DeviceState *dev;
	130	SysBusDevice *s;
	131	MemoryRegion *ram;
	132
	133	dev = qdev_create(NULL, "open_eth");
	134	qdev_set_nic_properties(dev, nd);
	135	qdev_init_nofail(dev);
	136
1356b98d	137	s = SYS_BUS_DEVICE(dev);
0200db65 MF	138	sysbus_connect_irq(s, 0, irq);
	139	memory_region_add_subregion(address_space, base,
	140	sysbus_mmio_get_region(s, 0));
	141	memory_region_add_subregion(address_space, descriptors,
	142	sysbus_mmio_get_region(s, 1));
	143
	144	ram = g_malloc(sizeof(*ram));
22fc860b	145	memory_region_init_ram(ram, OBJECT(s), "open_eth.ram", 16384);
c5705a77	146	vmstate_register_ram_global(ram);
0200db65 MF	147	memory_region_add_subregion(address_space, buffers, ram);
	148	}
	149
00b941e5	150	static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
0200db65	151	{
00b941e5 AF	152	XtensaCPU *cpu = opaque;
	153
	154	return cpu_get_phys_page_debug(CPU(cpu), addr);
0200db65 MF	155	}
0200db65 MF	156
1bba0dc9	157	static void lx60_reset(void *opaque)
0200db65	158	{
eded1267	159	XtensaCPU *cpu = opaque;
1bba0dc9	160
eded1267	161	cpu_reset(CPU(cpu));
0200db65 MF	162	}
0200db65 MF	163
3ef96221	164	static void lx_init(const LxBoardDesc board, MachineState machine)
0200db65 MF	165	{
	166	#ifdef TARGET_WORDS_BIGENDIAN
	167	int be = 1;
	168	#else
	169	int be = 0;
	170	#endif
	171	MemoryRegion *system_memory = get_system_memory();
adbb0f75	172	XtensaCPU *cpu = NULL;
5bfcb36e	173	CPUXtensaState *env = NULL;
0200db65	174	MemoryRegion ram, rom, *system_io;
82b25dc8 MF	175	DriveInfo *dinfo;
82b25dc8 MF	176	pflash_t *flash = NULL;
37b259d0	177	QemuOpts *machine_opts = qemu_get_machine_opts();
3ef96221	178	const char *cpu_model = machine->cpu_model;
37b259d0 MF	179	const char *kernel_filename = qemu_opt_get(machine_opts, "kernel");
37b259d0 MF	180	const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
0200db65 MF	181	int n;
0200db65 MF	182
82b25dc8	183	if (!cpu_model) {
e38077ff	184	cpu_model = XTENSA_DEFAULT_CPU_MODEL;
82b25dc8 MF	185	}
82b25dc8 MF	186
0200db65	187	for (n = 0; n < smp_cpus; n++) {
adbb0f75 AF	188	cpu = cpu_xtensa_init(cpu_model);
adbb0f75 AF	189	if (cpu == NULL) {
8488ab02 MF	190	error_report("unable to find CPU definition '%s'\n",
	191	cpu_model);
	192	exit(EXIT_FAILURE);
0200db65	193	}
adbb0f75 AF	194	env = &cpu->env;
adbb0f75 AF	195
0200db65	196	env->sregs[PRID] = n;
eded1267	197	qemu_register_reset(lx60_reset, cpu);
0200db65 MF	198	/* Need MMU initialized prior to ELF loading,
	199	* so that ELF gets loaded into virtual addresses
	200	*/
adbb0f75	201	cpu_reset(CPU(cpu));
0200db65 MF	202	}
	203
	204	ram = g_malloc(sizeof(*ram));
3ef96221	205	memory_region_init_ram(ram, NULL, "lx60.dram", machine->ram_size);
c5705a77	206	vmstate_register_ram_global(ram);
0200db65 MF	207	memory_region_add_subregion(system_memory, 0, ram);
0200db65 MF	208
0200db65	209	system_io = g_malloc(sizeof(*system_io));
2c9b15ca	210	memory_region_init(system_io, NULL, "lx60.io", 224 * 1024 * 1024);
0200db65 MF	211	memory_region_add_subregion(system_memory, 0xf0000000, system_io);
0200db65 MF	212	lx60_fpga_init(system_io, 0x0d020000);
a005d073	213	if (nd_table[0].used) {
0200db65 MF	214	lx60_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
	215	xtensa_get_extint(env, 1), nd_table);
	216	}
	217
	218	if (!serial_hds[0]) {
	219	serial_hds[0] = qemu_chr_new("serial0", "null", NULL);
	220	}
	221
	222	serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0),
	223	115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
	224
82b25dc8 MF	225	dinfo = drive_get(IF_PFLASH, 0, 0);
82b25dc8 MF	226	if (dinfo) {
e0db904d	227	flash = pflash_cfi01_register(board->flash_base,
82b25dc8 MF	228	NULL, "lx60.io.flash", board->flash_size,
	229	dinfo->bdrv, board->flash_sector_size,
	230	board->flash_size / board->flash_sector_size,
	231	4, 0x0000, 0x0000, 0x0000, 0x0000, be);
	232	if (flash == NULL) {
8488ab02 MF	233	error_report("unable to mount pflash\n");
8488ab02 MF	234	exit(EXIT_FAILURE);
82b25dc8 MF	235	}
	236	}
	237
	238	/* Use presence of kernel file name as 'boot from SRAM' switch. */
0200db65	239	if (kernel_filename) {
292627bb	240	rom = g_malloc(sizeof(*rom));
2c9b15ca	241	memory_region_init_ram(rom, NULL, "lx60.sram", board->sram_size);
c5705a77	242	vmstate_register_ram_global(rom);
292627bb MF	243	memory_region_add_subregion(system_memory, 0xfe000000, rom);
	244
	245	/* Put kernel bootparameters to the end of that SRAM */
	246	if (kernel_cmdline) {
	247	size_t cmdline_size = strlen(kernel_cmdline) + 1;
	248	size_t bp_size = sizeof(BpTag[4]) + cmdline_size;
	249	uint32_t tagptr = (0xfe000000 + board->sram_size - bp_size) & ~0xff;
	250
	251	env->regs[2] = tagptr;
	252
62dbaede	253	tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
292627bb	254	if (cmdline_size > 1) {
62dbaede	255	tagptr = put_tag(tagptr, BP_TAG_COMMAND_LINE,
292627bb MF	256	cmdline_size, kernel_cmdline);
292627bb MF	257	}
62dbaede	258	tagptr = put_tag(tagptr, BP_TAG_LAST, 0, NULL);
292627bb	259	}
0200db65 MF	260	uint64_t elf_entry;
0200db65 MF	261	uint64_t elf_lowaddr;
00b941e5	262	int success = load_elf(kernel_filename, translate_phys_addr, cpu,
0200db65 MF	263	&elf_entry, &elf_lowaddr, NULL, be, ELF_MACHINE, 0);
	264	if (success > 0) {
	265	env->pc = elf_entry;
	266	}
82b25dc8 MF	267	} else {
	268	if (flash) {
	269	MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
	270	MemoryRegion flash_io = g_malloc(sizeof(flash_io));
	271
2c9b15ca	272	memory_region_init_alias(flash_io, NULL, "lx60.flash",
37ed7c4b MF	273	flash_mr, board->flash_boot_base,
	274	board->flash_size - board->flash_boot_base < 0x02000000 ?
	275	board->flash_size - board->flash_boot_base : 0x02000000);
82b25dc8 MF	276	memory_region_add_subregion(system_memory, 0xfe000000,
	277	flash_io);
	278	}
0200db65 MF	279	}
	280	}
	281
3ef96221	282	static void xtensa_lx60_init(MachineState *machine)
0200db65	283	{
82b25dc8	284	static const LxBoardDesc lx60_board = {
e0db904d MF	285	.flash_base = 0xf8000000,
e0db904d MF	286	.flash_size = 0x00400000,
82b25dc8 MF	287	.flash_sector_size = 0x10000,
	288	.sram_size = 0x20000,
	289	};
3ef96221	290	lx_init(&lx60_board, machine);
82b25dc8 MF	291	}
82b25dc8 MF	292
3ef96221	293	static void xtensa_lx200_init(MachineState *machine)
82b25dc8 MF	294	{
82b25dc8 MF	295	static const LxBoardDesc lx200_board = {
e0db904d MF	296	.flash_base = 0xf8000000,
e0db904d MF	297	.flash_size = 0x01000000,
82b25dc8 MF	298	.flash_sector_size = 0x20000,
	299	.sram_size = 0x2000000,
	300	};
3ef96221	301	lx_init(&lx200_board, machine);
0200db65 MF	302	}
0200db65 MF	303
3ef96221	304	static void xtensa_ml605_init(MachineState *machine)
e0db904d MF	305	{
	306	static const LxBoardDesc ml605_board = {
	307	.flash_base = 0xf8000000,
	308	.flash_size = 0x02000000,
	309	.flash_sector_size = 0x20000,
	310	.sram_size = 0x2000000,
	311	};
3ef96221	312	lx_init(&ml605_board, machine);
e0db904d MF	313	}
e0db904d MF	314
3ef96221	315	static void xtensa_kc705_init(MachineState *machine)
e0db904d MF	316	{
	317	static const LxBoardDesc kc705_board = {
	318	.flash_base = 0xf0000000,
	319	.flash_size = 0x08000000,
37ed7c4b	320	.flash_boot_base = 0x06000000,
e0db904d MF	321	.flash_sector_size = 0x20000,
	322	.sram_size = 0x2000000,
	323	};
3ef96221	324	lx_init(&kc705_board, machine);
e0db904d MF	325	}
e0db904d MF	326
0200db65 MF	327	static QEMUMachine xtensa_lx60_machine = {
0200db65 MF	328	.name = "lx60",
e38077ff	329	.desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")",
0200db65 MF	330	.init = xtensa_lx60_init,
	331	.max_cpus = 4,
	332	};
	333
82b25dc8 MF	334	static QEMUMachine xtensa_lx200_machine = {
82b25dc8 MF	335	.name = "lx200",
e38077ff	336	.desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")",
82b25dc8 MF	337	.init = xtensa_lx200_init,
	338	.max_cpus = 4,
	339	};
	340
e0db904d MF	341	static QEMUMachine xtensa_ml605_machine = {
	342	.name = "ml605",
	343	.desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")",
	344	.init = xtensa_ml605_init,
	345	.max_cpus = 4,
	346	};
	347
	348	static QEMUMachine xtensa_kc705_machine = {
	349	.name = "kc705",
	350	.desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")",
	351	.init = xtensa_kc705_init,
	352	.max_cpus = 4,
	353	};
	354
82b25dc8	355	static void xtensa_lx_machines_init(void)
0200db65 MF	356	{
0200db65 MF	357	qemu_register_machine(&xtensa_lx60_machine);
82b25dc8	358	qemu_register_machine(&xtensa_lx200_machine);
e0db904d MF	359	qemu_register_machine(&xtensa_ml605_machine);
e0db904d MF	360	qemu_register_machine(&xtensa_kc705_machine);
0200db65 MF	361	}
0200db65 MF	362
82b25dc8	363	machine_init(xtensa_lx_machines_init);