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Commit | Line | Data |
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1ad2134f | 1 | #ifndef CPU_COMMON_H |
175de524 | 2 | #define CPU_COMMON_H |
1ad2134f | 3 | |
07f35073 | 4 | /* CPU interfaces that are target independent. */ |
1ad2134f | 5 | |
ce927ed9 | 6 | #ifndef CONFIG_USER_ONLY |
022c62cb | 7 | #include "exec/hwaddr.h" |
ce927ed9 | 8 | #endif |
37b76cfd | 9 | |
06445fbd PMD |
10 | /** |
11 | * vaddr: | |
12 | * Type wide enough to contain any #target_ulong virtual address. | |
13 | */ | |
14 | typedef uint64_t vaddr; | |
15 | #define VADDR_PRId PRId64 | |
16 | #define VADDR_PRIu PRIu64 | |
17 | #define VADDR_PRIo PRIo64 | |
18 | #define VADDR_PRIx PRIx64 | |
19 | #define VADDR_PRIX PRIX64 | |
20 | #define VADDR_MAX UINT64_MAX | |
21 | ||
1f269c14 MAL |
22 | void cpu_exec_init_all(void); |
23 | void cpu_exec_step_atomic(CPUState *cpu); | |
24 | ||
b269a708 PMD |
25 | /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even |
26 | * when intptr_t is 32-bit and we are aligning a long long. | |
27 | */ | |
28 | extern uintptr_t qemu_host_page_size; | |
29 | extern intptr_t qemu_host_page_mask; | |
30 | ||
31 | #define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size) | |
8e3b0cbb | 32 | #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size()) |
b269a708 | 33 | |
0ac20318 | 34 | /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */ |
267f685b PB |
35 | void qemu_init_cpu_list(void); |
36 | void cpu_list_lock(void); | |
37 | void cpu_list_unlock(void); | |
ab1a161f | 38 | unsigned int cpu_list_generation_id_get(void); |
267f685b | 39 | |
2cd53943 | 40 | void tcg_flush_softmmu_tlb(CPUState *cs); |
a976a99a | 41 | void tcg_flush_jmp_cache(CPUState *cs); |
2cd53943 | 42 | |
d9f24bf5 PB |
43 | void tcg_iommu_init_notifier_list(CPUState *cpu); |
44 | void tcg_iommu_free_notifier_list(CPUState *cpu); | |
45 | ||
b3755a91 PB |
46 | #if !defined(CONFIG_USER_ONLY) |
47 | ||
dd310534 AG |
48 | enum device_endian { |
49 | DEVICE_NATIVE_ENDIAN, | |
50 | DEVICE_BIG_ENDIAN, | |
51 | DEVICE_LITTLE_ENDIAN, | |
52 | }; | |
53 | ||
e03b5686 | 54 | #if HOST_BIG_ENDIAN |
c99a29e7 YX |
55 | #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN |
56 | #else | |
57 | #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN | |
58 | #endif | |
59 | ||
1ad2134f | 60 | /* address in the RAM (different from a physical address) */ |
4be403c8 | 61 | #if defined(CONFIG_XEN_BACKEND) |
f15fbc4b AP |
62 | typedef uint64_t ram_addr_t; |
63 | # define RAM_ADDR_MAX UINT64_MAX | |
64 | # define RAM_ADDR_FMT "%" PRIx64 | |
65 | #else | |
53576999 SW |
66 | typedef uintptr_t ram_addr_t; |
67 | # define RAM_ADDR_MAX UINTPTR_MAX | |
68 | # define RAM_ADDR_FMT "%" PRIxPTR | |
f15fbc4b | 69 | #endif |
1ad2134f PB |
70 | |
71 | /* memory API */ | |
72 | ||
cd19cfa2 | 73 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); |
1ad2134f | 74 | /* This should not be used by devices. */ |
07bdaa41 | 75 | ram_addr_t qemu_ram_addr_from_host(void *ptr); |
97e03465 | 76 | ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); |
e3dd7493 | 77 | RAMBlock *qemu_ram_block_by_name(const char *name); |
422148d3 | 78 | RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, |
f615f396 | 79 | ram_addr_t *offset); |
f90bb71b | 80 | ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host); |
fa53a0e5 GA |
81 | void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev); |
82 | void qemu_ram_unset_idstr(RAMBlock *block); | |
422148d3 | 83 | const char *qemu_ram_get_idstr(RAMBlock *rb); |
754cb9c0 YK |
84 | void *qemu_ram_get_host_addr(RAMBlock *rb); |
85 | ram_addr_t qemu_ram_get_offset(RAMBlock *rb); | |
86 | ram_addr_t qemu_ram_get_used_length(RAMBlock *rb); | |
082851a3 | 87 | ram_addr_t qemu_ram_get_max_length(RAMBlock *rb); |
463a4ac2 | 88 | bool qemu_ram_is_shared(RAMBlock *rb); |
8dbe22c6 | 89 | bool qemu_ram_is_noreserve(RAMBlock *rb); |
2ce16640 DDAG |
90 | bool qemu_ram_is_uf_zeroable(RAMBlock *rb); |
91 | void qemu_ram_set_uf_zeroable(RAMBlock *rb); | |
b895de50 CLG |
92 | bool qemu_ram_is_migratable(RAMBlock *rb); |
93 | void qemu_ram_set_migratable(RAMBlock *rb); | |
94 | void qemu_ram_unset_migratable(RAMBlock *rb); | |
2ce16640 | 95 | |
863e9621 | 96 | size_t qemu_ram_pagesize(RAMBlock *block); |
67f11b5c | 97 | size_t qemu_ram_pagesize_largest(void); |
1ad2134f | 98 | |
1f649fe0 PMD |
99 | /** |
100 | * cpu_address_space_init: | |
101 | * @cpu: CPU to add this address space to | |
102 | * @asidx: integer index of this address space | |
103 | * @prefix: prefix to be used as name of address space | |
104 | * @mr: the root memory region of address space | |
105 | * | |
106 | * Add the specified address space to the CPU's cpu_ases list. | |
107 | * The address space added with @asidx 0 is the one used for the | |
108 | * convenience pointer cpu->as. | |
109 | * The target-specific code which registers ASes is responsible | |
110 | * for defining what semantics address space 0, 1, 2, etc have. | |
111 | * | |
112 | * Before the first call to this function, the caller must set | |
113 | * cpu->num_ases to the total number of address spaces it needs | |
114 | * to support. | |
115 | * | |
116 | * Note that with KVM only one address space is supported. | |
117 | */ | |
118 | void cpu_address_space_init(CPUState *cpu, int asidx, | |
119 | const char *prefix, MemoryRegion *mr); | |
120 | ||
d7ef71ef | 121 | void cpu_physical_memory_rw(hwaddr addr, void *buf, |
28c80bfe | 122 | hwaddr len, bool is_write); |
a8170e5e | 123 | static inline void cpu_physical_memory_read(hwaddr addr, |
0c249ff7 | 124 | void *buf, hwaddr len) |
1ad2134f | 125 | { |
85eb7c18 | 126 | cpu_physical_memory_rw(addr, buf, len, false); |
1ad2134f | 127 | } |
a8170e5e | 128 | static inline void cpu_physical_memory_write(hwaddr addr, |
0c249ff7 | 129 | const void *buf, hwaddr len) |
1ad2134f | 130 | { |
85eb7c18 | 131 | cpu_physical_memory_rw(addr, (void *)buf, len, true); |
1ad2134f | 132 | } |
1f649fe0 | 133 | void cpu_reloading_memory_map(void); |
a8170e5e AK |
134 | void *cpu_physical_memory_map(hwaddr addr, |
135 | hwaddr *plen, | |
28c80bfe | 136 | bool is_write); |
a8170e5e | 137 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, |
28c80bfe | 138 | bool is_write, hwaddr access_len); |
e95205e1 FZ |
139 | void cpu_register_map_client(QEMUBH *bh); |
140 | void cpu_unregister_map_client(QEMUBH *bh); | |
1ad2134f | 141 | |
a8170e5e | 142 | bool cpu_physical_memory_is_io(hwaddr phys_addr); |
76f35538 | 143 | |
6842a08e BS |
144 | /* Coalesced MMIO regions are areas where write operations can be reordered. |
145 | * This usually implies that write operations are side-effect free. This allows | |
146 | * batching which can make a major impact on performance when using | |
147 | * virtualization. | |
148 | */ | |
6842a08e BS |
149 | void qemu_flush_coalesced_mmio_buffer(void); |
150 | ||
0c249ff7 | 151 | void cpu_flush_icache_range(hwaddr start, hwaddr len); |
1ad2134f | 152 | |
754cb9c0 | 153 | typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque); |
bd2fa51f | 154 | |
e3807054 | 155 | int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); |
d3a5038c | 156 | int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length); |
bd2fa51f | 157 | |
b3755a91 PB |
158 | #endif |
159 | ||
73842ef0 PMD |
160 | /* Returns: 0 on success, -1 on error */ |
161 | int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, | |
162 | void *ptr, size_t len, bool is_write); | |
163 | ||
c5e3c918 PB |
164 | /* vl.c */ |
165 | extern int singlestep; | |
166 | ||
377bf6f3 PMD |
167 | void list_cpus(const char *optarg); |
168 | ||
175de524 | 169 | #endif /* CPU_COMMON_H */ |