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Commit | Line | Data |
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43e3346e | 1 | /* |
ff90606f | 2 | * ASPEED SoC family |
43e3346e AJ |
3 | * |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * | |
6 | * Copyright 2016 IBM Corp. | |
7 | * | |
8 | * This code is licensed under the GPL version 2 or later. See | |
9 | * the COPYING file in the top-level directory. | |
10 | */ | |
11 | ||
ff90606f CLG |
12 | #ifndef ASPEED_SOC_H |
13 | #define ASPEED_SOC_H | |
43e3346e | 14 | |
f25c0ae1 | 15 | #include "hw/cpu/a15mpcore.h" |
356b230e | 16 | #include "hw/arm/armv7m.h" |
43e3346e | 17 | #include "hw/intc/aspeed_vic.h" |
334973bb | 18 | #include "hw/misc/aspeed_scu.h" |
199fd623 | 19 | #include "hw/adc/aspeed_adc.h" |
c2da8a8b | 20 | #include "hw/misc/aspeed_sdmc.h" |
118c82e7 | 21 | #include "hw/misc/aspeed_xdma.h" |
43e3346e | 22 | #include "hw/timer/aspeed_timer.h" |
ea5dcf4e | 23 | #include "hw/rtc/aspeed_rtc.h" |
16020011 | 24 | #include "hw/i2c/aspeed_i2c.h" |
3222165d | 25 | #include "hw/misc/aspeed_i3c.h" |
7c1c69bc | 26 | #include "hw/ssi/aspeed_smc.h" |
a3888d75 | 27 | #include "hw/misc/aspeed_hace.h" |
e1acf581 | 28 | #include "hw/misc/aspeed_sbc.h" |
013befe1 | 29 | #include "hw/watchdog/wdt_aspeed.h" |
ea337c65 | 30 | #include "hw/net/ftgmac100.h" |
ec150c7e | 31 | #include "target/arm/cpu.h" |
fdcc7c06 | 32 | #include "hw/gpio/aspeed_gpio.h" |
2bea128c | 33 | #include "hw/sd/aspeed_sdhci.h" |
bfdd34f1 | 34 | #include "hw/usb/hcd-ehci.h" |
db1015e9 | 35 | #include "qom/object.h" |
2ecf1726 | 36 | #include "hw/misc/aspeed_lpc.h" |
80beb085 | 37 | #include "hw/misc/unimp.h" |
55c57023 | 38 | #include "hw/misc/aspeed_peci.h" |
43e3346e | 39 | |
dbcabeeb | 40 | #define ASPEED_SPIS_NUM 2 |
bfdd34f1 | 41 | #define ASPEED_EHCIS_NUM 2 |
6b2b2a70 | 42 | #define ASPEED_WDTS_NUM 4 |
ece09bee | 43 | #define ASPEED_CPUS_NUM 2 |
d300db02 | 44 | #define ASPEED_MACS_NUM 4 |
dbcabeeb | 45 | |
db1015e9 | 46 | struct AspeedSoCState { |
43e3346e AJ |
47 | /*< private >*/ |
48 | DeviceState parent; | |
49 | ||
50 | /*< public >*/ | |
ece09bee | 51 | ARMCPU cpu[ASPEED_CPUS_NUM]; |
f25c0ae1 | 52 | A15MPPrivState a7mpcore; |
356b230e | 53 | ARMv7MState armv7m; |
4dd9d554 | 54 | MemoryRegion *memory; |
95b56e17 | 55 | MemoryRegion *dram_mr; |
346160cb | 56 | MemoryRegion dram_container; |
74af4eec | 57 | MemoryRegion sram; |
43e3346e | 58 | AspeedVICState vic; |
75fb4577 | 59 | AspeedRtcState rtc; |
43e3346e | 60 | AspeedTimerCtrlState timerctrl; |
16020011 | 61 | AspeedI2CState i2c; |
3222165d | 62 | AspeedI3CState i3c; |
334973bb | 63 | AspeedSCUState scu; |
a3888d75 | 64 | AspeedHACEState hace; |
118c82e7 | 65 | AspeedXDMAState xdma; |
199fd623 | 66 | AspeedADCState adc; |
0e5803df | 67 | AspeedSMCState fmc; |
dbcabeeb | 68 | AspeedSMCState spi[ASPEED_SPIS_NUM]; |
bfdd34f1 | 69 | EHCISysBusState ehci[ASPEED_EHCIS_NUM]; |
e1acf581 | 70 | AspeedSBCState sbc; |
80beb085 | 71 | UnimplementedDeviceState sbc_unimplemented; |
c2da8a8b | 72 | AspeedSDMCState sdmc; |
f986ee1d | 73 | AspeedWDTState wdt[ASPEED_WDTS_NUM]; |
67340990 | 74 | FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; |
289251b0 | 75 | AspeedMiiState mii[ASPEED_MACS_NUM]; |
fdcc7c06 | 76 | AspeedGPIOState gpio; |
f25c0ae1 | 77 | AspeedGPIOState gpio_1_8v; |
2bea128c | 78 | AspeedSDHCIState sdhci; |
a29e3e12 | 79 | AspeedSDHCIState emmc; |
2ecf1726 | 80 | AspeedLPCState lpc; |
55c57023 | 81 | AspeedPECIState peci; |
5d63d0c7 | 82 | uint32_t uart_default; |
356b230e | 83 | Clock *sysclk; |
80beb085 PD |
84 | UnimplementedDeviceState iomem; |
85 | UnimplementedDeviceState video; | |
86 | UnimplementedDeviceState emmc_boot_controller; | |
87 | UnimplementedDeviceState dpmcu; | |
db1015e9 | 88 | }; |
43e3346e | 89 | |
ff90606f | 90 | #define TYPE_ASPEED_SOC "aspeed-soc" |
a489d195 | 91 | OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) |
43e3346e | 92 | |
db1015e9 | 93 | struct AspeedSoCClass { |
54ecafb7 CLG |
94 | DeviceClass parent_class; |
95 | ||
b033271f | 96 | const char *name; |
ba1ba5cc | 97 | const char *cpu_type; |
b033271f | 98 | uint32_t silicon_rev; |
74af4eec | 99 | uint64_t sram_size; |
dbcabeeb | 100 | int spis_num; |
bfdd34f1 | 101 | int ehcis_num; |
f986ee1d | 102 | int wdts_num; |
d300db02 | 103 | int macs_num; |
c5e1bdb9 | 104 | int uarts_num; |
b456b113 | 105 | const int *irqmap; |
d783d1fe | 106 | const hwaddr *memmap; |
ece09bee | 107 | uint32_t num_cpus; |
699db715 | 108 | qemu_irq (*get_irq)(AspeedSoCState *s, int dev); |
db1015e9 | 109 | }; |
b033271f | 110 | |
43e3346e | 111 | |
b456b113 | 112 | enum { |
347df6f8 EH |
113 | ASPEED_DEV_IOMEM, |
114 | ASPEED_DEV_UART1, | |
115 | ASPEED_DEV_UART2, | |
116 | ASPEED_DEV_UART3, | |
117 | ASPEED_DEV_UART4, | |
118 | ASPEED_DEV_UART5, | |
ab5e8605 PD |
119 | ASPEED_DEV_UART6, |
120 | ASPEED_DEV_UART7, | |
121 | ASPEED_DEV_UART8, | |
122 | ASPEED_DEV_UART9, | |
123 | ASPEED_DEV_UART10, | |
124 | ASPEED_DEV_UART11, | |
125 | ASPEED_DEV_UART12, | |
126 | ASPEED_DEV_UART13, | |
347df6f8 EH |
127 | ASPEED_DEV_VUART, |
128 | ASPEED_DEV_FMC, | |
129 | ASPEED_DEV_SPI1, | |
130 | ASPEED_DEV_SPI2, | |
131 | ASPEED_DEV_EHCI1, | |
132 | ASPEED_DEV_EHCI2, | |
133 | ASPEED_DEV_VIC, | |
134 | ASPEED_DEV_SDMC, | |
135 | ASPEED_DEV_SCU, | |
136 | ASPEED_DEV_ADC, | |
e1acf581 | 137 | ASPEED_DEV_SBC, |
fe31a2ec | 138 | ASPEED_DEV_EMMC_BC, |
347df6f8 EH |
139 | ASPEED_DEV_VIDEO, |
140 | ASPEED_DEV_SRAM, | |
141 | ASPEED_DEV_SDHCI, | |
142 | ASPEED_DEV_GPIO, | |
143 | ASPEED_DEV_GPIO_1_8V, | |
144 | ASPEED_DEV_RTC, | |
145 | ASPEED_DEV_TIMER1, | |
146 | ASPEED_DEV_TIMER2, | |
147 | ASPEED_DEV_TIMER3, | |
148 | ASPEED_DEV_TIMER4, | |
149 | ASPEED_DEV_TIMER5, | |
150 | ASPEED_DEV_TIMER6, | |
151 | ASPEED_DEV_TIMER7, | |
152 | ASPEED_DEV_TIMER8, | |
153 | ASPEED_DEV_WDT, | |
154 | ASPEED_DEV_PWM, | |
155 | ASPEED_DEV_LPC, | |
156 | ASPEED_DEV_IBT, | |
157 | ASPEED_DEV_I2C, | |
55c57023 | 158 | ASPEED_DEV_PECI, |
347df6f8 EH |
159 | ASPEED_DEV_ETH1, |
160 | ASPEED_DEV_ETH2, | |
161 | ASPEED_DEV_ETH3, | |
162 | ASPEED_DEV_ETH4, | |
163 | ASPEED_DEV_MII1, | |
164 | ASPEED_DEV_MII2, | |
165 | ASPEED_DEV_MII3, | |
166 | ASPEED_DEV_MII4, | |
167 | ASPEED_DEV_SDRAM, | |
168 | ASPEED_DEV_XDMA, | |
169 | ASPEED_DEV_EMMC, | |
c59f781e | 170 | ASPEED_DEV_KCS, |
a3888d75 | 171 | ASPEED_DEV_HACE, |
d9e9cd59 TL |
172 | ASPEED_DEV_DPMCU, |
173 | ASPEED_DEV_DP, | |
3222165d | 174 | ASPEED_DEV_I3C, |
b456b113 CLG |
175 | }; |
176 | ||
699db715 | 177 | qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); |
470253b6 | 178 | void aspeed_soc_uart_init(AspeedSoCState *s); |
346160cb | 179 | bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); |
5bfcbda7 | 180 | void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr); |
80beb085 PD |
181 | void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, |
182 | const char *name, hwaddr addr, | |
183 | uint64_t size); | |
699db715 | 184 | |
ff90606f | 185 | #endif /* ASPEED_SOC_H */ |