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87ecb68b PB |
1 | #ifndef QEMU_PCI_H |
2 | #define QEMU_PCI_H | |
3 | ||
022c62cb | 4 | #include "exec/memory.h" |
9c17d615 | 5 | #include "sysemu/dma.h" |
6b1b92d3 | 6 | |
87ecb68b | 7 | /* PCI includes legacy ISA access. */ |
0d09e41a | 8 | #include "hw/isa/isa.h" |
87ecb68b | 9 | |
c759b24f | 10 | #include "hw/pci/pcie.h" |
0428527c | 11 | |
88c725c7 CH |
12 | extern bool pci_available; |
13 | ||
87ecb68b PB |
14 | /* PCI bus */ |
15 | ||
3ae80618 | 16 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
ab71cc0d | 17 | #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) |
3ae80618 AL |
18 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
19 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
4a94b3aa | 20 | #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn)) |
ab71cc0d DK |
21 | #define PCI_BUS_MAX 256 |
22 | #define PCI_DEVFN_MAX 256 | |
90a20dbb | 23 | #define PCI_SLOT_MAX 32 |
6fa84913 | 24 | #define PCI_FUNC_MAX 8 |
3ae80618 | 25 | |
a770dc7e | 26 | /* Class, Vendor and Device IDs from Linux's pci_ids.h */ |
c759b24f | 27 | #include "hw/pci/pci_ids.h" |
173a543b | 28 | |
a770dc7e | 29 | /* QEMU-specific Vendor and Device ID definitions */ |
6f338c34 | 30 | |
a770dc7e AL |
31 | /* IBM (0x1014) */ |
32 | #define PCI_DEVICE_ID_IBM_440GX 0x027f | |
4ebcf884 | 33 | #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
deb54399 | 34 | |
a770dc7e | 35 | /* Hitachi (0x1054) */ |
deb54399 | 36 | #define PCI_VENDOR_ID_HITACHI 0x1054 |
a770dc7e | 37 | #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e |
deb54399 | 38 | |
a770dc7e | 39 | /* Apple (0x106b) */ |
4ebcf884 BS |
40 | #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
41 | #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e | |
42 | #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f | |
4ebcf884 | 43 | #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
a770dc7e | 44 | #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f |
deb54399 | 45 | |
a770dc7e AL |
46 | /* Realtek (0x10ec) */ |
47 | #define PCI_DEVICE_ID_REALTEK_8029 0x8029 | |
deb54399 | 48 | |
a770dc7e AL |
49 | /* Xilinx (0x10ee) */ |
50 | #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 | |
deb54399 | 51 | |
a770dc7e AL |
52 | /* Marvell (0x11ab) */ |
53 | #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 | |
deb54399 | 54 | |
a770dc7e | 55 | /* QEMU/Bochs VGA (0x1234) */ |
4ebcf884 BS |
56 | #define PCI_VENDOR_ID_QEMU 0x1234 |
57 | #define PCI_DEVICE_ID_QEMU_VGA 0x1111 | |
12f983c6 | 58 | #define PCI_DEVICE_ID_QEMU_IPMI 0x1112 |
4ebcf884 | 59 | |
a770dc7e | 60 | /* VMWare (0x15ad) */ |
deb54399 AL |
61 | #define PCI_VENDOR_ID_VMWARE 0x15ad |
62 | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 | |
63 | #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 | |
64 | #define PCI_DEVICE_ID_VMWARE_NET 0x0720 | |
65 | #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 | |
881d588a | 66 | #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 |
deb54399 | 67 | #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 |
786fd2b0 | 68 | #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 |
deb54399 | 69 | |
cef3017c | 70 | /* Intel (0x8086) */ |
a770dc7e | 71 | #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 |
d6fd1e66 | 72 | #define PCI_DEVICE_ID_INTEL_82557 0x1229 |
1a5a86fb | 73 | #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 |
74c62ba8 | 74 | |
deb54399 | 75 | /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ |
d350d97d AL |
76 | #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
77 | #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 | |
78 | #define PCI_SUBDEVICE_ID_QEMU 0x1100 | |
79 | ||
80 | #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 | |
81 | #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 | |
82 | #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 | |
14d50bef | 83 | #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
973abc7f | 84 | #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 |
16c915ba | 85 | #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 |
13744bd0 | 86 | #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 |
fc0b9b0e | 87 | #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012 |
adf0748a | 88 | #define PCI_DEVICE_ID_VIRTIO_PMEM 0x1013 |
d350d97d | 89 | |
5c03a254 PB |
90 | #define PCI_VENDOR_ID_REDHAT 0x1b36 |
91 | #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 | |
92 | #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 | |
93 | #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 | |
94 | #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 | |
22773d60 | 95 | #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 |
5dcc2637 | 96 | #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 |
5aa81360 | 97 | #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 |
bf439db4 | 98 | #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008 |
40d14bef | 99 | #define PCI_DEVICE_ID_REDHAT_PXB 0x0009 |
eb6c6a60 | 100 | #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a |
02b07434 | 101 | #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b |
f7d6f3fa | 102 | #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c |
72a810f4 | 103 | #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d |
a35fe226 | 104 | #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e |
50a6fa8f | 105 | #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f |
5c03a254 PB |
106 | #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 |
107 | ||
4f8589e1 | 108 | #define FMT_PCIBUS PRIx64 |
6e355d90 | 109 | |
a7c4d9c7 MA |
110 | typedef uint64_t pcibus_t; |
111 | ||
112 | struct PCIHostDeviceAddress { | |
113 | unsigned int domain; | |
114 | unsigned int bus; | |
115 | unsigned int slot; | |
116 | unsigned int function; | |
117 | }; | |
118 | ||
87ecb68b PB |
119 | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
120 | uint32_t address, uint32_t data, int len); | |
121 | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, | |
122 | uint32_t address, int len); | |
123 | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, | |
6e355d90 | 124 | pcibus_t addr, pcibus_t size, int type); |
f90c2bcd | 125 | typedef void PCIUnregisterFunc(PCIDevice *pci_dev); |
87ecb68b | 126 | |
87ecb68b | 127 | typedef struct PCIIORegion { |
6e355d90 IY |
128 | pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ |
129 | #define PCI_BAR_UNMAPPED (~(pcibus_t)0) | |
130 | pcibus_t size; | |
87ecb68b | 131 | uint8_t type; |
79ff8cb0 | 132 | MemoryRegion *memory; |
5968eca3 | 133 | MemoryRegion *address_space; |
87ecb68b PB |
134 | } PCIIORegion; |
135 | ||
136 | #define PCI_ROM_SLOT 6 | |
137 | #define PCI_NUM_REGIONS 7 | |
138 | ||
e01fd687 AW |
139 | enum { |
140 | QEMU_PCI_VGA_MEM, | |
141 | QEMU_PCI_VGA_IO_LO, | |
142 | QEMU_PCI_VGA_IO_HI, | |
143 | QEMU_PCI_VGA_NUM_REGIONS, | |
144 | }; | |
145 | ||
146 | #define QEMU_PCI_VGA_MEM_BASE 0xa0000 | |
147 | #define QEMU_PCI_VGA_MEM_SIZE 0x20000 | |
148 | #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 | |
149 | #define QEMU_PCI_VGA_IO_LO_SIZE 0xc | |
150 | #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 | |
151 | #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 | |
152 | ||
c759b24f | 153 | #include "hw/pci/pci_regs.h" |
fb58a897 IY |
154 | |
155 | /* PCI HEADER_TYPE */ | |
6407f373 | 156 | #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 |
8098ed41 | 157 | |
b7ee1603 MT |
158 | /* Size of the standard PCI config header */ |
159 | #define PCI_CONFIG_HEADER_SIZE 0x40 | |
160 | /* Size of the standard PCI config space */ | |
161 | #define PCI_CONFIG_SPACE_SIZE 0x100 | |
98a2f30a | 162 | /* Size of the standard PCIe config space: 4KB */ |
a9f49946 | 163 | #define PCIE_CONFIG_SPACE_SIZE 0x1000 |
b7ee1603 | 164 | |
e369cad7 IY |
165 | #define PCI_NUM_PINS 4 /* A-D */ |
166 | ||
02eb84d0 MT |
167 | /* Bits in cap_present field. */ |
168 | enum { | |
e4c7d2ae IY |
169 | QEMU_PCI_CAP_MSI = 0x1, |
170 | QEMU_PCI_CAP_MSIX = 0x2, | |
171 | QEMU_PCI_CAP_EXPRESS = 0x4, | |
49823868 IY |
172 | |
173 | /* multifunction capable device */ | |
e4c7d2ae | 174 | #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 |
49823868 | 175 | QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), |
b1aeb926 | 176 | |
2a4dbaf1 | 177 | /* command register SERR bit enabled - unused since QEMU v5.0 */ |
b1aeb926 IY |
178 | #define QEMU_PCI_CAP_SERR_BITNR 4 |
179 | QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), | |
1dc324d2 MT |
180 | /* Standard hot plug controller. */ |
181 | #define QEMU_PCI_SHPC_BITNR 5 | |
182 | QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), | |
762833b3 MT |
183 | #define QEMU_PCI_SLOTID_BITNR 6 |
184 | QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), | |
f23b6bdc MA |
185 | /* PCI Express capability - Power Controller Present */ |
186 | #define QEMU_PCIE_SLTCAP_PCP_BITNR 7 | |
187 | QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), | |
6b449540 MT |
188 | /* Link active status in endpoint capability is always set */ |
189 | #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8 | |
190 | QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), | |
f03d8ea3 MA |
191 | #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 |
192 | QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), | |
02eb84d0 MT |
193 | }; |
194 | ||
40021f08 AL |
195 | #define TYPE_PCI_DEVICE "pci-device" |
196 | #define PCI_DEVICE(obj) \ | |
197 | OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) | |
198 | #define PCI_DEVICE_CLASS(klass) \ | |
199 | OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) | |
200 | #define PCI_DEVICE_GET_CLASS(obj) \ | |
201 | OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) | |
202 | ||
619f02ae EH |
203 | /* Implemented by devices that can be plugged on PCI Express buses */ |
204 | #define INTERFACE_PCIE_DEVICE "pci-express-device" | |
205 | ||
206 | /* Implemented by devices that can be plugged on Conventional PCI buses */ | |
207 | #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device" | |
208 | ||
3afa9bb4 MT |
209 | typedef struct PCIINTxRoute { |
210 | enum { | |
211 | PCI_INTX_ENABLED, | |
212 | PCI_INTX_INVERTED, | |
213 | PCI_INTX_DISABLED, | |
214 | } mode; | |
215 | int irq; | |
216 | } PCIINTxRoute; | |
217 | ||
40021f08 AL |
218 | typedef struct PCIDeviceClass { |
219 | DeviceClass parent_class; | |
220 | ||
7ee6c1e1 | 221 | void (*realize)(PCIDevice *dev, Error **errp); |
40021f08 AL |
222 | PCIUnregisterFunc *exit; |
223 | PCIConfigReadFunc *config_read; | |
224 | PCIConfigWriteFunc *config_write; | |
225 | ||
226 | uint16_t vendor_id; | |
227 | uint16_t device_id; | |
228 | uint8_t revision; | |
229 | uint16_t class_id; | |
230 | uint16_t subsystem_vendor_id; /* only for header type = 0 */ | |
231 | uint16_t subsystem_id; /* only for header type = 0 */ | |
232 | ||
233 | /* | |
234 | * pci-to-pci bridge or normal device. | |
235 | * This doesn't mean pci host switch. | |
236 | * When card bus bridge is supported, this would be enhanced. | |
237 | */ | |
91f4c995 | 238 | bool is_bridge; |
40021f08 | 239 | |
40021f08 AL |
240 | /* rom bar */ |
241 | const char *romfile; | |
242 | } PCIDeviceClass; | |
243 | ||
0ae16251 | 244 | typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); |
2cdfe53c JK |
245 | typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, |
246 | MSIMessage msg); | |
247 | typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); | |
bbef882c MT |
248 | typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, |
249 | unsigned int vector_start, | |
250 | unsigned int vector_end); | |
2cdfe53c | 251 | |
4a94b3aa PX |
252 | enum PCIReqIDType { |
253 | PCI_REQ_ID_INVALID = 0, | |
254 | PCI_REQ_ID_BDF, | |
255 | PCI_REQ_ID_SECONDARY_BUS, | |
256 | PCI_REQ_ID_MAX, | |
257 | }; | |
258 | typedef enum PCIReqIDType PCIReqIDType; | |
259 | ||
260 | struct PCIReqIDCache { | |
261 | PCIDevice *dev; | |
262 | PCIReqIDType type; | |
263 | }; | |
264 | typedef struct PCIReqIDCache PCIReqIDCache; | |
265 | ||
87ecb68b | 266 | struct PCIDevice { |
6b1b92d3 | 267 | DeviceState qdev; |
a99c4da9 | 268 | bool partially_hotplugged; |
5fa45de5 | 269 | |
87ecb68b | 270 | /* PCI config space */ |
a9f49946 | 271 | uint8_t *config; |
b7ee1603 | 272 | |
ebabb67a | 273 | /* Used to enable config checks on load. Note that writable bits are |
bd4b65ee | 274 | * never checked even if set in cmask. */ |
a9f49946 | 275 | uint8_t *cmask; |
bd4b65ee | 276 | |
b7ee1603 | 277 | /* Used to implement R/W bytes */ |
a9f49946 | 278 | uint8_t *wmask; |
87ecb68b | 279 | |
92ba5f51 IY |
280 | /* Used to implement RW1C(Write 1 to Clear) bytes */ |
281 | uint8_t *w1cmask; | |
282 | ||
6f4cbd39 | 283 | /* Used to allocate config space for capabilities. */ |
a9f49946 | 284 | uint8_t *used; |
6f4cbd39 | 285 | |
87ecb68b | 286 | /* the following fields are read only */ |
09f1bbcd | 287 | int32_t devfn; |
4a94b3aa PX |
288 | /* Cached device to fetch requester ID from, to avoid the PCI |
289 | * tree walking every time we invoke PCI request (e.g., | |
290 | * MSI). For conventional PCI root complex, this field is | |
291 | * meaningless. */ | |
292 | PCIReqIDCache requester_id_cache; | |
87ecb68b PB |
293 | char name[64]; |
294 | PCIIORegion io_regions[PCI_NUM_REGIONS]; | |
817dcc53 | 295 | AddressSpace bus_master_as; |
3716d590 | 296 | MemoryRegion bus_master_container_region; |
1c380f94 | 297 | MemoryRegion bus_master_enable_region; |
87ecb68b PB |
298 | |
299 | /* do not access the following fields */ | |
300 | PCIConfigReadFunc *config_read; | |
301 | PCIConfigWriteFunc *config_write; | |
87ecb68b | 302 | |
e01fd687 AW |
303 | /* Legacy PCI VGA regions */ |
304 | MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; | |
305 | bool has_vga; | |
306 | ||
87ecb68b | 307 | /* Current IRQ levels. Used internally by the generic PCI code. */ |
d036bb21 | 308 | uint8_t irq_state; |
02eb84d0 MT |
309 | |
310 | /* Capability bits */ | |
311 | uint32_t cap_present; | |
312 | ||
313 | /* Offset of MSI-X capability in config space */ | |
314 | uint8_t msix_cap; | |
315 | ||
316 | /* MSI-X entries */ | |
317 | int msix_entries_nr; | |
318 | ||
d35e428c AW |
319 | /* Space to store MSIX table & pending bit array */ |
320 | uint8_t *msix_table; | |
321 | uint8_t *msix_pba; | |
53f94925 AW |
322 | /* MemoryRegion container for msix exclusive BAR setup */ |
323 | MemoryRegion msix_exclusive_bar; | |
d35e428c AW |
324 | /* Memory Regions for MSIX table and pending bit entries. */ |
325 | MemoryRegion msix_table_mmio; | |
326 | MemoryRegion msix_pba_mmio; | |
02eb84d0 MT |
327 | /* Reference-count for entries actually in use by driver. */ |
328 | unsigned *msix_entry_used; | |
50322249 MT |
329 | /* MSIX function mask set or MSIX disabled */ |
330 | bool msix_function_masked; | |
f16c4abf JQ |
331 | /* Version id needed for VMState */ |
332 | int32_t version_id; | |
c2039bd0 | 333 | |
e4c7d2ae IY |
334 | /* Offset of MSI capability in config space */ |
335 | uint8_t msi_cap; | |
336 | ||
0428527c IY |
337 | /* PCI Express */ |
338 | PCIExpressDevice exp; | |
339 | ||
1dc324d2 MT |
340 | /* SHPC */ |
341 | SHPCDevice *shpc; | |
342 | ||
c2039bd0 | 343 | /* Location of option rom */ |
8c52c8f3 | 344 | char *romfile; |
14caaf7f AK |
345 | bool has_rom; |
346 | MemoryRegion rom; | |
88169ddf | 347 | uint32_t rom_bar; |
2cdfe53c | 348 | |
0ae16251 JK |
349 | /* INTx routing notifier */ |
350 | PCIINTxRoutingNotifier intx_routing_notifier; | |
351 | ||
2cdfe53c JK |
352 | /* MSI-X notifiers */ |
353 | MSIVectorUseNotifier msix_vector_use_notifier; | |
354 | MSIVectorReleaseNotifier msix_vector_release_notifier; | |
bbef882c | 355 | MSIVectorPollNotifier msix_vector_poll_notifier; |
4f5b6a05 JF |
356 | |
357 | /* ID of standby device in net_failover pair */ | |
358 | char *failover_pair_id; | |
87ecb68b PB |
359 | }; |
360 | ||
e824b2cc AK |
361 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
362 | uint8_t attr, MemoryRegion *memory); | |
e01fd687 AW |
363 | void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, |
364 | MemoryRegion *io_lo, MemoryRegion *io_hi); | |
365 | void pci_unregister_vga(PCIDevice *pci_dev); | |
16a96f28 | 366 | pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); |
87ecb68b | 367 | |
ca77089d | 368 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, |
9a7c2a59 MZ |
369 | uint8_t offset, uint8_t size, |
370 | Error **errp); | |
6f4cbd39 MT |
371 | |
372 | void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); | |
373 | ||
6f4cbd39 MT |
374 | uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); |
375 | ||
376 | ||
87ecb68b PB |
377 | uint32_t pci_default_read_config(PCIDevice *d, |
378 | uint32_t address, int len); | |
379 | void pci_default_write_config(PCIDevice *d, | |
380 | uint32_t address, uint32_t val, int len); | |
381 | void pci_device_save(PCIDevice *s, QEMUFile *f); | |
382 | int pci_device_load(PCIDevice *s, QEMUFile *f); | |
f5e6fed8 | 383 | MemoryRegion *pci_address_space(PCIDevice *dev); |
e11d6439 | 384 | MemoryRegion *pci_address_space_io(PCIDevice *dev); |
87ecb68b | 385 | |
cf8c704d MR |
386 | /* |
387 | * Should not normally be used by devices. For use by sPAPR target | |
388 | * where QEMU emulates firmware. | |
389 | */ | |
390 | int pci_bar(PCIDevice *d, int reg); | |
391 | ||
5d4e84c8 | 392 | typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); |
87ecb68b | 393 | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
3afa9bb4 | 394 | typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); |
e927d487 | 395 | |
cf09458d AW |
396 | #define TYPE_PCI_BUS "PCI" |
397 | #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS) | |
ce6a28ee MA |
398 | #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS) |
399 | #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS) | |
cf09458d AW |
400 | #define TYPE_PCIE_BUS "PCIE" |
401 | ||
8c0bf9e2 | 402 | bool pci_bus_is_express(PCIBus *bus); |
1c685a90 | 403 | |
1115ff6d DG |
404 | void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, |
405 | const char *name, | |
406 | MemoryRegion *address_space_mem, | |
407 | MemoryRegion *address_space_io, | |
408 | uint8_t devfn_min, const char *typename); | |
409 | PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, | |
aee97b84 AK |
410 | MemoryRegion *address_space_mem, |
411 | MemoryRegion *address_space_io, | |
60a0e443 | 412 | uint8_t devfn_min, const char *typename); |
c13ee169 | 413 | void pci_root_bus_cleanup(PCIBus *bus); |
21eea4b3 GH |
414 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
415 | void *irq_opaque, int nirq); | |
c13ee169 | 416 | void pci_bus_irqs_cleanup(PCIBus *bus); |
9ddf8437 | 417 | int pci_bus_get_irq_level(PCIBus *bus, int irq_num); |
91e56159 | 418 | /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ |
e8ec4adf GK |
419 | static inline int pci_swizzle(int slot, int pin) |
420 | { | |
421 | return (slot + pin) % PCI_NUM_PINS; | |
422 | } | |
91e56159 | 423 | int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); |
1115ff6d DG |
424 | PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, |
425 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
426 | void *irq_opaque, | |
427 | MemoryRegion *address_space_mem, | |
428 | MemoryRegion *address_space_io, | |
429 | uint8_t devfn_min, int nirq, | |
430 | const char *typename); | |
c13ee169 | 431 | void pci_unregister_root_bus(PCIBus *bus); |
3afa9bb4 MT |
432 | void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); |
433 | PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); | |
d6e65d54 | 434 | bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); |
0ae16251 JK |
435 | void pci_bus_fire_intx_routing_notifier(PCIBus *bus); |
436 | void pci_device_set_intx_routing_notifier(PCIDevice *dev, | |
437 | PCIINTxRoutingNotifier notifier); | |
0ead87c8 | 438 | void pci_device_reset(PCIDevice *dev); |
87ecb68b | 439 | |
29b358f9 DG |
440 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, |
441 | const char *default_model, | |
07caea31 | 442 | const char *default_devaddr); |
129d42fb AJ |
443 | |
444 | PCIDevice *pci_vga_init(PCIBus *bus); | |
445 | ||
fd56e061 DG |
446 | static inline PCIBus *pci_get_bus(const PCIDevice *dev) |
447 | { | |
448 | return PCI_BUS(qdev_get_parent_bus(DEVICE(dev))); | |
449 | } | |
87ecb68b | 450 | int pci_bus_num(PCIBus *s); |
cdc57472 DG |
451 | static inline int pci_dev_bus_num(const PCIDevice *dev) |
452 | { | |
fd56e061 | 453 | return pci_bus_num(pci_get_bus(dev)); |
cdc57472 DG |
454 | } |
455 | ||
6a3042b2 | 456 | int pci_bus_numa_node(PCIBus *bus); |
7aa8cbb9 AP |
457 | void pci_for_each_device(PCIBus *bus, int bus_num, |
458 | void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), | |
459 | void *opaque); | |
a8eeafda GK |
460 | void pci_for_each_device_reverse(PCIBus *bus, int bus_num, |
461 | void (*fn)(PCIBus *bus, PCIDevice *d, | |
462 | void *opaque), | |
463 | void *opaque); | |
eb0acfdd MT |
464 | void pci_for_each_bus_depth_first(PCIBus *bus, |
465 | void *(*begin)(PCIBus *bus, void *parent_state), | |
466 | void (*end)(PCIBus *bus, void *state), | |
467 | void *parent_state); | |
3f1e1478 | 468 | PCIDevice *pci_get_function_0(PCIDevice *pci_dev); |
eb0acfdd MT |
469 | |
470 | /* Use this wrapper when specific scan order is not required. */ | |
471 | static inline | |
472 | void pci_for_each_bus(PCIBus *bus, | |
473 | void (*fn)(PCIBus *bus, void *opaque), | |
474 | void *opaque) | |
475 | { | |
476 | pci_for_each_bus_depth_first(bus, NULL, fn, opaque); | |
477 | } | |
478 | ||
c473d18d | 479 | PCIBus *pci_device_root_bus(const PCIDevice *d); |
568f0690 | 480 | const char *pci_root_bus_path(PCIDevice *dev); |
5256d8bf | 481 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); |
f3006dd1 | 482 | int pci_qdev_find_device(const char *id, PCIDevice **pdev); |
43864069 | 483 | void pci_bus_get_w64_range(PCIBus *bus, Range *range); |
87ecb68b | 484 | |
4c92325b IY |
485 | void pci_device_deassert_intx(PCIDevice *dev); |
486 | ||
e00387d5 | 487 | typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int); |
5fa45de5 | 488 | |
9eda7d37 | 489 | AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); |
e00387d5 | 490 | void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque); |
5fa45de5 | 491 | |
64d50b8b MT |
492 | static inline void |
493 | pci_set_byte(uint8_t *config, uint8_t val) | |
494 | { | |
495 | *config = val; | |
496 | } | |
497 | ||
498 | static inline uint8_t | |
cb95c2e4 | 499 | pci_get_byte(const uint8_t *config) |
64d50b8b MT |
500 | { |
501 | return *config; | |
502 | } | |
503 | ||
14e12559 MT |
504 | static inline void |
505 | pci_set_word(uint8_t *config, uint16_t val) | |
506 | { | |
587ae227 | 507 | stw_le_p(config, val); |
14e12559 MT |
508 | } |
509 | ||
510 | static inline uint16_t | |
cb95c2e4 | 511 | pci_get_word(const uint8_t *config) |
14e12559 | 512 | { |
c65e5de9 | 513 | return lduw_le_p(config); |
14e12559 MT |
514 | } |
515 | ||
516 | static inline void | |
517 | pci_set_long(uint8_t *config, uint32_t val) | |
518 | { | |
6e931878 | 519 | stl_le_p(config, val); |
14e12559 MT |
520 | } |
521 | ||
522 | static inline uint32_t | |
cb95c2e4 | 523 | pci_get_long(const uint8_t *config) |
14e12559 | 524 | { |
f567656a | 525 | return ldl_le_p(config); |
14e12559 MT |
526 | } |
527 | ||
059a65f3 DF |
528 | /* |
529 | * PCI capabilities and/or their fields | |
530 | * are generally DWORD aligned only so | |
531 | * mechanism used by pci_set/get_quad() | |
532 | * must be tolerant to unaligned pointers | |
533 | * | |
534 | */ | |
fb5ce7d2 IY |
535 | static inline void |
536 | pci_set_quad(uint8_t *config, uint64_t val) | |
537 | { | |
059a65f3 | 538 | stq_le_p(config, val); |
fb5ce7d2 IY |
539 | } |
540 | ||
541 | static inline uint64_t | |
cb95c2e4 | 542 | pci_get_quad(const uint8_t *config) |
fb5ce7d2 | 543 | { |
059a65f3 | 544 | return ldq_le_p(config); |
fb5ce7d2 IY |
545 | } |
546 | ||
deb54399 AL |
547 | static inline void |
548 | pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) | |
549 | { | |
14e12559 | 550 | pci_set_word(&pci_config[PCI_VENDOR_ID], val); |
deb54399 AL |
551 | } |
552 | ||
553 | static inline void | |
554 | pci_config_set_device_id(uint8_t *pci_config, uint16_t val) | |
555 | { | |
14e12559 | 556 | pci_set_word(&pci_config[PCI_DEVICE_ID], val); |
deb54399 AL |
557 | } |
558 | ||
cf602c7b IE |
559 | static inline void |
560 | pci_config_set_revision(uint8_t *pci_config, uint8_t val) | |
561 | { | |
562 | pci_set_byte(&pci_config[PCI_REVISION_ID], val); | |
563 | } | |
564 | ||
173a543b BS |
565 | static inline void |
566 | pci_config_set_class(uint8_t *pci_config, uint16_t val) | |
567 | { | |
14e12559 | 568 | pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); |
173a543b BS |
569 | } |
570 | ||
cf602c7b IE |
571 | static inline void |
572 | pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) | |
573 | { | |
574 | pci_set_byte(&pci_config[PCI_CLASS_PROG], val); | |
575 | } | |
576 | ||
577 | static inline void | |
578 | pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) | |
579 | { | |
580 | pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); | |
581 | } | |
582 | ||
aabcf526 IY |
583 | /* |
584 | * helper functions to do bit mask operation on configuration space. | |
585 | * Just to set bit, use test-and-set and discard returned value. | |
586 | * Just to clear bit, use test-and-clear and discard returned value. | |
587 | * NOTE: They aren't atomic. | |
588 | */ | |
589 | static inline uint8_t | |
590 | pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) | |
591 | { | |
592 | uint8_t val = pci_get_byte(config); | |
593 | pci_set_byte(config, val & ~mask); | |
594 | return val & mask; | |
595 | } | |
596 | ||
597 | static inline uint8_t | |
598 | pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) | |
599 | { | |
600 | uint8_t val = pci_get_byte(config); | |
601 | pci_set_byte(config, val | mask); | |
602 | return val & mask; | |
603 | } | |
604 | ||
605 | static inline uint16_t | |
606 | pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) | |
607 | { | |
608 | uint16_t val = pci_get_word(config); | |
609 | pci_set_word(config, val & ~mask); | |
610 | return val & mask; | |
611 | } | |
612 | ||
613 | static inline uint16_t | |
614 | pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) | |
615 | { | |
616 | uint16_t val = pci_get_word(config); | |
617 | pci_set_word(config, val | mask); | |
618 | return val & mask; | |
619 | } | |
620 | ||
621 | static inline uint32_t | |
622 | pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) | |
623 | { | |
624 | uint32_t val = pci_get_long(config); | |
625 | pci_set_long(config, val & ~mask); | |
626 | return val & mask; | |
627 | } | |
628 | ||
629 | static inline uint32_t | |
630 | pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) | |
631 | { | |
632 | uint32_t val = pci_get_long(config); | |
633 | pci_set_long(config, val | mask); | |
634 | return val & mask; | |
635 | } | |
636 | ||
637 | static inline uint64_t | |
638 | pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) | |
639 | { | |
640 | uint64_t val = pci_get_quad(config); | |
641 | pci_set_quad(config, val & ~mask); | |
642 | return val & mask; | |
643 | } | |
644 | ||
645 | static inline uint64_t | |
646 | pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) | |
647 | { | |
648 | uint64_t val = pci_get_quad(config); | |
649 | pci_set_quad(config, val | mask); | |
650 | return val & mask; | |
651 | } | |
652 | ||
c9f50cea MT |
653 | /* Access a register specified by a mask */ |
654 | static inline void | |
655 | pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) | |
656 | { | |
657 | uint8_t val = pci_get_byte(config); | |
786a4ea8 | 658 | uint8_t rval = reg << ctz32(mask); |
c9f50cea MT |
659 | pci_set_byte(config, (~mask & val) | (mask & rval)); |
660 | } | |
661 | ||
662 | static inline uint8_t | |
663 | pci_get_byte_by_mask(uint8_t *config, uint8_t mask) | |
664 | { | |
665 | uint8_t val = pci_get_byte(config); | |
786a4ea8 | 666 | return (val & mask) >> ctz32(mask); |
c9f50cea MT |
667 | } |
668 | ||
669 | static inline void | |
670 | pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) | |
671 | { | |
672 | uint16_t val = pci_get_word(config); | |
786a4ea8 | 673 | uint16_t rval = reg << ctz32(mask); |
c9f50cea MT |
674 | pci_set_word(config, (~mask & val) | (mask & rval)); |
675 | } | |
676 | ||
677 | static inline uint16_t | |
678 | pci_get_word_by_mask(uint8_t *config, uint16_t mask) | |
679 | { | |
680 | uint16_t val = pci_get_word(config); | |
786a4ea8 | 681 | return (val & mask) >> ctz32(mask); |
c9f50cea MT |
682 | } |
683 | ||
684 | static inline void | |
685 | pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) | |
686 | { | |
687 | uint32_t val = pci_get_long(config); | |
786a4ea8 | 688 | uint32_t rval = reg << ctz32(mask); |
c9f50cea MT |
689 | pci_set_long(config, (~mask & val) | (mask & rval)); |
690 | } | |
691 | ||
692 | static inline uint32_t | |
693 | pci_get_long_by_mask(uint8_t *config, uint32_t mask) | |
694 | { | |
695 | uint32_t val = pci_get_long(config); | |
786a4ea8 | 696 | return (val & mask) >> ctz32(mask); |
c9f50cea MT |
697 | } |
698 | ||
699 | static inline void | |
700 | pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) | |
701 | { | |
702 | uint64_t val = pci_get_quad(config); | |
786a4ea8 | 703 | uint64_t rval = reg << ctz32(mask); |
c9f50cea MT |
704 | pci_set_quad(config, (~mask & val) | (mask & rval)); |
705 | } | |
706 | ||
707 | static inline uint64_t | |
708 | pci_get_quad_by_mask(uint8_t *config, uint64_t mask) | |
709 | { | |
710 | uint64_t val = pci_get_quad(config); | |
786a4ea8 | 711 | return (val & mask) >> ctz32(mask); |
c9f50cea MT |
712 | } |
713 | ||
49823868 IY |
714 | PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
715 | const char *name); | |
716 | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, | |
717 | bool multifunction, | |
718 | const char *name); | |
499cf102 | 719 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); |
6b1b92d3 PB |
720 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); |
721 | ||
f74a4f3a | 722 | void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev); |
a64aa578 | 723 | |
d98f08f5 MA |
724 | qemu_irq pci_allocate_irq(PCIDevice *pci_dev); |
725 | void pci_set_irq(PCIDevice *pci_dev, int level); | |
726 | ||
727 | static inline void pci_irq_assert(PCIDevice *pci_dev) | |
728 | { | |
729 | pci_set_irq(pci_dev, 1); | |
730 | } | |
731 | ||
732 | static inline void pci_irq_deassert(PCIDevice *pci_dev) | |
733 | { | |
734 | pci_set_irq(pci_dev, 0); | |
735 | } | |
736 | ||
737 | /* | |
738 | * FIXME: PCI does not work this way. | |
739 | * All the callers to this method should be fixed. | |
740 | */ | |
741 | static inline void pci_irq_pulse(PCIDevice *pci_dev) | |
742 | { | |
743 | pci_irq_assert(pci_dev); | |
744 | pci_irq_deassert(pci_dev); | |
745 | } | |
746 | ||
3c18685f | 747 | static inline int pci_is_express(const PCIDevice *d) |
a9f49946 IY |
748 | { |
749 | return d->cap_present & QEMU_PCI_CAP_EXPRESS; | |
750 | } | |
751 | ||
727b4866 AW |
752 | static inline int pci_is_express_downstream_port(const PCIDevice *d) |
753 | { | |
754 | uint8_t type; | |
755 | ||
756 | if (!pci_is_express(d) || !d->exp.exp_cap) { | |
757 | return 0; | |
758 | } | |
759 | ||
760 | type = pcie_cap_get_type(d); | |
761 | ||
762 | return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT; | |
763 | } | |
764 | ||
3c18685f | 765 | static inline uint32_t pci_config_size(const PCIDevice *d) |
a9f49946 IY |
766 | { |
767 | return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; | |
768 | } | |
769 | ||
4a94b3aa | 770 | static inline uint16_t pci_get_bdf(PCIDevice *dev) |
a05f686f | 771 | { |
fd56e061 | 772 | return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn); |
a05f686f PF |
773 | } |
774 | ||
4a94b3aa PX |
775 | uint16_t pci_requester_id(PCIDevice *dev); |
776 | ||
ec174575 | 777 | /* DMA access functions */ |
df32fd1c | 778 | static inline AddressSpace *pci_get_address_space(PCIDevice *dev) |
d86a77f8 | 779 | { |
df32fd1c | 780 | return &dev->bus_master_as; |
d86a77f8 DG |
781 | } |
782 | ||
ec174575 DG |
783 | static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, |
784 | void *buf, dma_addr_t len, DMADirection dir) | |
785 | { | |
df32fd1c | 786 | dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); |
ec174575 DG |
787 | return 0; |
788 | } | |
789 | ||
790 | static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, | |
791 | void *buf, dma_addr_t len) | |
792 | { | |
793 | return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); | |
794 | } | |
795 | ||
796 | static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, | |
797 | const void *buf, dma_addr_t len) | |
798 | { | |
799 | return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); | |
800 | } | |
801 | ||
802 | #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ | |
803 | static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ | |
804 | dma_addr_t addr) \ | |
805 | { \ | |
df32fd1c | 806 | return ld##_l##_dma(pci_get_address_space(dev), addr); \ |
ec174575 DG |
807 | } \ |
808 | static inline void st##_s##_pci_dma(PCIDevice *dev, \ | |
d86a77f8 | 809 | dma_addr_t addr, uint##_bits##_t val) \ |
ec174575 | 810 | { \ |
df32fd1c | 811 | st##_s##_dma(pci_get_address_space(dev), addr, val); \ |
ec174575 DG |
812 | } |
813 | ||
814 | PCI_DMA_DEFINE_LDST(ub, b, 8); | |
815 | PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) | |
816 | PCI_DMA_DEFINE_LDST(l_le, l_le, 32); | |
817 | PCI_DMA_DEFINE_LDST(q_le, q_le, 64); | |
818 | PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) | |
819 | PCI_DMA_DEFINE_LDST(l_be, l_be, 32); | |
820 | PCI_DMA_DEFINE_LDST(q_be, q_be, 64); | |
821 | ||
822 | #undef PCI_DMA_DEFINE_LDST | |
823 | ||
824 | static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, | |
825 | dma_addr_t *plen, DMADirection dir) | |
826 | { | |
ec174575 DG |
827 | void *buf; |
828 | ||
df32fd1c | 829 | buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir); |
ec174575 DG |
830 | return buf; |
831 | } | |
832 | ||
833 | static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, | |
834 | DMADirection dir, dma_addr_t access_len) | |
835 | { | |
df32fd1c | 836 | dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len); |
ec174575 DG |
837 | } |
838 | ||
839 | static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, | |
840 | int alloc_hint) | |
841 | { | |
f487b677 | 842 | qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev)); |
ec174575 DG |
843 | } |
844 | ||
701a8f76 PB |
845 | extern const VMStateDescription vmstate_pci_device; |
846 | ||
847 | #define VMSTATE_PCI_DEVICE(_field, _state) { \ | |
848 | .name = (stringify(_field)), \ | |
849 | .size = sizeof(PCIDevice), \ | |
850 | .vmsd = &vmstate_pci_device, \ | |
851 | .flags = VMS_STRUCT, \ | |
852 | .offset = vmstate_offset_value(_state, _field, PCIDevice), \ | |
853 | } | |
854 | ||
855 | #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ | |
856 | .name = (stringify(_field)), \ | |
857 | .size = sizeof(PCIDevice), \ | |
858 | .vmsd = &vmstate_pci_device, \ | |
859 | .flags = VMS_STRUCT|VMS_POINTER, \ | |
860 | .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ | |
861 | } | |
862 | ||
e1d4fb2d PX |
863 | MSIMessage pci_get_msi_message(PCIDevice *dev, int vector); |
864 | ||
87ecb68b | 865 | #endif |