[mirror_qemu.git] / include / hw / s390x / css.h

/*
 * Channel subsystem structures and definitions.
 *
 * Copyright 2012 IBM Corp.
 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or (at
 * your option) any later version. See the COPYING file in the top-level
 * directory.
 */

#ifndef CSS_H
#define CSS_H

#include "cpu.h"
#include "hw/s390x/adapter.h"
#include "hw/s390x/s390_flic.h"
#include "hw/s390x/ioinst.h"
#include "sysemu/kvm.h"

/* Channel subsystem constants. */
#define MAX_DEVNO 65535
#define MAX_SCHID 65535
#define MAX_SSID 3
#define MAX_CSSID 255
#define MAX_CHPID 255

#define MAX_ISC 7

#define MAX_CIWS 62

#define VIRTUAL_CSSID 0xfe
#define VIRTIO_CCW_CHPID 0   /* used by convention */

typedef struct CIW {
    uint8_t type;
    uint8_t command;
    uint16_t count;
} QEMU_PACKED CIW;

typedef struct SenseId {
    /* common part */
    uint8_t reserved;        /* always 0x'FF' */
    uint16_t cu_type;        /* control unit type */
    uint8_t cu_model;        /* control unit model */
    uint16_t dev_type;       /* device type */
    uint8_t dev_model;       /* device model */
    uint8_t unused;          /* padding byte */
    /* extended part */
    CIW ciw[MAX_CIWS];       /* variable # of CIWs */
} SenseId;                   /* Note: No QEMU_PACKED due to unaligned members */

/* Channel measurements, from linux/drivers/s390/cio/cmf.c. */
typedef struct CMB {
    uint16_t ssch_rsch_count;
    uint16_t sample_count;
    uint32_t device_connect_time;
    uint32_t function_pending_time;
    uint32_t device_disconnect_time;
    uint32_t control_unit_queuing_time;
    uint32_t device_active_only_time;
    uint32_t reserved[2];
} QEMU_PACKED CMB;

typedef struct CMBE {
    uint32_t ssch_rsch_count;
    uint32_t sample_count;
    uint32_t device_connect_time;
    uint32_t function_pending_time;
    uint32_t device_disconnect_time;
    uint32_t control_unit_queuing_time;
    uint32_t device_active_only_time;
    uint32_t device_busy_time;
    uint32_t initial_command_response_time;
    uint32_t reserved[7];
} QEMU_PACKED CMBE;

typedef enum CcwDataStreamOp {
    CDS_OP_R = 0, /* read, false when used as is_write */
    CDS_OP_W = 1, /* write, true when used as is_write */
    CDS_OP_A = 2  /* advance, should not be used as is_write */
} CcwDataStreamOp;

/* normal usage is via SuchchDev.cds instead of instantiating */
typedef struct CcwDataStream {
#define CDS_F_IDA   0x01
#define CDS_F_MIDA  0x02
#define CDS_F_I2K   0x04
#define CDS_F_C64   0x08
#define CDS_F_FMT   0x10 /* CCW format-1 */
#define CDS_F_STREAM_BROKEN  0x80
    uint8_t flags;
    uint8_t at_idaw;
    uint16_t at_byte;
    uint16_t count;
    uint32_t cda_orig;
    int (*op_handler)(struct CcwDataStream *cds, void *buff, int len,
                      CcwDataStreamOp op);
    hwaddr cda;
    bool do_skip;
} CcwDataStream;

/*
 * IO instructions conclude according to this. Currently we have only
 * cc codes. Valid values are 0, 1, 2, 3 and the generic semantic for
 * IO instructions is described briefly. For more details consult the PoP.
 */
typedef enum IOInstEnding {
    /* produced expected result */
    IOINST_CC_EXPECTED = 0,
    /* status conditions were present or produced alternate result */
    IOINST_CC_STATUS_PRESENT = 1,
    /* inst. ineffective because busy with previously initiated function */
    IOINST_CC_BUSY = 2,
    /* inst. ineffective because not operational */
    IOINST_CC_NOT_OPERATIONAL = 3
} IOInstEnding;

typedef struct SubchDev SubchDev;
struct SubchDev {
    /* channel-subsystem related things: */
    SCHIB curr_status;           /* Needs alignment and thus must come first */
    ORB orb;
    uint8_t cssid;
    uint8_t ssid;
    uint16_t schid;
    uint16_t devno;
    uint8_t sense_data[32];
    hwaddr channel_prog;
    CCW1 last_cmd;
    bool last_cmd_valid;
    bool ccw_fmt_1;
    bool thinint_active;
    uint8_t ccw_no_data_cnt;
    uint16_t migrated_schid; /* used for missmatch detection */
    CcwDataStream cds;
    /* transport-provided data: */
    int (*ccw_cb) (SubchDev *, CCW1);
    void (*disable_cb)(SubchDev *);
    IOInstEnding (*do_subchannel_work) (SubchDev *);
    SenseId id;
    void *driver_data;
};

static inline void sch_gen_unit_exception(SubchDev *sch)
{
    sch->curr_status.scsw.ctrl &= ~SCSW_ACTL_START_PEND;
    sch->curr_status.scsw.ctrl |= SCSW_STCTL_PRIMARY |
                                  SCSW_STCTL_SECONDARY |
                                  SCSW_STCTL_ALERT |
                                  SCSW_STCTL_STATUS_PEND;
    sch->curr_status.scsw.cpa = sch->channel_prog + 8;
    sch->curr_status.scsw.dstat =  SCSW_DSTAT_UNIT_EXCEP;
}

extern const VMStateDescription vmstate_subch_dev;

/*
 * Identify a device within the channel subsystem.
 * Note that this can be used to identify either the subchannel or
 * the attached I/O device, as there's always one I/O device per
 * subchannel.
 */
typedef struct CssDevId {
    uint8_t cssid;
    uint8_t ssid;
    uint16_t devid;
    bool valid;
} CssDevId;

extern const PropertyInfo css_devid_propinfo;

#define DEFINE_PROP_CSS_DEV_ID(_n, _s, _f) \
    DEFINE_PROP(_n, _s, _f, css_devid_propinfo, CssDevId)

typedef struct IndAddr {
    hwaddr addr;
    uint64_t map;
    unsigned long refcnt;
    int32_t len;
    QTAILQ_ENTRY(IndAddr) sibling;
} IndAddr;

extern const VMStateDescription vmstate_ind_addr;

#define VMSTATE_PTR_TO_IND_ADDR(_f, _s)                                   \
    VMSTATE_STRUCT(_f, _s, 1, vmstate_ind_addr, IndAddr*)

IndAddr *get_indicator(hwaddr ind_addr, int len);
void release_indicator(AdapterInfo *adapter, IndAddr *indicator);
int map_indicator(AdapterInfo *adapter, IndAddr *indicator);

typedef SubchDev *(*css_subch_cb_func)(uint8_t m, uint8_t cssid, uint8_t ssid,
                                       uint16_t schid);
int css_create_css_image(uint8_t cssid, bool default_image);
bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno);
void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid,
                      uint16_t devno, SubchDev *sch);
void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type);
int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id);
unsigned int css_find_free_chpid(uint8_t cssid);
uint16_t css_build_subchannel_id(SubchDev *sch);
void copy_scsw_to_guest(SCSW *dest, const SCSW *src);
void css_inject_io_interrupt(SubchDev *sch);
void css_reset(void);
void css_reset_sch(SubchDev *sch);
void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited,
                   int chain, uint16_t rsid);
void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid,
                           int hotplugged, int add);
void css_generate_chp_crws(uint8_t cssid, uint8_t chpid);
void css_generate_css_crws(uint8_t cssid);
void css_clear_sei_pending(void);
IOInstEnding s390_ccw_cmd_request(SubchDev *sch);
IOInstEnding do_subchannel_work_virtual(SubchDev *sub);
IOInstEnding do_subchannel_work_passthrough(SubchDev *sub);

int s390_ccw_halt(SubchDev *sch);
int s390_ccw_clear(SubchDev *sch);

typedef enum {
    CSS_IO_ADAPTER_VIRTIO = 0,
    CSS_IO_ADAPTER_PCI = 1,
    CSS_IO_ADAPTER_TYPE_NUMS,
} CssIoAdapterType;

void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc);
int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode);
uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc);
void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable,
                              uint8_t flags, Error **errp);

#ifndef CONFIG_KVM
#define S390_ADAPTER_SUPPRESSIBLE 0x01
#else
#define S390_ADAPTER_SUPPRESSIBLE KVM_S390_ADAPTER_SUPPRESSIBLE
#endif

#ifndef CONFIG_USER_ONLY
SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
                         uint16_t schid);
bool css_subch_visible(SubchDev *sch);
void css_conditional_io_interrupt(SubchDev *sch);
int css_do_stsch(SubchDev *sch, SCHIB *schib);
bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
IOInstEnding css_do_msch(SubchDev *sch, const SCHIB *schib);
IOInstEnding css_do_xsch(SubchDev *sch);
IOInstEnding css_do_csch(SubchDev *sch);
IOInstEnding css_do_hsch(SubchDev *sch);
IOInstEnding css_do_ssch(SubchDev *sch, ORB *orb);
int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
void css_do_tsch_update_subch(SubchDev *sch);
int css_do_stcrw(CRW *crw);
void css_undo_stcrw(CRW *crw);
int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
                         int rfmt, void *buf);
void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
int css_enable_mcsse(void);
int css_enable_mss(void);
IOInstEnding css_do_rsch(SubchDev *sch);
int css_do_rchp(uint8_t cssid, uint8_t chpid);
bool css_present(uint8_t cssid);
#endif

extern const PropertyInfo css_devid_ro_propinfo;

#define DEFINE_PROP_CSS_DEV_ID_RO(_n, _s, _f) \
    DEFINE_PROP(_n, _s, _f, css_devid_ro_propinfo, CssDevId)

/**
 * Create a subchannel for the given bus id.
 *
 * If @p bus_id is valid, verify that it is not already in use, and find a
 * free devno for it.
 * If @p bus_id is not valid find a free subchannel id and device number
 * across all subchannel sets and all css images starting from the default
 * css image.
 *
 * If either of the former actions succeed, allocate a subchannel structure,
 * initialise it with the bus id, subchannel id and device number, register
 * it with the CSS and return it. Otherwise return NULL.
 *
 * The caller becomes owner of the returned subchannel structure and
 * is responsible for unregistering and freeing it.
 */
SubchDev *css_create_sch(CssDevId bus_id, Error **errp);

/** Turn on css migration */
void css_register_vmstate(void);


void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb);

static inline void ccw_dstream_rewind(CcwDataStream *cds)
{
    cds->at_byte = 0;
    cds->at_idaw = 0;
    cds->cda = cds->cda_orig;
}

static inline bool ccw_dstream_good(CcwDataStream *cds)
{
    return !(cds->flags & CDS_F_STREAM_BROKEN);
}

static inline uint16_t ccw_dstream_residual_count(CcwDataStream *cds)
{
    return cds->count - cds->at_byte;
}

static inline uint16_t ccw_dstream_avail(CcwDataStream *cds)
{
    return ccw_dstream_good(cds) ? ccw_dstream_residual_count(cds) : 0;
}

static inline int ccw_dstream_advance(CcwDataStream *cds, int len)
{
    return cds->op_handler(cds, NULL, len, CDS_OP_A);
}

static inline int ccw_dstream_write_buf(CcwDataStream *cds, void *buff, int len)
{
    return cds->op_handler(cds, buff, len, CDS_OP_W);
}

static inline int ccw_dstream_read_buf(CcwDataStream *cds, void *buff, int len)
{
    return cds->op_handler(cds, buff, len, CDS_OP_R);
}

#define ccw_dstream_read(cds, v) ccw_dstream_read_buf((cds), &(v), sizeof(v))
#define ccw_dstream_write(cds, v) ccw_dstream_write_buf((cds), &(v), sizeof(v))

#endif
Commit	Line	Data
df1fe5bb CH	1	/*
	2	* Channel subsystem structures and definitions.
	3	*
	4	* Copyright 2012 IBM Corp.
	5	* Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
	6	*
	7	* This work is licensed under the terms of the GNU GPL, version 2 or (at
	8	* your option) any later version. See the COPYING file in the top-level
	9	* directory.
	10	*/
	11
	12	#ifndef CSS_H
	13	#define CSS_H
	14
2283f4d6	15	#include "cpu.h"
a28d8391 YMZ	16	#include "hw/s390x/adapter.h"
a28d8391 YMZ	17	#include "hw/s390x/s390_flic.h"
bd3f16ac	18	#include "hw/s390x/ioinst.h"
f16bbb9b	19	#include "sysemu/kvm.h"
df1fe5bb CH	20
df1fe5bb CH	21	/* Channel subsystem constants. */
cf249935	22	#define MAX_DEVNO 65535
df1fe5bb CH	23	#define MAX_SCHID 65535
df1fe5bb CH	24	#define MAX_SSID 3
882b3b97	25	#define MAX_CSSID 255
df1fe5bb CH	26	#define MAX_CHPID 255
df1fe5bb CH	27
dde522bb FL	28	#define MAX_ISC 7
dde522bb FL	29
df1fe5bb CH	30	#define MAX_CIWS 62
df1fe5bb CH	31
cf249935	32	#define VIRTUAL_CSSID 0xfe
6c15e9bf	33	#define VIRTIO_CCW_CHPID 0 /* used by convention */
cf249935	34
df1fe5bb CH	35	typedef struct CIW {
	36	uint8_t type;
	37	uint8_t command;
	38	uint16_t count;
	39	} QEMU_PACKED CIW;
	40
	41	typedef struct SenseId {
	42	/* common part */
	43	uint8_t reserved; /* always 0x'FF' */
	44	uint16_t cu_type; /* control unit type */
	45	uint8_t cu_model; /* control unit model */
	46	uint16_t dev_type; /* device type */
	47	uint8_t dev_model; /* device model */
	48	uint8_t unused; /* padding byte */
	49	/* extended part */
	50	CIW ciw[MAX_CIWS]; /* variable # of CIWs */
729315eb	51	} SenseId; /* Note: No QEMU_PACKED due to unaligned members */
df1fe5bb CH	52
	53	/* Channel measurements, from linux/drivers/s390/cio/cmf.c. */
	54	typedef struct CMB {
	55	uint16_t ssch_rsch_count;
	56	uint16_t sample_count;
	57	uint32_t device_connect_time;
	58	uint32_t function_pending_time;
	59	uint32_t device_disconnect_time;
	60	uint32_t control_unit_queuing_time;
	61	uint32_t device_active_only_time;
	62	uint32_t reserved[2];
	63	} QEMU_PACKED CMB;
	64
	65	typedef struct CMBE {
	66	uint32_t ssch_rsch_count;
	67	uint32_t sample_count;
	68	uint32_t device_connect_time;
	69	uint32_t function_pending_time;
	70	uint32_t device_disconnect_time;
	71	uint32_t control_unit_queuing_time;
	72	uint32_t device_active_only_time;
	73	uint32_t device_busy_time;
	74	uint32_t initial_command_response_time;
	75	uint32_t reserved[7];
	76	} QEMU_PACKED CMBE;
	77
57065a70 HP	78	typedef enum CcwDataStreamOp {
	79	CDS_OP_R = 0, /* read, false when used as is_write */
	80	CDS_OP_W = 1, /* write, true when used as is_write */
	81	CDS_OP_A = 2 /* advance, should not be used as is_write */
	82	} CcwDataStreamOp;
	83
	84	/* normal usage is via SuchchDev.cds instead of instantiating */
	85	typedef struct CcwDataStream {
	86	#define CDS_F_IDA 0x01
	87	#define CDS_F_MIDA 0x02
	88	#define CDS_F_I2K 0x04
	89	#define CDS_F_C64 0x08
62a2554e	90	#define CDS_F_FMT 0x10 /* CCW format-1 */
57065a70 HP	91	#define CDS_F_STREAM_BROKEN 0x80
	92	uint8_t flags;
	93	uint8_t at_idaw;
	94	uint16_t at_byte;
	95	uint16_t count;
	96	uint32_t cda_orig;
	97	int (op_handler)(struct CcwDataStream cds, void *buff, int len,
	98	CcwDataStreamOp op);
	99	hwaddr cda;
85fa94e1	100	bool do_skip;
57065a70 HP	101	} CcwDataStream;
57065a70 HP	102
e443ef9f HP	103	/*
	104	* IO instructions conclude according to this. Currently we have only
	105	* cc codes. Valid values are 0, 1, 2, 3 and the generic semantic for
	106	* IO instructions is described briefly. For more details consult the PoP.
	107	*/
	108	typedef enum IOInstEnding {
	109	/* produced expected result */
	110	IOINST_CC_EXPECTED = 0,
	111	/* status conditions were present or produced alternate result */
	112	IOINST_CC_STATUS_PRESENT = 1,
	113	/* inst. ineffective because busy with previously initiated function */
	114	IOINST_CC_BUSY = 2,
	115	/* inst. ineffective because not operational */
	116	IOINST_CC_NOT_OPERATIONAL = 3
	117	} IOInstEnding;
	118
bd3f16ac	119	typedef struct SubchDev SubchDev;
df1fe5bb CH	120	struct SubchDev {
df1fe5bb CH	121	/* channel-subsystem related things: */
cb89b349 TH	122	SCHIB curr_status; /* Needs alignment and thus must come first */
cb89b349 TH	123	ORB orb;
df1fe5bb CH	124	uint8_t cssid;
	125	uint8_t ssid;
	126	uint16_t schid;
	127	uint16_t devno;
df1fe5bb CH	128	uint8_t sense_data[32];
	129	hwaddr channel_prog;
	130	CCW1 last_cmd;
	131	bool last_cmd_valid;
a327c921	132	bool ccw_fmt_1;
7e749462	133	bool thinint_active;
e8601dd5	134	uint8_t ccw_no_data_cnt;
517ff12c	135	uint16_t migrated_schid; /* used for missmatch detection */
57065a70	136	CcwDataStream cds;
df1fe5bb CH	137	/* transport-provided data: */
df1fe5bb CH	138	int (ccw_cb) (SubchDev , CCW1);
62ac4a52	139	void (disable_cb)(SubchDev );
66dc50f7	140	IOInstEnding (do_subchannel_work) (SubchDev );
df1fe5bb CH	141	SenseId id;
	142	void *driver_data;
	143	};
	144
66dc50f7 HP	145	static inline void sch_gen_unit_exception(SubchDev *sch)
	146	{
	147	sch->curr_status.scsw.ctrl &= ~SCSW_ACTL_START_PEND;
	148	sch->curr_status.scsw.ctrl \|= SCSW_STCTL_PRIMARY \|
	149	SCSW_STCTL_SECONDARY \|
	150	SCSW_STCTL_ALERT \|
	151	SCSW_STCTL_STATUS_PEND;
	152	sch->curr_status.scsw.cpa = sch->channel_prog + 8;
	153	sch->curr_status.scsw.dstat = SCSW_DSTAT_UNIT_EXCEP;
	154	}
	155
517ff12c HP	156	extern const VMStateDescription vmstate_subch_dev;
517ff12c HP	157
8f3cf012 XFR	158	/*
	159	* Identify a device within the channel subsystem.
	160	* Note that this can be used to identify either the subchannel or
	161	* the attached I/O device, as there's always one I/O device per
	162	* subchannel.
	163	*/
	164	typedef struct CssDevId {
	165	uint8_t cssid;
	166	uint8_t ssid;
	167	uint16_t devid;
	168	bool valid;
	169	} CssDevId;
	170
1b6b7d10	171	extern const PropertyInfo css_devid_propinfo;
8f3cf012 XFR	172
	173	#define DEFINE_PROP_CSS_DEV_ID(_n, _s, _f) \
	174	DEFINE_PROP(_n, _s, _f, css_devid_propinfo, CssDevId)
	175
a28d8391 YMZ	176	typedef struct IndAddr {
	177	hwaddr addr;
	178	uint64_t map;
	179	unsigned long refcnt;
517ff12c	180	int32_t len;
a28d8391 YMZ	181	QTAILQ_ENTRY(IndAddr) sibling;
	182	} IndAddr;
	183
517ff12c HP	184	extern const VMStateDescription vmstate_ind_addr;
	185
	186	#define VMSTATE_PTR_TO_IND_ADDR(_f, _s) \
	187	VMSTATE_STRUCT(_f, _s, 1, vmstate_ind_addr, IndAddr*)
	188
a28d8391 YMZ	189	IndAddr *get_indicator(hwaddr ind_addr, int len);
	190	void release_indicator(AdapterInfo adapter, IndAddr indicator);
	191	int map_indicator(AdapterInfo adapter, IndAddr indicator);
	192
df1fe5bb CH	193	typedef SubchDev (css_subch_cb_func)(uint8_t m, uint8_t cssid, uint8_t ssid,
	194	uint16_t schid);
	195	int css_create_css_image(uint8_t cssid, bool default_image);
	196	bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno);
	197	void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid,
	198	uint16_t devno, SubchDev *sch);
	199	void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type);
8f3cf012	200	int css_sch_build_schib(SubchDev sch, CssDevId dev_id);
6c15e9bf	201	unsigned int css_find_free_chpid(uint8_t cssid);
b4436a0b	202	uint16_t css_build_subchannel_id(SubchDev *sch);
8ca2b376 XFR	203	void copy_scsw_to_guest(SCSW dest, const SCSW src);
8ca2b376 XFR	204	void css_inject_io_interrupt(SubchDev *sch);
df1fe5bb CH	205	void css_reset(void);
df1fe5bb CH	206	void css_reset_sch(SubchDev *sch);
5c8d6f00 DJS	207	void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited,
5c8d6f00 DJS	208	int chain, uint16_t rsid);
df1fe5bb CH	209	void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid,
	210	int hotplugged, int add);
	211	void css_generate_chp_crws(uint8_t cssid, uint8_t chpid);
8cba80c3	212	void css_generate_css_crws(uint8_t cssid);
c81b4f89	213	void css_clear_sei_pending(void);
66dc50f7 HP	214	IOInstEnding s390_ccw_cmd_request(SubchDev *sch);
	215	IOInstEnding do_subchannel_work_virtual(SubchDev *sub);
	216	IOInstEnding do_subchannel_work_passthrough(SubchDev *sub);
03cf077a	217
8fadea24 CH	218	int s390_ccw_halt(SubchDev *sch);
	219	int s390_ccw_clear(SubchDev *sch);
	220
5b00bef2 FL	221	typedef enum {
	222	CSS_IO_ADAPTER_VIRTIO = 0,
	223	CSS_IO_ADAPTER_PCI = 1,
	224	CSS_IO_ADAPTER_TYPE_NUMS,
	225	} CssIoAdapterType;
	226
25a08b8d	227	void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc);
2283f4d6	228	int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode);
dde522bb FL	229	uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc);
dde522bb FL	230	void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable,
1497c160 FL	231	uint8_t flags, Error **errp);
	232
	233	#ifndef CONFIG_KVM
	234	#define S390_ADAPTER_SUPPRESSIBLE 0x01
	235	#else
	236	#define S390_ADAPTER_SUPPRESSIBLE KVM_S390_ADAPTER_SUPPRESSIBLE
	237	#endif
bd3f16ac PB	238
	239	#ifndef CONFIG_USER_ONLY
	240	SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
	241	uint16_t schid);
	242	bool css_subch_visible(SubchDev *sch);
	243	void css_conditional_io_interrupt(SubchDev *sch);
	244	int css_do_stsch(SubchDev sch, SCHIB schib);
	245	bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
6bb6f194	246	IOInstEnding css_do_msch(SubchDev sch, const SCHIB schib);
96376408	247	IOInstEnding css_do_xsch(SubchDev *sch);
77331442	248	IOInstEnding css_do_csch(SubchDev *sch);
ae9f1be3	249	IOInstEnding css_do_hsch(SubchDev *sch);
66dc50f7	250	IOInstEnding css_do_ssch(SubchDev sch, ORB orb);
bd3f16ac PB	251	int css_do_tsch_get_irb(SubchDev sch, IRB irb, int *irb_len);
	252	void css_do_tsch_update_subch(SubchDev *sch);
	253	int css_do_stcrw(CRW *crw);
	254	void css_undo_stcrw(CRW *crw);
bd3f16ac PB	255	int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
	256	int rfmt, void *buf);
	257	void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
	258	int css_enable_mcsse(void);
	259	int css_enable_mss(void);
66dc50f7	260	IOInstEnding css_do_rsch(SubchDev *sch);
bd3f16ac PB	261	int css_do_rchp(uint8_t cssid, uint8_t chpid);
	262	bool css_present(uint8_t cssid);
	263	#endif
	264
1b6b7d10	265	extern const PropertyInfo css_devid_ro_propinfo;
c35fc6aa DJS	266
	267	#define DEFINE_PROP_CSS_DEV_ID_RO(_n, _s, _f) \
	268	DEFINE_PROP(_n, _s, _f, css_devid_ro_propinfo, CssDevId)
	269
cf249935 SS	270	/**
	271	* Create a subchannel for the given bus id.
	272	*
36699ab4 CH	273	* If @p bus_id is valid, verify that it is not already in use, and find a
36699ab4 CH	274	* free devno for it.
99577c49 HP	275	* If @p bus_id is not valid find a free subchannel id and device number
	276	* across all subchannel sets and all css images starting from the default
	277	* css image.
817d4a6b DJS	278	*
	279	* If either of the former actions succeed, allocate a subchannel structure,
	280	* initialise it with the bus id, subchannel id and device number, register
	281	* it with the CSS and return it. Otherwise return NULL.
cf249935 SS	282	*
	283	* The caller becomes owner of the returned subchannel structure and
	284	* is responsible for unregistering and freeing it.
	285	*/
36699ab4	286	SubchDev css_create_sch(CssDevId bus_id, Error *errp);
e996583e HP	287
	288	/** Turn on css migration */
	289	void css_register_vmstate(void);
	290
57065a70 HP	291
	292	void ccw_dstream_init(CcwDataStream cds, CCW1 const ccw, ORB const *orb);
	293
	294	static inline void ccw_dstream_rewind(CcwDataStream *cds)
	295	{
	296	cds->at_byte = 0;
	297	cds->at_idaw = 0;
	298	cds->cda = cds->cda_orig;
	299	}
	300
	301	static inline bool ccw_dstream_good(CcwDataStream *cds)
	302	{
	303	return !(cds->flags & CDS_F_STREAM_BROKEN);
	304	}
	305
	306	static inline uint16_t ccw_dstream_residual_count(CcwDataStream *cds)
	307	{
	308	return cds->count - cds->at_byte;
	309	}
	310
	311	static inline uint16_t ccw_dstream_avail(CcwDataStream *cds)
	312	{
	313	return ccw_dstream_good(cds) ? ccw_dstream_residual_count(cds) : 0;
	314	}
	315
	316	static inline int ccw_dstream_advance(CcwDataStream *cds, int len)
	317	{
	318	return cds->op_handler(cds, NULL, len, CDS_OP_A);
	319	}
	320
	321	static inline int ccw_dstream_write_buf(CcwDataStream cds, void buff, int len)
	322	{
	323	return cds->op_handler(cds, buff, len, CDS_OP_W);
	324	}
	325
	326	static inline int ccw_dstream_read_buf(CcwDataStream cds, void buff, int len)
	327	{
	328	return cds->op_handler(cds, buff, len, CDS_OP_R);
	329	}
	330
	331	#define ccw_dstream_read(cds, v) ccw_dstream_read_buf((cds), &(v), sizeof(v))
	332	#define ccw_dstream_write(cds, v) ccw_dstream_write_buf((cds), &(v), sizeof(v))
	333
df1fe5bb	334	#endif