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spapr: Refactor spapr_populate_memory() to allow memoryless nodes
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1/*
2 * QEMU System Emulator
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24/*
25 * splitted out ioport related stuffs from vl.c.
26 */
27
022c62cb 28#include "exec/ioport.h"
bd3c9aa5 29#include "trace.h"
022c62cb 30#include "exec/memory.h"
b40acf99 31#include "exec/address-spaces.h"
32993977 32
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33//#define DEBUG_IOPORT
34
35#ifdef DEBUG_IOPORT
36# define LOG_IOPORT(...) qemu_log_mask(CPU_LOG_IOPORT, ## __VA_ARGS__)
37#else
38# define LOG_IOPORT(...) do { } while (0)
39#endif
40
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41typedef struct MemoryRegionPortioList {
42 MemoryRegion mr;
43 void *portio_opaque;
44 MemoryRegionPortio ports[];
45} MemoryRegionPortioList;
46
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47static uint64_t unassigned_io_read(void *opaque, hwaddr addr, unsigned size)
48{
49 return -1ULL;
50}
51
52static void unassigned_io_write(void *opaque, hwaddr addr, uint64_t val,
53 unsigned size)
54{
55}
56
57const MemoryRegionOps unassigned_io_ops = {
58 .read = unassigned_io_read,
59 .write = unassigned_io_write,
60 .endianness = DEVICE_NATIVE_ENDIAN,
61};
62
c227f099 63void cpu_outb(pio_addr_t addr, uint8_t val)
32993977 64{
07323531 65 LOG_IOPORT("outb: %04"FMT_pioaddr" %02"PRIx8"\n", addr, val);
bd3c9aa5 66 trace_cpu_out(addr, val);
b40acf99 67 address_space_write(&address_space_io, addr, &val, 1);
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68}
69
c227f099 70void cpu_outw(pio_addr_t addr, uint16_t val)
32993977 71{
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72 uint8_t buf[2];
73
07323531 74 LOG_IOPORT("outw: %04"FMT_pioaddr" %04"PRIx16"\n", addr, val);
bd3c9aa5 75 trace_cpu_out(addr, val);
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76 stw_p(buf, val);
77 address_space_write(&address_space_io, addr, buf, 2);
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78}
79
c227f099 80void cpu_outl(pio_addr_t addr, uint32_t val)
32993977 81{
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82 uint8_t buf[4];
83
07323531 84 LOG_IOPORT("outl: %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
bd3c9aa5 85 trace_cpu_out(addr, val);
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86 stl_p(buf, val);
87 address_space_write(&address_space_io, addr, buf, 4);
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88}
89
c227f099 90uint8_t cpu_inb(pio_addr_t addr)
32993977 91{
07323531 92 uint8_t val;
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93
94 address_space_read(&address_space_io, addr, &val, 1);
bd3c9aa5 95 trace_cpu_in(addr, val);
07323531 96 LOG_IOPORT("inb : %04"FMT_pioaddr" %02"PRIx8"\n", addr, val);
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97 return val;
98}
99
c227f099 100uint16_t cpu_inw(pio_addr_t addr)
32993977 101{
b40acf99 102 uint8_t buf[2];
07323531 103 uint16_t val;
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104
105 address_space_read(&address_space_io, addr, buf, 2);
106 val = lduw_p(buf);
bd3c9aa5 107 trace_cpu_in(addr, val);
07323531 108 LOG_IOPORT("inw : %04"FMT_pioaddr" %04"PRIx16"\n", addr, val);
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109 return val;
110}
111
c227f099 112uint32_t cpu_inl(pio_addr_t addr)
32993977 113{
b40acf99 114 uint8_t buf[4];
07323531 115 uint32_t val;
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116
117 address_space_read(&address_space_io, addr, buf, 4);
118 val = ldl_p(buf);
bd3c9aa5 119 trace_cpu_in(addr, val);
07323531 120 LOG_IOPORT("inl : %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
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121 return val;
122}
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123
124void portio_list_init(PortioList *piolist,
db10ca90 125 Object *owner,
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126 const MemoryRegionPortio *callbacks,
127 void *opaque, const char *name)
128{
129 unsigned n = 0;
130
131 while (callbacks[n].size) {
132 ++n;
133 }
134
135 piolist->ports = callbacks;
136 piolist->nr = 0;
137 piolist->regions = g_new0(MemoryRegion *, n);
138 piolist->address_space = NULL;
139 piolist->opaque = opaque;
db10ca90 140 piolist->owner = owner;
6bf9fd43 141 piolist->name = name;
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142 piolist->flush_coalesced_mmio = false;
143}
144
145void portio_list_set_flush_coalesced(PortioList *piolist)
146{
147 piolist->flush_coalesced_mmio = true;
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148}
149
150void portio_list_destroy(PortioList *piolist)
151{
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152 MemoryRegionPortioList *mrpio;
153 unsigned i;
154
155 for (i = 0; i < piolist->nr; ++i) {
156 mrpio = container_of(piolist->regions[i], MemoryRegionPortioList, mr);
d8d95814 157 object_unparent(OBJECT(&mrpio->mr));
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158 g_free(mrpio);
159 }
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160 g_free(piolist->regions);
161}
162
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163static const MemoryRegionPortio *find_portio(MemoryRegionPortioList *mrpio,
164 uint64_t offset, unsigned size,
165 bool write)
166{
167 const MemoryRegionPortio *mrp;
168
169 for (mrp = mrpio->ports; mrp->size; ++mrp) {
170 if (offset >= mrp->offset && offset < mrp->offset + mrp->len &&
171 size == mrp->size &&
172 (write ? (bool)mrp->write : (bool)mrp->read)) {
173 return mrp;
174 }
175 }
176 return NULL;
177}
178
179static uint64_t portio_read(void *opaque, hwaddr addr, unsigned size)
180{
181 MemoryRegionPortioList *mrpio = opaque;
182 const MemoryRegionPortio *mrp = find_portio(mrpio, addr, size, false);
183 uint64_t data;
184
185 data = ((uint64_t)1 << (size * 8)) - 1;
186 if (mrp) {
187 data = mrp->read(mrpio->portio_opaque, mrp->base + addr);
188 } else if (size == 2) {
189 mrp = find_portio(mrpio, addr, 1, false);
190 assert(mrp);
191 data = mrp->read(mrpio->portio_opaque, mrp->base + addr) |
192 (mrp->read(mrpio->portio_opaque, mrp->base + addr + 1) << 8);
193 }
194 return data;
195}
196
197static void portio_write(void *opaque, hwaddr addr, uint64_t data,
198 unsigned size)
199{
200 MemoryRegionPortioList *mrpio = opaque;
201 const MemoryRegionPortio *mrp = find_portio(mrpio, addr, size, true);
202
203 if (mrp) {
204 mrp->write(mrpio->portio_opaque, mrp->base + addr, data);
205 } else if (size == 2) {
206 mrp = find_portio(mrpio, addr, 1, true);
207 assert(mrp);
208 mrp->write(mrpio->portio_opaque, mrp->base + addr, data & 0xff);
209 mrp->write(mrpio->portio_opaque, mrp->base + addr + 1, data >> 8);
210 }
211}
212
213static const MemoryRegionOps portio_ops = {
214 .read = portio_read,
215 .write = portio_write,
f36a6382 216 .endianness = DEVICE_LITTLE_ENDIAN,
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217 .valid.unaligned = true,
218 .impl.unaligned = true,
219};
220
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221static void portio_list_add_1(PortioList *piolist,
222 const MemoryRegionPortio *pio_init,
223 unsigned count, unsigned start,
224 unsigned off_low, unsigned off_high)
225{
b40acf99 226 MemoryRegionPortioList *mrpio;
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227 unsigned i;
228
229 /* Copy the sub-list and null-terminate it. */
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230 mrpio = g_malloc0(sizeof(MemoryRegionPortioList) +
231 sizeof(MemoryRegionPortio) * (count + 1));
232 mrpio->portio_opaque = piolist->opaque;
233 memcpy(mrpio->ports, pio_init, sizeof(MemoryRegionPortio) * count);
234 memset(mrpio->ports + count, 0, sizeof(MemoryRegionPortio));
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235
236 /* Adjust the offsets to all be zero-based for the region. */
237 for (i = 0; i < count; ++i) {
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238 mrpio->ports[i].offset -= off_low;
239 mrpio->ports[i].base = start + off_low;
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240 }
241
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242 /*
243 * Use an alias so that the callback is called with an absolute address,
244 * rather than an offset relative to to start + off_low.
245 */
db10ca90
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246 memory_region_init_io(&mrpio->mr, piolist->owner, &portio_ops, mrpio,
247 piolist->name, off_high - off_low);
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248 if (piolist->flush_coalesced_mmio) {
249 memory_region_set_flush_coalesced(&mrpio->mr);
250 }
6bf9fd43 251 memory_region_add_subregion(piolist->address_space,
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252 start + off_low, &mrpio->mr);
253 piolist->regions[piolist->nr] = &mrpio->mr;
de58ac72 254 ++piolist->nr;
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255}
256
257void portio_list_add(PortioList *piolist,
258 MemoryRegion *address_space,
259 uint32_t start)
260{
261 const MemoryRegionPortio *pio, *pio_start = piolist->ports;
262 unsigned int off_low, off_high, off_last, count;
263
264 piolist->address_space = address_space;
265
266 /* Handle the first entry specially. */
267 off_last = off_low = pio_start->offset;
268 off_high = off_low + pio_start->len;
269 count = 1;
270
271 for (pio = pio_start + 1; pio->size != 0; pio++, count++) {
272 /* All entries must be sorted by offset. */
273 assert(pio->offset >= off_last);
274 off_last = pio->offset;
275
276 /* If we see a hole, break the region. */
277 if (off_last > off_high) {
278 portio_list_add_1(piolist, pio_start, count, start, off_low,
279 off_high);
280 /* ... and start collecting anew. */
281 pio_start = pio;
282 off_low = off_last;
283 off_high = off_low + pio->len;
284 count = 0;
285 } else if (off_last + pio->len > off_high) {
286 off_high = off_last + pio->len;
287 }
288 }
289
290 /* There will always be an open sub-list. */
291 portio_list_add_1(piolist, pio_start, count, start, off_low, off_high);
292}
293
294void portio_list_del(PortioList *piolist)
295{
b40acf99 296 MemoryRegionPortioList *mrpio;
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297 unsigned i;
298
299 for (i = 0; i < piolist->nr; ++i) {
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300 mrpio = container_of(piolist->regions[i], MemoryRegionPortioList, mr);
301 memory_region_del_subregion(piolist->address_space, &mrpio->mr);
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302 }
303}