[mirror_qemu.git] / linux-user / aarch64 / cpu_loop.c

/*
 *  qemu user cpu loop
 *
 *  Copyright (c) 2003-2008 Fabrice Bellard
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu.h"
#include "user-internals.h"
#include "cpu_loop-common.h"
#include "signal-common.h"
#include "qemu/guest-random.h"
#include "semihosting/common-semi.h"
#include "target/arm/syndrome.h"

#define get_user_code_u32(x, gaddr, env)                \
    ({ abi_long __r = get_user_u32((x), (gaddr));       \
        if (!__r && bswap_code(arm_sctlr_b(env))) {     \
            (x) = bswap32(x);                           \
        }                                               \
        __r;                                            \
    })

#define get_user_code_u16(x, gaddr, env)                \
    ({ abi_long __r = get_user_u16((x), (gaddr));       \
        if (!__r && bswap_code(arm_sctlr_b(env))) {     \
            (x) = bswap16(x);                           \
        }                                               \
        __r;                                            \
    })

#define get_user_data_u32(x, gaddr, env)                \
    ({ abi_long __r = get_user_u32((x), (gaddr));       \
        if (!__r && arm_cpu_bswap_data(env)) {          \
            (x) = bswap32(x);                           \
        }                                               \
        __r;                                            \
    })

#define get_user_data_u16(x, gaddr, env)                \
    ({ abi_long __r = get_user_u16((x), (gaddr));       \
        if (!__r && arm_cpu_bswap_data(env)) {          \
            (x) = bswap16(x);                           \
        }                                               \
        __r;                                            \
    })

#define put_user_data_u32(x, gaddr, env)                \
    ({ typeof(x) __x = (x);                             \
        if (arm_cpu_bswap_data(env)) {                  \
            __x = bswap32(__x);                         \
        }                                               \
        put_user_u32(__x, (gaddr));                     \
    })

#define put_user_data_u16(x, gaddr, env)                \
    ({ typeof(x) __x = (x);                             \
        if (arm_cpu_bswap_data(env)) {                  \
            __x = bswap16(__x);                         \
        }                                               \
        put_user_u16(__x, (gaddr));                     \
    })

/* AArch64 main loop */
void cpu_loop(CPUARMState *env)
{
    CPUState *cs = env_cpu(env);
    int trapnr, ec, fsc, si_code, si_signo;
    abi_long ret;

    for (;;) {
        cpu_exec_start(cs);
        trapnr = cpu_exec(cs);
        cpu_exec_end(cs);
        process_queued_cpu_work(cs);

        switch (trapnr) {
        case EXCP_SWI:
            ret = do_syscall(env,
                             env->xregs[8],
                             env->xregs[0],
                             env->xregs[1],
                             env->xregs[2],
                             env->xregs[3],
                             env->xregs[4],
                             env->xregs[5],
                             0, 0);
            if (ret == -QEMU_ERESTARTSYS) {
                env->pc -= 4;
            } else if (ret != -QEMU_ESIGRETURN) {
                env->xregs[0] = ret;
            }
            break;
        case EXCP_INTERRUPT:
            /* just indicate that signals should be handled asap */
            break;
        case EXCP_UDEF:
            force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc);
            break;
        case EXCP_PREFETCH_ABORT:
        case EXCP_DATA_ABORT:
            ec = syn_get_ec(env->exception.syndrome);
            switch (ec) {
            case EC_DATAABORT:
            case EC_INSNABORT:
                /* Both EC have the same format for FSC, or close enough. */
                fsc = extract32(env->exception.syndrome, 0, 6);
                switch (fsc) {
                case 0x04 ... 0x07: /* Translation fault, level {0-3} */
                    si_signo = TARGET_SIGSEGV;
                    si_code = TARGET_SEGV_MAPERR;
                    break;
                case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
                case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
                    si_signo = TARGET_SIGSEGV;
                    si_code = TARGET_SEGV_ACCERR;
                    break;
                case 0x11: /* Synchronous Tag Check Fault */
                    si_signo = TARGET_SIGSEGV;
                    si_code = TARGET_SEGV_MTESERR;
                    break;
                case 0x21: /* Alignment fault */
                    si_signo = TARGET_SIGBUS;
                    si_code = TARGET_BUS_ADRALN;
                    break;
                default:
                    g_assert_not_reached();
                }
                break;
            case EC_PCALIGNMENT:
                si_signo = TARGET_SIGBUS;
                si_code = TARGET_BUS_ADRALN;
                break;
            default:
                g_assert_not_reached();
            }
            force_sig_fault(si_signo, si_code, env->exception.vaddress);
            break;
        case EXCP_DEBUG:
        case EXCP_BKPT:
            force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
            break;
        case EXCP_SEMIHOST:
            env->xregs[0] = do_common_semihosting(cs);
            env->pc += 4;
            break;
        case EXCP_YIELD:
            /* nothing to do here for user-mode, just resume guest code */
            break;
        case EXCP_ATOMIC:
            cpu_exec_step_atomic(cs);
            break;
        default:
            EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
            abort();
        }

        /* Check for MTE asynchronous faults */
        if (unlikely(env->cp15.tfsr_el[0])) {
            env->cp15.tfsr_el[0] = 0;
            force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MTEAERR, 0);
        }

        process_pending_signals(env);
        /* Exception return on AArch64 always clears the exclusive monitor,
         * so any return to running guest code implies this.
         */
        env->exclusive_addr = -1;
    }
}

void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
{
    ARMCPU *cpu = env_archcpu(env);
    CPUState *cs = env_cpu(env);
    TaskState *ts = cs->opaque;
    struct image_info *info = ts->info;
    int i;

    if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
        fprintf(stderr,
                "The selected ARM CPU does not support 64 bit mode\n");
        exit(EXIT_FAILURE);
    }

    for (i = 0; i < 31; i++) {
        env->xregs[i] = regs->regs[i];
    }
    env->pc = regs->pc;
    env->xregs[31] = regs->sp;
#if TARGET_BIG_ENDIAN
    env->cp15.sctlr_el[1] |= SCTLR_E0E;
    for (i = 1; i < 4; ++i) {
        env->cp15.sctlr_el[i] |= SCTLR_EE;
    }
    arm_rebuild_hflags(env);
#endif

    if (cpu_isar_feature(aa64_pauth, cpu)) {
        qemu_guest_getrandom_nofail(&env->keys, sizeof(env->keys));
    }

    ts->stack_base = info->start_stack;
    ts->heap_base = info->brk;
    /* This will be filled in on the first SYS_HEAPINFO call.  */
    ts->heap_limit = 0;
}
Commit	Line	Data
cd71c089 LV	1	/*
	2	* qemu user cpu loop
	3	*
	4	* Copyright (c) 2003-2008 Fabrice Bellard
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "qemu/osdep.h"
	21	#include "qemu.h"
3b249d26	22	#include "user-internals.h"
cd71c089	23	#include "cpu_loop-common.h"
2113aed6	24	#include "signal-common.h"
51977e25	25	#include "qemu/guest-random.h"
6b5fe137	26	#include "semihosting/common-semi.h"
8db94ab4	27	#include "target/arm/syndrome.h"
cd71c089	28
3c439b17 LV	29	#define get_user_code_u32(x, gaddr, env) \
	30	({ abi_long __r = get_user_u32((x), (gaddr)); \
	31	if (!__r && bswap_code(arm_sctlr_b(env))) { \
	32	(x) = bswap32(x); \
	33	} \
	34	__r; \
	35	})
	36
	37	#define get_user_code_u16(x, gaddr, env) \
	38	({ abi_long __r = get_user_u16((x), (gaddr)); \
	39	if (!__r && bswap_code(arm_sctlr_b(env))) { \
	40	(x) = bswap16(x); \
	41	} \
	42	__r; \
	43	})
	44
	45	#define get_user_data_u32(x, gaddr, env) \
	46	({ abi_long __r = get_user_u32((x), (gaddr)); \
	47	if (!__r && arm_cpu_bswap_data(env)) { \
	48	(x) = bswap32(x); \
	49	} \
	50	__r; \
	51	})
	52
	53	#define get_user_data_u16(x, gaddr, env) \
	54	({ abi_long __r = get_user_u16((x), (gaddr)); \
	55	if (!__r && arm_cpu_bswap_data(env)) { \
	56	(x) = bswap16(x); \
	57	} \
	58	__r; \
	59	})
	60
	61	#define put_user_data_u32(x, gaddr, env) \
	62	({ typeof(x) __x = (x); \
	63	if (arm_cpu_bswap_data(env)) { \
	64	__x = bswap32(__x); \
	65	} \
	66	put_user_u32(__x, (gaddr)); \
	67	})
	68
	69	#define put_user_data_u16(x, gaddr, env) \
	70	({ typeof(x) __x = (x); \
	71	if (arm_cpu_bswap_data(env)) { \
	72	__x = bswap16(__x); \
	73	} \
	74	put_user_u16(__x, (gaddr)); \
	75	})
	76
	77	/* AArch64 main loop */
	78	void cpu_loop(CPUARMState *env)
	79	{
2fc0cc0e	80	CPUState *cs = env_cpu(env);
39a099ca	81	int trapnr, ec, fsc, si_code, si_signo;
3c439b17	82	abi_long ret;
3c439b17 LV	83
	84	for (;;) {
	85	cpu_exec_start(cs);
	86	trapnr = cpu_exec(cs);
	87	cpu_exec_end(cs);
	88	process_queued_cpu_work(cs);
	89
	90	switch (trapnr) {
	91	case EXCP_SWI:
	92	ret = do_syscall(env,
	93	env->xregs[8],
	94	env->xregs[0],
	95	env->xregs[1],
	96	env->xregs[2],
	97	env->xregs[3],
	98	env->xregs[4],
	99	env->xregs[5],
	100	0, 0);
af254a27	101	if (ret == -QEMU_ERESTARTSYS) {
3c439b17	102	env->pc -= 4;
57a0c938	103	} else if (ret != -QEMU_ESIGRETURN) {
3c439b17 LV	104	env->xregs[0] = ret;
	105	}
	106	break;
	107	case EXCP_INTERRUPT:
	108	/* just indicate that signals should be handled asap */
	109	break;
	110	case EXCP_UDEF:
fce9608d	111	force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc);
3c439b17 LV	112	break;
	113	case EXCP_PREFETCH_ABORT:
	114	case EXCP_DATA_ABORT:
8db94ab4	115	ec = syn_get_ec(env->exception.syndrome);
ee03027a RH	116	switch (ec) {
	117	case EC_DATAABORT:
	118	case EC_INSNABORT:
	119	/* Both EC have the same format for FSC, or close enough. */
	120	fsc = extract32(env->exception.syndrome, 0, 6);
	121	switch (fsc) {
	122	case 0x04 ... 0x07: /* Translation fault, level {0-3} */
	123	si_signo = TARGET_SIGSEGV;
	124	si_code = TARGET_SEGV_MAPERR;
	125	break;
	126	case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
	127	case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
	128	si_signo = TARGET_SIGSEGV;
	129	si_code = TARGET_SEGV_ACCERR;
	130	break;
	131	case 0x11: /* Synchronous Tag Check Fault */
	132	si_signo = TARGET_SIGSEGV;
	133	si_code = TARGET_SEGV_MTESERR;
	134	break;
	135	case 0x21: /* Alignment fault */
	136	si_signo = TARGET_SIGBUS;
	137	si_code = TARGET_BUS_ADRALN;
	138	break;
	139	default:
	140	g_assert_not_reached();
	141	}
61dbe037	142	break;
ee03027a	143	case EC_PCALIGNMENT:
39a099ca RH	144	si_signo = TARGET_SIGBUS;
	145	si_code = TARGET_BUS_ADRALN;
	146	break;
8db94ab4 RH	147	default:
	148	g_assert_not_reached();
	149	}
39a099ca	150	force_sig_fault(si_signo, si_code, env->exception.vaddress);
3c439b17 LV	151	break;
	152	case EXCP_DEBUG:
	153	case EXCP_BKPT:
fce9608d	154	force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
3c439b17 LV	155	break;
3c439b17 LV	156	case EXCP_SEMIHOST:
0bb446d8	157	env->xregs[0] = do_common_semihosting(cs);
4ff5ef9e	158	env->pc += 4;
3c439b17 LV	159	break;
	160	case EXCP_YIELD:
	161	/* nothing to do here for user-mode, just resume guest code */
	162	break;
	163	case EXCP_ATOMIC:
	164	cpu_exec_step_atomic(cs);
	165	break;
	166	default:
	167	EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
	168	abort();
	169	}
5d70c351 RH	170
	171	/* Check for MTE asynchronous faults */
	172	if (unlikely(env->cp15.tfsr_el[0])) {
	173	env->cp15.tfsr_el[0] = 0;
fce9608d	174	force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MTEAERR, 0);
5d70c351 RH	175	}
5d70c351 RH	176
3c439b17 LV	177	process_pending_signals(env);
	178	/* Exception return on AArch64 always clears the exclusive monitor,
	179	* so any return to running guest code implies this.
	180	*/
	181	env->exclusive_addr = -1;
	182	}
	183	}
	184
cd71c089 LV	185	void target_cpu_copy_regs(CPUArchState env, struct target_pt_regs regs)
cd71c089 LV	186	{
2fc0cc0e RH	187	ARMCPU *cpu = env_archcpu(env);
2fc0cc0e RH	188	CPUState *cs = env_cpu(env);
87877543	189	TaskState *ts = cs->opaque;
3c439b17 LV	190	struct image_info *info = ts->info;
	191	int i;
	192
	193	if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
	194	fprintf(stderr,
	195	"The selected ARM CPU does not support 64 bit mode\n");
	196	exit(EXIT_FAILURE);
	197	}
	198
	199	for (i = 0; i < 31; i++) {
	200	env->xregs[i] = regs->regs[i];
	201	}
	202	env->pc = regs->pc;
	203	env->xregs[31] = regs->sp;
ee3eb3a7	204	#if TARGET_BIG_ENDIAN
3c439b17 LV	205	env->cp15.sctlr_el[1] \|= SCTLR_E0E;
	206	for (i = 1; i < 4; ++i) {
	207	env->cp15.sctlr_el[i] \|= SCTLR_EE;
	208	}
62fb8a47	209	arm_rebuild_hflags(env);
3c439b17 LV	210	#endif
3c439b17 LV	211
87877543	212	if (cpu_isar_feature(aa64_pauth, cpu)) {
108b3ba8	213	qemu_guest_getrandom_nofail(&env->keys, sizeof(env->keys));
87877543 RH	214	}
87877543 RH	215
3c439b17 LV	216	ts->stack_base = info->start_stack;
	217	ts->heap_base = info->brk;
	218	/* This will be filled in on the first SYS_HEAPINFO call. */
	219	ts->heap_limit = 0;
cd71c089	220	}