[mirror_qemu.git] / linux-user / mips / cpu_loop.c

/*
 *  qemu user cpu loop
 *
 *  Copyright (c) 2003-2008 Fabrice Bellard
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu.h"
#include "user-internals.h"
#include "cpu_loop-common.h"
#include "signal-common.h"
#include "elf.h"
#include "internal.h"
#include "fpu_helper.h"

# ifdef TARGET_ABI_MIPSO32
#  define MIPS_SYSCALL_NUMBER_UNUSED -1
static const int8_t mips_syscall_args[] = {
#include "syscall-args-o32.c.inc"
};
# endif /* O32 */

/* Break codes */
enum {
    BRK_OVERFLOW = 6,
    BRK_DIVZERO = 7
};

static void do_tr_or_bp(CPUMIPSState *env, unsigned int code, bool trap)
{
    target_ulong pc = env->active_tc.PC;

    switch (code) {
    case BRK_OVERFLOW:
        force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, pc);
        break;
    case BRK_DIVZERO:
        force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, pc);
        break;
    default:
        if (trap) {
            force_sig(TARGET_SIGTRAP);
        } else {
            force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, pc);
        }
        break;
    }
}

void cpu_loop(CPUMIPSState *env)
{
    CPUState *cs = env_cpu(env);
    int trapnr, si_code;
    unsigned int code;
    abi_long ret;
# ifdef TARGET_ABI_MIPSO32
    unsigned int syscall_num;
# endif

    for(;;) {
        cpu_exec_start(cs);
        trapnr = cpu_exec(cs);
        cpu_exec_end(cs);
        process_queued_cpu_work(cs);

        switch(trapnr) {
        case EXCP_SYSCALL:
            env->active_tc.PC += 4;
# ifdef TARGET_ABI_MIPSO32
            syscall_num = env->active_tc.gpr[2] - 4000;
            if (syscall_num >= sizeof(mips_syscall_args)) {
                /* syscall_num is larger that any defined for MIPS O32 */
                ret = -TARGET_ENOSYS;
            } else if (mips_syscall_args[syscall_num] ==
                       MIPS_SYSCALL_NUMBER_UNUSED) {
                /* syscall_num belongs to the range not defined for MIPS O32 */
                ret = -TARGET_ENOSYS;
            } else {
                /* syscall_num is valid */
                int nb_args;
                abi_ulong sp_reg;
                abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;

                nb_args = mips_syscall_args[syscall_num];
                sp_reg = env->active_tc.gpr[29];
                switch (nb_args) {
                /* these arguments are taken from the stack */
                case 8:
                    if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
                        goto done_syscall;
                    }
                    /* fall through */
                case 7:
                    if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
                        goto done_syscall;
                    }
                    /* fall through */
                case 6:
                    if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
                        goto done_syscall;
                    }
                    /* fall through */
                case 5:
                    if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
                        goto done_syscall;
                    }
                    /* fall through */
                default:
                    break;
                }
                ret = do_syscall(env, env->active_tc.gpr[2],
                                 env->active_tc.gpr[4],
                                 env->active_tc.gpr[5],
                                 env->active_tc.gpr[6],
                                 env->active_tc.gpr[7],
                                 arg5, arg6, arg7, arg8);
            }
done_syscall:
# else
            ret = do_syscall(env, env->active_tc.gpr[2],
                             env->active_tc.gpr[4], env->active_tc.gpr[5],
                             env->active_tc.gpr[6], env->active_tc.gpr[7],
                             env->active_tc.gpr[8], env->active_tc.gpr[9],
                             env->active_tc.gpr[10], env->active_tc.gpr[11]);
# endif /* O32 */
            if (ret == -QEMU_ERESTARTSYS) {
                env->active_tc.PC -= 4;
                break;
            }
            if (ret == -QEMU_ESIGRETURN) {
                /* Returning from a successful sigreturn syscall.
                   Avoid clobbering register state.  */
                break;
            }
            if ((abi_ulong)ret >= (abi_ulong)-1133) {
                env->active_tc.gpr[7] = 1; /* error flag */
                ret = -ret;
            } else {
                env->active_tc.gpr[7] = 0; /* error flag */
            }
            env->active_tc.gpr[2] = ret;
            break;
        case EXCP_CpU:
        case EXCP_RI:
        case EXCP_DSPDIS:
            force_sig(TARGET_SIGILL);
            break;
        case EXCP_INTERRUPT:
            /* just indicate that signals should be handled asap */
            break;
        case EXCP_DEBUG:
            force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT,
                            env->active_tc.PC);
            break;
        case EXCP_FPE:
            si_code = TARGET_FPE_FLTUNK;
            if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) {
                si_code = TARGET_FPE_FLTINV;
            } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_DIV0) {
                si_code = TARGET_FPE_FLTDIV;
            } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_OVERFLOW) {
                si_code = TARGET_FPE_FLTOVF;
            } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_UNDERFLOW) {
                si_code = TARGET_FPE_FLTUND;
            } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INEXACT) {
                si_code = TARGET_FPE_FLTRES;
            }
            force_sig_fault(TARGET_SIGFPE, si_code, env->active_tc.PC);
            break;
	case EXCP_OVERFLOW:
            force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->active_tc.PC);
            break;
        /* The code below was inspired by the MIPS Linux kernel trap
         * handling code in arch/mips/kernel/traps.c.
         */
        case EXCP_BREAK:
            /*
             * As described in the original Linux kernel code, the below
             * checks on 'code' are to work around an old assembly bug.
             */
            code = env->error_code;
            if (code >= (1 << 10)) {
                code >>= 10;
            }
            do_tr_or_bp(env, code, false);
            break;
        case EXCP_TRAP:
            do_tr_or_bp(env, env->error_code, true);
            break;
        case EXCP_ATOMIC:
            cpu_exec_step_atomic(cs);
            break;
        default:
            EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
            abort();
        }
        process_pending_signals(env);
    }
}

void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
{
    CPUState *cpu = env_cpu(env);
    TaskState *ts = get_task_state(cpu);
    struct image_info *info = ts->info;
    int i;

    struct mode_req {
        bool single;
        bool soft;
        bool fr1;
        bool frdefault;
        bool fre;
    };

    static const struct mode_req fpu_reqs[] = {
        [MIPS_ABI_FP_ANY]    = { true,  true,  true,  true,  true  },
        [MIPS_ABI_FP_DOUBLE] = { false, false, false, true,  true  },
        [MIPS_ABI_FP_SINGLE] = { true,  false, false, false, false },
        [MIPS_ABI_FP_SOFT]   = { false, true,  false, false, false },
        [MIPS_ABI_FP_OLD_64] = { false, false, false, false, false },
        [MIPS_ABI_FP_XX]     = { false, false, true,  true,  true  },
        [MIPS_ABI_FP_64]     = { false, false, true,  false, false },
        [MIPS_ABI_FP_64A]    = { false, false, true,  false, true  }
    };

    /*
     * Mode requirements when .MIPS.abiflags is not present in the ELF.
     * Not present means that everything is acceptable except FR1.
     */
    static struct mode_req none_req = { true, true, false, true, true };

    struct mode_req prog_req;
    struct mode_req interp_req;

    for(i = 0; i < 32; i++) {
        env->active_tc.gpr[i] = regs->regs[i];
    }
    env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
    if (regs->cp0_epc & 1) {
        env->hflags |= MIPS_HFLAG_M16;
    }

#ifdef TARGET_ABI_MIPSO32
# define MAX_FP_ABI MIPS_ABI_FP_64A
#else
# define MAX_FP_ABI MIPS_ABI_FP_SOFT
#endif
     if ((info->fp_abi > MAX_FP_ABI && info->fp_abi != MIPS_ABI_FP_UNKNOWN)
        || (info->interp_fp_abi > MAX_FP_ABI &&
            info->interp_fp_abi != MIPS_ABI_FP_UNKNOWN)) {
        fprintf(stderr, "qemu: Unexpected FPU mode\n");
        exit(1);
    }

    prog_req = (info->fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req
                                            : fpu_reqs[info->fp_abi];
    interp_req = (info->interp_fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req
                                            : fpu_reqs[info->interp_fp_abi];

    prog_req.single &= interp_req.single;
    prog_req.soft &= interp_req.soft;
    prog_req.fr1 &= interp_req.fr1;
    prog_req.frdefault &= interp_req.frdefault;
    prog_req.fre &= interp_req.fre;

    bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 ||
                              env->insn_flags & ISA_MIPS_R6;

    if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) {
        env->CP0_Config5 |= (1 << CP0C5_FRE);
        if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
            env->hflags |= MIPS_HFLAG_FRE;
        }
    } else if ((prog_req.fr1 && prog_req.frdefault) ||
         (prog_req.single && !prog_req.frdefault)) {
        if ((env->active_fpu.fcr0 & (1 << FCR0_F64)
            && cpu_has_mips_r2_r6) || prog_req.fr1) {
            env->CP0_Status |= (1 << CP0St_FR);
            env->hflags |= MIPS_HFLAG_F64;
        }
    } else if (prog_req.fr1) {
        env->CP0_Status |= (1 << CP0St_FR);
        env->hflags |= MIPS_HFLAG_F64;
    } else if (!prog_req.fre && !prog_req.frdefault &&
          !prog_req.fr1 && !prog_req.single && !prog_req.soft) {
        fprintf(stderr, "qemu: Can't find a matching FPU mode\n");
        exit(1);
    }

    if (env->insn_flags & ISA_NANOMIPS32) {
        return;
    }
    if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
        ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
        if ((env->active_fpu.fcr31_rw_bitmask &
              (1 << FCR31_NAN2008)) == 0) {
            fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
            exit(1);
        }
        if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
            env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
        } else {
            env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
        }
        restore_snan_bit_mode(env);
    }
}
Commit	Line	Data
cd71c089 LV	1	/*
	2	* qemu user cpu loop
	3	*
	4	* Copyright (c) 2003-2008 Fabrice Bellard
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "qemu/osdep.h"
	21	#include "qemu.h"
3b249d26	22	#include "user-internals.h"
cd71c089	23	#include "cpu_loop-common.h"
2113aed6	24	#include "signal-common.h"
58908ef6	25	#include "elf.h"
502700d0	26	#include "internal.h"
81ddae7c	27	#include "fpu_helper.h"
58908ef6 LV	28
58908ef6 LV	29	# ifdef TARGET_ABI_MIPSO32
8d6d4c1b	30	# define MIPS_SYSCALL_NUMBER_UNUSED -1
8d6d4c1b	31	static const int8_t mips_syscall_args[] = {
ac5d3c67	32	#include "syscall-args-o32.c.inc"
58908ef6	33	};
58908ef6 LV	34	# endif /* O32 */
58908ef6 LV	35
58908ef6 LV	36	/* Break codes */
	37	enum {
	38	BRK_OVERFLOW = 6,
	39	BRK_DIVZERO = 7
	40	};
	41
bf19bdb8	42	static void do_tr_or_bp(CPUMIPSState *env, unsigned int code, bool trap)
58908ef6	43	{
bf19bdb8	44	target_ulong pc = env->active_tc.PC;
58908ef6 LV	45
	46	switch (code) {
	47	case BRK_OVERFLOW:
bf19bdb8 RH	48	force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, pc);
bf19bdb8 RH	49	break;
58908ef6	50	case BRK_DIVZERO:
bf19bdb8	51	force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, pc);
58908ef6 LV	52	break;
58908ef6 LV	53	default:
bf19bdb8 RH	54	if (trap) {
	55	force_sig(TARGET_SIGTRAP);
	56	} else {
	57	force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, pc);
	58	}
58908ef6 LV	59	break;
58908ef6 LV	60	}
58908ef6 LV	61	}
	62
	63	void cpu_loop(CPUMIPSState *env)
	64	{
5a7330b3	65	CPUState *cs = env_cpu(env);
73c0aa6a	66	int trapnr, si_code;
6f3533dd	67	unsigned int code;
58908ef6 LV	68	abi_long ret;
	69	# ifdef TARGET_ABI_MIPSO32
	70	unsigned int syscall_num;
	71	# endif
	72
	73	for(;;) {
	74	cpu_exec_start(cs);
	75	trapnr = cpu_exec(cs);
	76	cpu_exec_end(cs);
	77	process_queued_cpu_work(cs);
	78
	79	switch(trapnr) {
	80	case EXCP_SYSCALL:
	81	env->active_tc.PC += 4;
	82	# ifdef TARGET_ABI_MIPSO32
	83	syscall_num = env->active_tc.gpr[2] - 4000;
	84	if (syscall_num >= sizeof(mips_syscall_args)) {
8d6d4c1b AM	85	/* syscall_num is larger that any defined for MIPS O32 */
	86	ret = -TARGET_ENOSYS;
	87	} else if (mips_syscall_args[syscall_num] ==
	88	MIPS_SYSCALL_NUMBER_UNUSED) {
	89	/* syscall_num belongs to the range not defined for MIPS O32 */
58908ef6 LV	90	ret = -TARGET_ENOSYS;
58908ef6 LV	91	} else {
8d6d4c1b	92	/* syscall_num is valid */
58908ef6 LV	93	int nb_args;
	94	abi_ulong sp_reg;
	95	abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
	96
	97	nb_args = mips_syscall_args[syscall_num];
	98	sp_reg = env->active_tc.gpr[29];
	99	switch (nb_args) {
	100	/* these arguments are taken from the stack */
	101	case 8:
	102	if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
	103	goto done_syscall;
	104	}
81966c18	105	/* fall through */
58908ef6 LV	106	case 7:
	107	if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
	108	goto done_syscall;
	109	}
81966c18	110	/* fall through */
58908ef6 LV	111	case 6:
	112	if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
	113	goto done_syscall;
	114	}
81966c18	115	/* fall through */
58908ef6 LV	116	case 5:
	117	if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
	118	goto done_syscall;
	119	}
81966c18	120	/* fall through */
58908ef6 LV	121	default:
	122	break;
	123	}
	124	ret = do_syscall(env, env->active_tc.gpr[2],
	125	env->active_tc.gpr[4],
	126	env->active_tc.gpr[5],
	127	env->active_tc.gpr[6],
	128	env->active_tc.gpr[7],
	129	arg5, arg6, arg7, arg8);
	130	}
	131	done_syscall:
	132	# else
	133	ret = do_syscall(env, env->active_tc.gpr[2],
	134	env->active_tc.gpr[4], env->active_tc.gpr[5],
	135	env->active_tc.gpr[6], env->active_tc.gpr[7],
	136	env->active_tc.gpr[8], env->active_tc.gpr[9],
	137	env->active_tc.gpr[10], env->active_tc.gpr[11]);
	138	# endif /* O32 */
af254a27	139	if (ret == -QEMU_ERESTARTSYS) {
58908ef6 LV	140	env->active_tc.PC -= 4;
	141	break;
	142	}
57a0c938	143	if (ret == -QEMU_ESIGRETURN) {
58908ef6 LV	144	/* Returning from a successful sigreturn syscall.
	145	Avoid clobbering register state. */
	146	break;
	147	}
	148	if ((abi_ulong)ret >= (abi_ulong)-1133) {
	149	env->active_tc.gpr[7] = 1; /* error flag */
	150	ret = -ret;
	151	} else {
	152	env->active_tc.gpr[7] = 0; /* error flag */
	153	}
	154	env->active_tc.gpr[2] = ret;
	155	break;
58908ef6 LV	156	case EXCP_CpU:
58908ef6 LV	157	case EXCP_RI:
73c0aa6a RH	158	case EXCP_DSPDIS:
73c0aa6a RH	159	force_sig(TARGET_SIGILL);
58908ef6 LV	160	break;
	161	case EXCP_INTERRUPT:
	162	/* just indicate that signals should be handled asap */
	163	break;
	164	case EXCP_DEBUG:
73c0aa6a RH	165	force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT,
73c0aa6a RH	166	env->active_tc.PC);
58908ef6	167	break;
64ce541c	168	case EXCP_FPE:
73c0aa6a	169	si_code = TARGET_FPE_FLTUNK;
64ce541c	170	if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) {
73c0aa6a	171	si_code = TARGET_FPE_FLTINV;
64ce541c	172	} else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_DIV0) {
73c0aa6a	173	si_code = TARGET_FPE_FLTDIV;
64ce541c	174	} else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_OVERFLOW) {
73c0aa6a	175	si_code = TARGET_FPE_FLTOVF;
64ce541c	176	} else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_UNDERFLOW) {
73c0aa6a	177	si_code = TARGET_FPE_FLTUND;
64ce541c	178	} else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INEXACT) {
73c0aa6a	179	si_code = TARGET_FPE_FLTRES;
64ce541c	180	}
73c0aa6a	181	force_sig_fault(TARGET_SIGFPE, si_code, env->active_tc.PC);
64ce541c	182	break;
6fad9b4b MP	183	case EXCP_OVERFLOW:
	184	force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->active_tc.PC);
	185	break;
58908ef6 LV	186	/* The code below was inspired by the MIPS Linux kernel trap
	187	* handling code in arch/mips/kernel/traps.c.
	188	*/
	189	case EXCP_BREAK:
6f3533dd RH	190	/*
	191	* As described in the original Linux kernel code, the below
	192	* checks on 'code' are to work around an old assembly bug.
	193	*/
	194	code = env->error_code;
	195	if (code >= (1 << 10)) {
	196	code >>= 10;
58908ef6	197	}
6f3533dd	198	do_tr_or_bp(env, code, false);
58908ef6 LV	199	break;
58908ef6 LV	200	case EXCP_TRAP:
0a3336f6	201	do_tr_or_bp(env, env->error_code, true);
58908ef6 LV	202	break;
	203	case EXCP_ATOMIC:
	204	cpu_exec_step_atomic(cs);
	205	break;
	206	default:
58908ef6 LV	207	EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
	208	abort();
	209	}
	210	process_pending_signals(env);
	211	}
	212	}
cd71c089 LV	213
	214	void target_cpu_copy_regs(CPUArchState env, struct target_pt_regs regs)
	215	{
29a0af61	216	CPUState *cpu = env_cpu(env);
e4e5cb4a	217	TaskState *ts = get_task_state(cpu);
58908ef6 LV	218	struct image_info *info = ts->info;
	219	int i;
	220
0c1bbedc SM	221	struct mode_req {
	222	bool single;
	223	bool soft;
	224	bool fr1;
	225	bool frdefault;
	226	bool fre;
	227	};
	228
	229	static const struct mode_req fpu_reqs[] = {
	230	[MIPS_ABI_FP_ANY] = { true, true, true, true, true },
	231	[MIPS_ABI_FP_DOUBLE] = { false, false, false, true, true },
	232	[MIPS_ABI_FP_SINGLE] = { true, false, false, false, false },
	233	[MIPS_ABI_FP_SOFT] = { false, true, false, false, false },
	234	[MIPS_ABI_FP_OLD_64] = { false, false, false, false, false },
	235	[MIPS_ABI_FP_XX] = { false, false, true, true, true },
	236	[MIPS_ABI_FP_64] = { false, false, true, false, false },
	237	[MIPS_ABI_FP_64A] = { false, false, true, false, true }
	238	};
	239
	240	/*
	241	* Mode requirements when .MIPS.abiflags is not present in the ELF.
	242	* Not present means that everything is acceptable except FR1.
	243	*/
	244	static struct mode_req none_req = { true, true, false, true, true };
	245
	246	struct mode_req prog_req;
	247	struct mode_req interp_req;
	248
58908ef6 LV	249	for(i = 0; i < 32; i++) {
	250	env->active_tc.gpr[i] = regs->regs[i];
	251	}
	252	env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
	253	if (regs->cp0_epc & 1) {
	254	env->hflags \|= MIPS_HFLAG_M16;
	255	}
0c1bbedc SM	256
	257	#ifdef TARGET_ABI_MIPSO32
	258	# define MAX_FP_ABI MIPS_ABI_FP_64A
	259	#else
	260	# define MAX_FP_ABI MIPS_ABI_FP_SOFT
	261	#endif
	262	if ((info->fp_abi > MAX_FP_ABI && info->fp_abi != MIPS_ABI_FP_UNKNOWN)
	263	\|\| (info->interp_fp_abi > MAX_FP_ABI &&
	264	info->interp_fp_abi != MIPS_ABI_FP_UNKNOWN)) {
	265	fprintf(stderr, "qemu: Unexpected FPU mode\n");
	266	exit(1);
	267	}
	268
	269	prog_req = (info->fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req
	270	: fpu_reqs[info->fp_abi];
	271	interp_req = (info->interp_fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req
	272	: fpu_reqs[info->interp_fp_abi];
	273
	274	prog_req.single &= interp_req.single;
	275	prog_req.soft &= interp_req.soft;
	276	prog_req.fr1 &= interp_req.fr1;
	277	prog_req.frdefault &= interp_req.frdefault;
	278	prog_req.fre &= interp_req.fre;
	279
7a47bae5	280	bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 \|\|
2e211e0a	281	env->insn_flags & ISA_MIPS_R6;
0c1bbedc SM	282
	283	if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) {
	284	env->CP0_Config5 \|= (1 << CP0C5_FRE);
	285	if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
	286	env->hflags \|= MIPS_HFLAG_FRE;
	287	}
	288	} else if ((prog_req.fr1 && prog_req.frdefault) \|\|
	289	(prog_req.single && !prog_req.frdefault)) {
	290	if ((env->active_fpu.fcr0 & (1 << FCR0_F64)
	291	&& cpu_has_mips_r2_r6) \|\| prog_req.fr1) {
	292	env->CP0_Status \|= (1 << CP0St_FR);
	293	env->hflags \|= MIPS_HFLAG_F64;
	294	}
a0f8d270 DK	295	} else if (prog_req.fr1) {
	296	env->CP0_Status \|= (1 << CP0St_FR);
	297	env->hflags \|= MIPS_HFLAG_F64;
	298	} else if (!prog_req.fre && !prog_req.frdefault &&
0c1bbedc SM	299	!prog_req.fr1 && !prog_req.single && !prog_req.soft) {
	300	fprintf(stderr, "qemu: Can't find a matching FPU mode\n");
	301	exit(1);
	302	}
	303
722ac96c AM	304	if (env->insn_flags & ISA_NANOMIPS32) {
	305	return;
	306	}
58908ef6 LV	307	if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
	308	((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
	309	if ((env->active_fpu.fcr31_rw_bitmask &
	310	(1 << FCR31_NAN2008)) == 0) {
	311	fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
	312	exit(1);
	313	}
	314	if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
	315	env->active_fpu.fcr31 \|= (1 << FCR31_NAN2008);
	316	} else {
	317	env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
	318	}
	319	restore_snan_bit_mode(env);
	320	}
cd71c089	321	}