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cd71c089 LV |
1 | /* |
2 | * qemu user cpu loop | |
3 | * | |
4 | * Copyright (c) 2003-2008 Fabrice Bellard | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu.h" | |
3b249d26 | 22 | #include "user-internals.h" |
cd71c089 | 23 | #include "cpu_loop-common.h" |
2113aed6 | 24 | #include "signal-common.h" |
cd71c089 | 25 | |
a5fd8ee1 | 26 | |
ccb5f270 JA |
27 | static int get_pgm_data_si_code(int dxc_code) |
28 | { | |
29 | switch (dxc_code) { | |
30 | /* Non-simulated IEEE exceptions */ | |
31 | case 0x80: | |
32 | return TARGET_FPE_FLTINV; | |
33 | case 0x40: | |
34 | return TARGET_FPE_FLTDIV; | |
35 | case 0x20: | |
36 | case 0x28: | |
37 | case 0x2c: | |
38 | return TARGET_FPE_FLTOVF; | |
39 | case 0x10: | |
40 | case 0x18: | |
41 | case 0x1c: | |
42 | return TARGET_FPE_FLTUND; | |
43 | case 0x08: | |
44 | case 0x0c: | |
45 | return TARGET_FPE_FLTRES; | |
46 | } | |
47 | /* | |
48 | * Non-IEEE and simulated IEEE: | |
49 | * Includes compare-and-trap, quantum exception, etc. | |
50 | * Simulated IEEE are included here to match current | |
51 | * s390x linux kernel. | |
52 | */ | |
53 | return 0; | |
54 | } | |
55 | ||
a5fd8ee1 LV |
56 | void cpu_loop(CPUS390XState *env) |
57 | { | |
dc79e928 | 58 | CPUState *cs = env_cpu(env); |
a5fd8ee1 | 59 | int trapnr, n, sig; |
a5fd8ee1 LV |
60 | target_ulong addr; |
61 | abi_long ret; | |
62 | ||
63 | while (1) { | |
64 | cpu_exec_start(cs); | |
65 | trapnr = cpu_exec(cs); | |
66 | cpu_exec_end(cs); | |
67 | process_queued_cpu_work(cs); | |
68 | ||
69 | switch (trapnr) { | |
70 | case EXCP_INTERRUPT: | |
71 | /* Just indicate that signals should be handled asap. */ | |
72 | break; | |
73 | ||
74 | case EXCP_SVC: | |
75 | n = env->int_svc_code; | |
76 | if (!n) { | |
77 | /* syscalls > 255 */ | |
78 | n = env->regs[1]; | |
79 | } | |
80 | env->psw.addr += env->int_svc_ilen; | |
81 | ret = do_syscall(env, n, env->regs[2], env->regs[3], | |
82 | env->regs[4], env->regs[5], | |
83 | env->regs[6], env->regs[7], 0, 0); | |
af254a27 | 84 | if (ret == -QEMU_ERESTARTSYS) { |
a5fd8ee1 | 85 | env->psw.addr -= env->int_svc_ilen; |
57a0c938 | 86 | } else if (ret != -QEMU_ESIGRETURN) { |
a5fd8ee1 LV |
87 | env->regs[2] = ret; |
88 | } | |
89 | break; | |
90 | ||
91 | case EXCP_DEBUG: | |
b10089a1 PM |
92 | sig = TARGET_SIGTRAP; |
93 | n = TARGET_TRAP_BRKPT; | |
54ba2161 IL |
94 | /* |
95 | * For SIGTRAP the PSW must point after the instruction, which it | |
96 | * already does thanks to s390x_tr_tb_stop(). si_addr doesn't need | |
97 | * to be filled. | |
98 | */ | |
99 | addr = 0; | |
100 | goto do_signal; | |
a5fd8ee1 LV |
101 | case EXCP_PGM: |
102 | n = env->int_pgm_code; | |
103 | switch (n) { | |
104 | case PGM_OPERATION: | |
105 | case PGM_PRIVILEGED: | |
106 | sig = TARGET_SIGILL; | |
107 | n = TARGET_ILL_ILLOPC; | |
108 | goto do_signal_pc; | |
109 | case PGM_PROTECTION: | |
c8e7fef1 RH |
110 | force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_ACCERR, |
111 | env->__excp_addr); | |
112 | break; | |
a5fd8ee1 | 113 | case PGM_ADDRESSING: |
c8e7fef1 RH |
114 | force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, |
115 | env->__excp_addr); | |
116 | break; | |
a5fd8ee1 LV |
117 | case PGM_EXECUTE: |
118 | case PGM_SPECIFICATION: | |
119 | case PGM_SPECIAL_OP: | |
120 | case PGM_OPERAND: | |
121 | do_sigill_opn: | |
122 | sig = TARGET_SIGILL; | |
123 | n = TARGET_ILL_ILLOPN; | |
124 | goto do_signal_pc; | |
125 | ||
126 | case PGM_FIXPT_OVERFLOW: | |
127 | sig = TARGET_SIGFPE; | |
128 | n = TARGET_FPE_INTOVF; | |
129 | goto do_signal_pc; | |
130 | case PGM_FIXPT_DIVIDE: | |
131 | sig = TARGET_SIGFPE; | |
132 | n = TARGET_FPE_INTDIV; | |
133 | goto do_signal_pc; | |
134 | ||
135 | case PGM_DATA: | |
136 | n = (env->fpc >> 8) & 0xff; | |
ccb5f270 | 137 | if (n == 0) { |
a5fd8ee1 | 138 | goto do_sigill_opn; |
a5fd8ee1 LV |
139 | } |
140 | ||
ccb5f270 JA |
141 | sig = TARGET_SIGFPE; |
142 | n = get_pgm_data_si_code(n); | |
143 | goto do_signal_pc; | |
144 | ||
a5fd8ee1 LV |
145 | default: |
146 | fprintf(stderr, "Unhandled program exception: %#x\n", n); | |
90c84c56 | 147 | cpu_dump_state(cs, stderr, 0); |
a5fd8ee1 LV |
148 | exit(EXIT_FAILURE); |
149 | } | |
150 | break; | |
151 | ||
152 | do_signal_pc: | |
153 | addr = env->psw.addr; | |
54ba2161 IL |
154 | /* |
155 | * For SIGILL and SIGFPE the PSW must point after the instruction. | |
156 | */ | |
157 | env->psw.addr += env->int_pgm_ilen; | |
a5fd8ee1 | 158 | do_signal: |
8f0bebeb | 159 | force_sig_fault(sig, n, addr); |
a5fd8ee1 LV |
160 | break; |
161 | ||
162 | case EXCP_ATOMIC: | |
163 | cpu_exec_step_atomic(cs); | |
164 | break; | |
165 | default: | |
166 | fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr); | |
90c84c56 | 167 | cpu_dump_state(cs, stderr, 0); |
a5fd8ee1 LV |
168 | exit(EXIT_FAILURE); |
169 | } | |
170 | process_pending_signals (env); | |
171 | } | |
172 | } | |
173 | ||
cd71c089 LV |
174 | void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) |
175 | { | |
a5fd8ee1 LV |
176 | int i; |
177 | for (i = 0; i < 16; i++) { | |
178 | env->regs[i] = regs->gprs[i]; | |
179 | } | |
180 | env->psw.mask = regs->psw.mask; | |
181 | env->psw.addr = regs->psw.addr; | |
cd71c089 | 182 | } |