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CommitLineData
dd83b06a
AF
1/*
2 * QEMU CPU model
3 *
1590bbcb 4 * Copyright (c) 2012-2014 SUSE LINUX Products GmbH
dd83b06a
AF
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
1ef26b1f 21#include "qemu/osdep.h"
da34e65c 22#include "qapi/error.h"
dd83b06a 23#include "qemu-common.h"
878096ee 24#include "qom/cpu.h"
b3946626 25#include "sysemu/hw_accel.h"
066e9b27 26#include "qemu/notify.h"
91b1df8c 27#include "qemu/log.h"
508127e2 28#include "exec/log.h"
2cd53943 29#include "exec/cpu-common.h"
9262685b 30#include "qemu/error-report.h"
066e9b27 31#include "sysemu/sysemu.h"
ed860129 32#include "hw/boards.h"
62a48a2a 33#include "hw/qdev-properties.h"
0ab8ed18 34#include "trace-root.h"
066e9b27 35
290dae46
PB
36CPUInterruptHandler cpu_interrupt_handler;
37
5ce46cb3 38CPUState *cpu_by_arch_id(int64_t id)
69e5ff06 39{
38fcbd3f
AF
40 CPUState *cpu;
41
42 CPU_FOREACH(cpu) {
43 CPUClass *cc = CPU_GET_CLASS(cpu);
69e5ff06 44
38fcbd3f 45 if (cc->get_arch_id(cpu) == id) {
5ce46cb3 46 return cpu;
38fcbd3f
AF
47 }
48 }
5ce46cb3
EH
49 return NULL;
50}
51
52bool cpu_exists(int64_t id)
53{
54 return !!cpu_by_arch_id(id);
69e5ff06
IM
55}
56
3c72234c
IM
57CPUState *cpu_create(const char *typename)
58{
59 Error *err = NULL;
60 CPUState *cpu = CPU(object_new(typename));
61 object_property_set_bool(OBJECT(cpu), true, "realized", &err);
62 if (err != NULL) {
63 error_report_err(err);
64 object_unref(OBJECT(cpu));
4482e05c 65 exit(EXIT_FAILURE);
3c72234c
IM
66 }
67 return cpu;
68}
69
444d5590
AF
70bool cpu_paging_enabled(const CPUState *cpu)
71{
72 CPUClass *cc = CPU_GET_CLASS(cpu);
73
74 return cc->get_paging_enabled(cpu);
75}
76
77static bool cpu_common_get_paging_enabled(const CPUState *cpu)
78{
6db297ea 79 return false;
444d5590
AF
80}
81
a23bbfda
AF
82void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
83 Error **errp)
84{
85 CPUClass *cc = CPU_GET_CLASS(cpu);
86
fbe95bfb 87 cc->get_memory_mapping(cpu, list, errp);
a23bbfda
AF
88}
89
90static void cpu_common_get_memory_mapping(CPUState *cpu,
91 MemoryMappingList *list,
92 Error **errp)
93{
94 error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
95}
96
8d04fb55
JK
97/* Resetting the IRQ comes from across the code base so we take the
98 * BQL here if we need to. cpu_interrupt assumes it is held.*/
d8ed887b
AF
99void cpu_reset_interrupt(CPUState *cpu, int mask)
100{
8d04fb55
JK
101 bool need_lock = !qemu_mutex_iothread_locked();
102
103 if (need_lock) {
104 qemu_mutex_lock_iothread();
105 }
d8ed887b 106 cpu->interrupt_request &= ~mask;
8d04fb55
JK
107 if (need_lock) {
108 qemu_mutex_unlock_iothread();
109 }
d8ed887b
AF
110}
111
60a3e17a
AF
112void cpu_exit(CPUState *cpu)
113{
027d9a7d 114 atomic_set(&cpu->exit_request, 1);
ab096a75
PB
115 /* Ensure cpu_exec will see the exit request after TCG has exited. */
116 smp_wmb();
1aab16c2 117 atomic_set(&cpu->icount_decr.u16.high, -1);
60a3e17a
AF
118}
119
c72bf468
JF
120int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
121 void *opaque)
122{
123 CPUClass *cc = CPU_GET_CLASS(cpu);
124
125 return (*cc->write_elf32_qemunote)(f, cpu, opaque);
126}
127
128static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
129 CPUState *cpu, void *opaque)
130{
b09afd58 131 return 0;
c72bf468
JF
132}
133
134int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
135 int cpuid, void *opaque)
136{
137 CPUClass *cc = CPU_GET_CLASS(cpu);
138
139 return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
140}
141
142static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
143 CPUState *cpu, int cpuid,
144 void *opaque)
145{
146 return -1;
147}
148
149int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
150 void *opaque)
151{
152 CPUClass *cc = CPU_GET_CLASS(cpu);
153
154 return (*cc->write_elf64_qemunote)(f, cpu, opaque);
155}
156
157static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
158 CPUState *cpu, void *opaque)
159{
b09afd58 160 return 0;
c72bf468
JF
161}
162
163int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
164 int cpuid, void *opaque)
165{
166 CPUClass *cc = CPU_GET_CLASS(cpu);
167
168 return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
169}
170
171static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
172 CPUState *cpu, int cpuid,
173 void *opaque)
174{
175 return -1;
176}
177
178
5b50e790
AF
179static int cpu_common_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg)
180{
181 return 0;
182}
183
184static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
185{
186 return 0;
187}
188
568496c0
SF
189static bool cpu_common_debug_check_watchpoint(CPUState *cpu, CPUWatchpoint *wp)
190{
191 /* If no extra check is required, QEMU watchpoint match can be considered
192 * as an architectural match.
193 */
194 return true;
195}
196
bf7663c4
GK
197static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
198{
199 return target_words_bigendian();
200}
5b50e790 201
cffe7b32 202static void cpu_common_noop(CPUState *cpu)
86025ee4
PM
203{
204}
205
9585db68
RH
206static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req)
207{
208 return false;
209}
210
c86f106b
AN
211GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
212{
213 CPUClass *cc = CPU_GET_CLASS(cpu);
214 GuestPanicInformation *res = NULL;
215
216 if (cc->get_crash_info) {
217 res = cc->get_crash_info(cpu);
218 }
219 return res;
220}
221
878096ee
AF
222void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
223 int flags)
224{
225 CPUClass *cc = CPU_GET_CLASS(cpu);
226
227 if (cc->dump_state) {
97577fd4 228 cpu_synchronize_state(cpu);
878096ee
AF
229 cc->dump_state(cpu, f, cpu_fprintf, flags);
230 }
231}
232
233void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
234 int flags)
235{
236 CPUClass *cc = CPU_GET_CLASS(cpu);
237
238 if (cc->dump_statistics) {
239 cc->dump_statistics(cpu, f, cpu_fprintf, flags);
240 }
241}
242
dd83b06a
AF
243void cpu_reset(CPUState *cpu)
244{
245 CPUClass *klass = CPU_GET_CLASS(cpu);
246
247 if (klass->reset != NULL) {
248 (*klass->reset)(cpu);
249 }
2cc2d082
LV
250
251 trace_guest_cpu_reset(cpu);
dd83b06a
AF
252}
253
254static void cpu_common_reset(CPUState *cpu)
255{
91b1df8c
AF
256 CPUClass *cc = CPU_GET_CLASS(cpu);
257
258 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
259 qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);
260 log_cpu_state(cpu, cc->reset_dump_flags);
261 }
262
259186a7 263 cpu->interrupt_request = 0;
259186a7 264 cpu->halted = 0;
93afeade
AF
265 cpu->mem_io_pc = 0;
266 cpu->mem_io_vaddr = 0;
efee7340 267 cpu->icount_extra = 0;
fff42f18 268 atomic_set(&cpu->icount_decr.u32, 0);
414b15c9 269 cpu->can_do_io = 1;
f9d8f667 270 cpu->exception_index = -1;
bac05aa9 271 cpu->crash_occurred = false;
9b990ee5 272 cpu->cflags_next_tb = -1;
ce7cf6a9 273
ba7d3d18 274 if (tcg_enabled()) {
f3ced3c5 275 cpu_tb_jmp_cache_clear(cpu);
1f5c00cf 276
2cd53943 277 tcg_flush_softmmu_tlb(cpu);
ba7d3d18 278 }
dd83b06a
AF
279}
280
8c2e1b00
AF
281static bool cpu_common_has_work(CPUState *cs)
282{
283 return false;
284}
285
2b8c2754
AF
286ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
287{
99193d8f 288 CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
2b8c2754 289
99193d8f 290 assert(cpu_model && cc->class_by_name);
2b8c2754
AF
291 return cc->class_by_name(cpu_model);
292}
293
62a48a2a 294static void cpu_common_parse_features(const char *typename, char *features,
1590bbcb
AF
295 Error **errp)
296{
1590bbcb 297 char *val;
62a48a2a 298 static bool cpu_globals_initialized;
2278b939
IM
299 /* Single "key=value" string being parsed */
300 char *featurestr = features ? strtok(features, ",") : NULL;
62a48a2a 301
2278b939
IM
302 /* should be called only once, catch invalid users */
303 assert(!cpu_globals_initialized);
62a48a2a 304 cpu_globals_initialized = true;
1590bbcb 305
1590bbcb
AF
306 while (featurestr) {
307 val = strchr(featurestr, '=');
308 if (val) {
62a48a2a 309 GlobalProperty *prop = g_new0(typeof(*prop), 1);
1590bbcb
AF
310 *val = 0;
311 val++;
62a48a2a
IM
312 prop->driver = typename;
313 prop->property = g_strdup(featurestr);
314 prop->value = g_strdup(val);
62a48a2a 315 qdev_prop_register_global(prop);
1590bbcb
AF
316 } else {
317 error_setg(errp, "Expected key=value format, found %s.",
318 featurestr);
319 return;
320 }
321 featurestr = strtok(NULL, ",");
322 }
323}
324
4f658099
AF
325static void cpu_common_realizefn(DeviceState *dev, Error **errp)
326{
13eed94e 327 CPUState *cpu = CPU(dev);
ed860129
PM
328 Object *machine = qdev_get_machine();
329
330 /* qdev_get_machine() can return something that's not TYPE_MACHINE
331 * if this is one of the user-only emulators; in that case there's
332 * no need to check the ignore_memory_transaction_failures board flag.
333 */
334 if (object_dynamic_cast(machine, TYPE_MACHINE)) {
335 ObjectClass *oc = object_get_class(machine);
336 MachineClass *mc = MACHINE_CLASS(oc);
337
338 if (mc) {
339 cpu->ignore_memory_transaction_failures =
340 mc->ignore_memory_transaction_failures;
341 }
342 }
13eed94e
IM
343
344 if (dev->hotplugged) {
345 cpu_synchronize_post_init(cpu);
6afb4721 346 cpu_resume(cpu);
13eed94e 347 }
2bfe11c8
LV
348
349 /* NOTE: latest generic point where the cpu is fully realized */
350 trace_init_vcpu(cpu);
4f658099
AF
351}
352
7bbc124e
LV
353static void cpu_common_unrealizefn(DeviceState *dev, Error **errp)
354{
355 CPUState *cpu = CPU(dev);
82e95ec8
LV
356 /* NOTE: latest generic point before the cpu is fully unrealized */
357 trace_fini_vcpu(cpu);
7bbc124e
LV
358 cpu_exec_unrealizefn(cpu);
359}
360
a0e372f0
AF
361static void cpu_common_initfn(Object *obj)
362{
363 CPUState *cpu = CPU(obj);
364 CPUClass *cc = CPU_GET_CLASS(obj);
365
a07f953e 366 cpu->cpu_index = UNASSIGNED_CPU_INDEX;
7ea7b9ad 367 cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX;
35143f01 368 cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
fa5376dd
MAL
369 /* *-user doesn't have configurable SMP topology */
370 /* the default value is changed by qemu_init_vcpu() for softmmu */
371 cpu->nr_cores = 1;
372 cpu->nr_threads = 1;
373
376692b9 374 qemu_mutex_init(&cpu->work_mutex);
7c39163e
EH
375 QTAILQ_INIT(&cpu->breakpoints);
376 QTAILQ_INIT(&cpu->watchpoints);
b7d48952 377
39e329e3 378 cpu_exec_initfn(cpu);
a0e372f0
AF
379}
380
b7bca733
BR
381static void cpu_common_finalize(Object *obj)
382{
b7bca733
BR
383}
384
997395d3
IM
385static int64_t cpu_common_get_arch_id(CPUState *cpu)
386{
387 return cpu->cpu_index;
388}
389
40612000
JB
390static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)
391{
392 return addr;
393}
394
290dae46
PB
395static void generic_handle_interrupt(CPUState *cpu, int mask)
396{
397 cpu->interrupt_request |= mask;
398
399 if (!qemu_cpu_is_self(cpu)) {
400 qemu_cpu_kick(cpu);
401 }
402}
403
404CPUInterruptHandler cpu_interrupt_handler = generic_handle_interrupt;
405
dd83b06a
AF
406static void cpu_class_init(ObjectClass *klass, void *data)
407{
961f8395 408 DeviceClass *dc = DEVICE_CLASS(klass);
dd83b06a
AF
409 CPUClass *k = CPU_CLASS(klass);
410
1590bbcb 411 k->parse_features = cpu_common_parse_features;
dd83b06a 412 k->reset = cpu_common_reset;
997395d3 413 k->get_arch_id = cpu_common_get_arch_id;
8c2e1b00 414 k->has_work = cpu_common_has_work;
444d5590 415 k->get_paging_enabled = cpu_common_get_paging_enabled;
a23bbfda 416 k->get_memory_mapping = cpu_common_get_memory_mapping;
c72bf468
JF
417 k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
418 k->write_elf32_note = cpu_common_write_elf32_note;
419 k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
420 k->write_elf64_note = cpu_common_write_elf64_note;
5b50e790
AF
421 k->gdb_read_register = cpu_common_gdb_read_register;
422 k->gdb_write_register = cpu_common_gdb_write_register;
bf7663c4 423 k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
cffe7b32 424 k->debug_excp_handler = cpu_common_noop;
568496c0 425 k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
cffe7b32
RH
426 k->cpu_exec_enter = cpu_common_noop;
427 k->cpu_exec_exit = cpu_common_noop;
9585db68 428 k->cpu_exec_interrupt = cpu_common_exec_interrupt;
40612000 429 k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
ba31cc72 430 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
4f658099 431 dc->realize = cpu_common_realizefn;
7bbc124e 432 dc->unrealize = cpu_common_unrealizefn;
c7e002c5 433 dc->props = cpu_common_props;
ffa95714
MA
434 /*
435 * Reason: CPUs still need special care by board code: wiring up
436 * IRQs, adding reset handlers, halting non-first CPUs, ...
437 */
e90f2a8c 438 dc->user_creatable = false;
dd83b06a
AF
439}
440
961f8395 441static const TypeInfo cpu_type_info = {
dd83b06a 442 .name = TYPE_CPU,
961f8395 443 .parent = TYPE_DEVICE,
dd83b06a 444 .instance_size = sizeof(CPUState),
a0e372f0 445 .instance_init = cpu_common_initfn,
b7bca733 446 .instance_finalize = cpu_common_finalize,
dd83b06a
AF
447 .abstract = true,
448 .class_size = sizeof(CPUClass),
449 .class_init = cpu_class_init,
450};
451
452static void cpu_register_types(void)
453{
454 type_register_static(&cpu_type_info);
455}
456
457type_init(cpu_register_types)