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c7f0f3b1
AL
1/*
2 * Test Server
3 *
4 * Copyright IBM, Corp. 2011
5 *
6 * Authors:
7 * Anthony Liguori <aliguori@us.ibm.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
11 *
12 */
13
d38ea87a 14#include "qemu/osdep.h"
9c17d615 15#include "sysemu/qtest.h"
20288345 16#include "hw/qdev.h"
dccfcd0e 17#include "sysemu/char.h"
022c62cb
PB
18#include "exec/ioport.h"
19#include "exec/memory.h"
c7f0f3b1 20#include "hw/irq.h"
3a6ce514 21#include "sysemu/accel.h"
9c17d615
PB
22#include "sysemu/sysemu.h"
23#include "sysemu/cpus.h"
1ad9580b
ST
24#include "qemu/config-file.h"
25#include "qemu/option.h"
26#include "qemu/error-report.h"
c7f0f3b1
AL
27
28#define MAX_IRQ 256
29
d5286af5 30bool qtest_allowed;
c7f0f3b1 31
20288345 32static DeviceState *irq_intercept_dev;
c7f0f3b1
AL
33static FILE *qtest_log_fp;
34static CharDriverState *qtest_chr;
35static GString *inbuf;
36static int irq_levels[MAX_IRQ];
6e92466a 37static qemu_timeval start_time;
c7f0f3b1
AL
38static bool qtest_opened;
39
6b7cff76 40#define FMT_timeval "%ld.%06ld"
c7f0f3b1
AL
41
42/**
43 * QTest Protocol
44 *
45 * Line based protocol, request/response based. Server can send async messages
46 * so clients should always handle many async messages before the response
47 * comes in.
48 *
49 * Valid requests
50 *
8156be56
PB
51 * Clock management:
52 *
bc72ad67 53 * The qtest client is completely in charge of the QEMU_CLOCK_VIRTUAL. qtest commands
8156be56
PB
54 * let you adjust the value of the clock (monotonically). All the commands
55 * return the current value of the clock in nanoseconds.
56 *
57 * > clock_step
58 * < OK VALUE
59 *
60 * Advance the clock to the next deadline. Useful when waiting for
61 * asynchronous events.
62 *
63 * > clock_step NS
64 * < OK VALUE
65 *
66 * Advance the clock by NS nanoseconds.
67 *
68 * > clock_set NS
69 * < OK VALUE
70 *
71 * Advance the clock to NS nanoseconds (do nothing if it's already past).
72 *
73 * PIO and memory access:
74 *
c7f0f3b1
AL
75 * > outb ADDR VALUE
76 * < OK
77 *
78 * > outw ADDR VALUE
79 * < OK
80 *
81 * > outl ADDR VALUE
82 * < OK
83 *
84 * > inb ADDR
85 * < OK VALUE
86 *
87 * > inw ADDR
88 * < OK VALUE
89 *
90 * > inl ADDR
91 * < OK VALUE
92 *
872536bf
AF
93 * > writeb ADDR VALUE
94 * < OK
95 *
96 * > writew ADDR VALUE
97 * < OK
98 *
99 * > writel ADDR VALUE
100 * < OK
101 *
102 * > writeq ADDR VALUE
103 * < OK
104 *
105 * > readb ADDR
106 * < OK VALUE
107 *
108 * > readw ADDR
109 * < OK VALUE
110 *
111 * > readl ADDR
112 * < OK VALUE
113 *
114 * > readq ADDR
115 * < OK VALUE
116 *
c7f0f3b1
AL
117 * > read ADDR SIZE
118 * < OK DATA
119 *
120 * > write ADDR SIZE DATA
121 * < OK
122 *
7a6a740d
JS
123 * > b64read ADDR SIZE
124 * < OK B64_DATA
125 *
126 * > b64write ADDR SIZE B64_DATA
127 * < OK
128 *
4d007963
JS
129 * > memset ADDR SIZE VALUE
130 * < OK
131 *
c7f0f3b1
AL
132 * ADDR, SIZE, VALUE are all integers parsed with strtoul() with a base of 0.
133 *
134 * DATA is an arbitrarily long hex number prefixed with '0x'. If it's smaller
135 * than the expected size, the value will be zero filled at the end of the data
136 * sequence.
137 *
7a6a740d
JS
138 * B64_DATA is an arbitrarily long base64 encoded string.
139 * If the sizes do not match, the data will be truncated.
140 *
20288345
PB
141 * IRQ management:
142 *
143 * > irq_intercept_in QOM-PATH
144 * < OK
145 *
146 * > irq_intercept_out QOM-PATH
147 * < OK
148 *
149 * Attach to the gpio-in (resp. gpio-out) pins exported by the device at
150 * QOM-PATH. When the pin is triggered, one of the following async messages
151 * will be printed to the qtest stream:
152 *
153 * IRQ raise NUM
154 * IRQ lower NUM
155 *
156 * where NUM is an IRQ number. For the PC, interrupts can be intercepted
157 * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
158 * NUM=0 even though it is remapped to GSI 2).
c7f0f3b1
AL
159 */
160
161static int hex2nib(char ch)
162{
163 if (ch >= '0' && ch <= '9') {
164 return ch - '0';
165 } else if (ch >= 'a' && ch <= 'f') {
166 return 10 + (ch - 'a');
167 } else if (ch >= 'A' && ch <= 'F') {
2a802aaf 168 return 10 + (ch - 'A');
c7f0f3b1
AL
169 } else {
170 return -1;
171 }
172}
173
6e92466a 174static void qtest_get_time(qemu_timeval *tv)
c7f0f3b1 175{
6e92466a 176 qemu_gettimeofday(tv);
c7f0f3b1
AL
177 tv->tv_sec -= start_time.tv_sec;
178 tv->tv_usec -= start_time.tv_usec;
179 if (tv->tv_usec < 0) {
180 tv->tv_usec += 1000000;
181 tv->tv_sec -= 1;
182 }
183}
184
185static void qtest_send_prefix(CharDriverState *chr)
186{
6e92466a 187 qemu_timeval tv;
c7f0f3b1
AL
188
189 if (!qtest_log_fp || !qtest_opened) {
190 return;
191 }
192
193 qtest_get_time(&tv);
194 fprintf(qtest_log_fp, "[S +" FMT_timeval "] ",
35aa3fb3 195 (long) tv.tv_sec, (long) tv.tv_usec);
c7f0f3b1
AL
196}
197
7a6a740d
JS
198static void GCC_FMT_ATTR(1, 2) qtest_log_send(const char *fmt, ...)
199{
200 va_list ap;
201
202 if (!qtest_log_fp || !qtest_opened) {
203 return;
204 }
205
206 qtest_send_prefix(NULL);
207
208 va_start(ap, fmt);
209 vfprintf(qtest_log_fp, fmt, ap);
210 va_end(ap);
211}
212
332cc7e9
JS
213static void do_qtest_send(CharDriverState *chr, const char *str, size_t len)
214{
215 qemu_chr_fe_write_all(chr, (uint8_t *)str, len);
216 if (qtest_log_fp && qtest_opened) {
217 fprintf(qtest_log_fp, "%s", str);
218 }
219}
220
221static void qtest_send(CharDriverState *chr, const char *str)
222{
223 do_qtest_send(chr, str, strlen(str));
224}
225
226static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharDriverState *chr,
227 const char *fmt, ...)
c7f0f3b1
AL
228{
229 va_list ap;
332cc7e9 230 gchar *buffer;
c7f0f3b1
AL
231
232 va_start(ap, fmt);
332cc7e9
JS
233 buffer = g_strdup_vprintf(fmt, ap);
234 qtest_send(chr, buffer);
c7f0f3b1 235 va_end(ap);
c7f0f3b1
AL
236}
237
20288345
PB
238static void qtest_irq_handler(void *opaque, int n, int level)
239{
60a79016
PC
240 qemu_irq old_irq = *(qemu_irq *)opaque;
241 qemu_set_irq(old_irq, level);
20288345
PB
242
243 if (irq_levels[n] != level) {
244 CharDriverState *chr = qtest_chr;
245 irq_levels[n] = level;
246 qtest_send_prefix(chr);
332cc7e9
JS
247 qtest_sendf(chr, "IRQ %s %d\n",
248 level ? "raise" : "lower", n);
20288345
PB
249 }
250}
251
c7f0f3b1
AL
252static void qtest_process_command(CharDriverState *chr, gchar **words)
253{
254 const gchar *command;
255
256 g_assert(words);
257
258 command = words[0];
259
260 if (qtest_log_fp) {
6e92466a 261 qemu_timeval tv;
c7f0f3b1
AL
262 int i;
263
264 qtest_get_time(&tv);
265 fprintf(qtest_log_fp, "[R +" FMT_timeval "]",
35aa3fb3 266 (long) tv.tv_sec, (long) tv.tv_usec);
c7f0f3b1
AL
267 for (i = 0; words[i]; i++) {
268 fprintf(qtest_log_fp, " %s", words[i]);
269 }
270 fprintf(qtest_log_fp, "\n");
271 }
272
273 g_assert(command);
20288345
PB
274 if (strcmp(words[0], "irq_intercept_out") == 0
275 || strcmp(words[0], "irq_intercept_in") == 0) {
a5f54290
PC
276 DeviceState *dev;
277 NamedGPIOList *ngl;
20288345
PB
278
279 g_assert(words[1]);
280 dev = DEVICE(object_resolve_path(words[1], NULL));
281 if (!dev) {
282 qtest_send_prefix(chr);
283 qtest_send(chr, "FAIL Unknown device\n");
284 return;
285 }
286
287 if (irq_intercept_dev) {
288 qtest_send_prefix(chr);
289 if (irq_intercept_dev != dev) {
290 qtest_send(chr, "FAIL IRQ intercept already enabled\n");
291 } else {
292 qtest_send(chr, "OK\n");
293 }
294 return;
295 }
296
a5f54290
PC
297 QLIST_FOREACH(ngl, &dev->gpios, node) {
298 /* We don't support intercept of named GPIOs yet */
299 if (ngl->name) {
300 continue;
301 }
302 if (words[0][14] == 'o') {
60a79016
PC
303 int i;
304 for (i = 0; i < ngl->num_out; ++i) {
305 qemu_irq *disconnected = g_new0(qemu_irq, 1);
306 qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler,
307 disconnected, i);
308
309 *disconnected = qdev_intercept_gpio_out(dev, icpt,
310 ngl->name, i);
311 }
a5f54290
PC
312 } else {
313 qemu_irq_intercept_in(ngl->in, qtest_irq_handler,
314 ngl->num_in);
315 }
20288345
PB
316 }
317 irq_intercept_dev = dev;
318 qtest_send_prefix(chr);
319 qtest_send(chr, "OK\n");
320
321 } else if (strcmp(words[0], "outb") == 0 ||
322 strcmp(words[0], "outw") == 0 ||
323 strcmp(words[0], "outl") == 0) {
c7f0f3b1
AL
324 uint16_t addr;
325 uint32_t value;
326
327 g_assert(words[1] && words[2]);
56863d4f
PM
328 addr = strtoul(words[1], NULL, 0);
329 value = strtoul(words[2], NULL, 0);
c7f0f3b1
AL
330
331 if (words[0][3] == 'b') {
332 cpu_outb(addr, value);
333 } else if (words[0][3] == 'w') {
334 cpu_outw(addr, value);
335 } else if (words[0][3] == 'l') {
336 cpu_outl(addr, value);
337 }
338 qtest_send_prefix(chr);
339 qtest_send(chr, "OK\n");
340 } else if (strcmp(words[0], "inb") == 0 ||
341 strcmp(words[0], "inw") == 0 ||
342 strcmp(words[0], "inl") == 0) {
343 uint16_t addr;
344 uint32_t value = -1U;
345
346 g_assert(words[1]);
56863d4f 347 addr = strtoul(words[1], NULL, 0);
c7f0f3b1
AL
348
349 if (words[0][2] == 'b') {
350 value = cpu_inb(addr);
351 } else if (words[0][2] == 'w') {
352 value = cpu_inw(addr);
353 } else if (words[0][2] == 'l') {
354 value = cpu_inl(addr);
355 }
356 qtest_send_prefix(chr);
332cc7e9 357 qtest_sendf(chr, "OK 0x%04x\n", value);
872536bf
AF
358 } else if (strcmp(words[0], "writeb") == 0 ||
359 strcmp(words[0], "writew") == 0 ||
360 strcmp(words[0], "writel") == 0 ||
361 strcmp(words[0], "writeq") == 0) {
362 uint64_t addr;
363 uint64_t value;
364
365 g_assert(words[1] && words[2]);
366 addr = strtoull(words[1], NULL, 0);
367 value = strtoull(words[2], NULL, 0);
368
369 if (words[0][5] == 'b') {
370 uint8_t data = value;
371 cpu_physical_memory_write(addr, &data, 1);
372 } else if (words[0][5] == 'w') {
373 uint16_t data = value;
374 tswap16s(&data);
375 cpu_physical_memory_write(addr, &data, 2);
376 } else if (words[0][5] == 'l') {
377 uint32_t data = value;
378 tswap32s(&data);
379 cpu_physical_memory_write(addr, &data, 4);
380 } else if (words[0][5] == 'q') {
381 uint64_t data = value;
382 tswap64s(&data);
383 cpu_physical_memory_write(addr, &data, 8);
384 }
385 qtest_send_prefix(chr);
386 qtest_send(chr, "OK\n");
387 } else if (strcmp(words[0], "readb") == 0 ||
388 strcmp(words[0], "readw") == 0 ||
389 strcmp(words[0], "readl") == 0 ||
390 strcmp(words[0], "readq") == 0) {
391 uint64_t addr;
392 uint64_t value = UINT64_C(-1);
393
394 g_assert(words[1]);
395 addr = strtoull(words[1], NULL, 0);
396
397 if (words[0][4] == 'b') {
398 uint8_t data;
399 cpu_physical_memory_read(addr, &data, 1);
400 value = data;
401 } else if (words[0][4] == 'w') {
402 uint16_t data;
403 cpu_physical_memory_read(addr, &data, 2);
404 value = tswap16(data);
405 } else if (words[0][4] == 'l') {
406 uint32_t data;
407 cpu_physical_memory_read(addr, &data, 4);
408 value = tswap32(data);
409 } else if (words[0][4] == 'q') {
410 cpu_physical_memory_read(addr, &value, 8);
411 tswap64s(&value);
412 }
413 qtest_send_prefix(chr);
332cc7e9 414 qtest_sendf(chr, "OK 0x%016" PRIx64 "\n", value);
c7f0f3b1
AL
415 } else if (strcmp(words[0], "read") == 0) {
416 uint64_t addr, len, i;
417 uint8_t *data;
5560b85a 418 char *enc;
c7f0f3b1
AL
419
420 g_assert(words[1] && words[2]);
5dd6be06
AF
421 addr = strtoull(words[1], NULL, 0);
422 len = strtoull(words[2], NULL, 0);
c7f0f3b1
AL
423
424 data = g_malloc(len);
425 cpu_physical_memory_read(addr, data, len);
426
5560b85a 427 enc = g_malloc(2 * len + 1);
c7f0f3b1 428 for (i = 0; i < len; i++) {
5560b85a 429 sprintf(&enc[i * 2], "%02x", data[i]);
c7f0f3b1 430 }
5560b85a
JS
431
432 qtest_send_prefix(chr);
433 qtest_sendf(chr, "OK 0x%s\n", enc);
c7f0f3b1
AL
434
435 g_free(data);
5560b85a 436 g_free(enc);
7a6a740d
JS
437 } else if (strcmp(words[0], "b64read") == 0) {
438 uint64_t addr, len;
439 uint8_t *data;
440 gchar *b64_data;
441
442 g_assert(words[1] && words[2]);
443 addr = strtoull(words[1], NULL, 0);
444 len = strtoull(words[2], NULL, 0);
445
446 data = g_malloc(len);
447 cpu_physical_memory_read(addr, data, len);
448 b64_data = g_base64_encode(data, len);
449 qtest_send_prefix(chr);
450 qtest_sendf(chr, "OK %s\n", b64_data);
451
452 g_free(data);
453 g_free(b64_data);
c7f0f3b1
AL
454 } else if (strcmp(words[0], "write") == 0) {
455 uint64_t addr, len, i;
456 uint8_t *data;
457 size_t data_len;
458
459 g_assert(words[1] && words[2] && words[3]);
5dd6be06
AF
460 addr = strtoull(words[1], NULL, 0);
461 len = strtoull(words[2], NULL, 0);
c7f0f3b1
AL
462
463 data_len = strlen(words[3]);
464 if (data_len < 3) {
465 qtest_send(chr, "ERR invalid argument size\n");
466 return;
467 }
468
469 data = g_malloc(len);
470 for (i = 0; i < len; i++) {
471 if ((i * 2 + 4) <= data_len) {
472 data[i] = hex2nib(words[3][i * 2 + 2]) << 4;
473 data[i] |= hex2nib(words[3][i * 2 + 3]);
474 } else {
475 data[i] = 0;
476 }
477 }
478 cpu_physical_memory_write(addr, data, len);
479 g_free(data);
480
4d007963
JS
481 qtest_send_prefix(chr);
482 qtest_send(chr, "OK\n");
483 } else if (strcmp(words[0], "memset") == 0) {
484 uint64_t addr, len;
485 uint8_t *data;
486 uint8_t pattern;
487
488 g_assert(words[1] && words[2] && words[3]);
489 addr = strtoull(words[1], NULL, 0);
490 len = strtoull(words[2], NULL, 0);
491 pattern = strtoull(words[3], NULL, 0);
492
493 data = g_malloc(len);
494 memset(data, pattern, len);
495 cpu_physical_memory_write(addr, data, len);
496 g_free(data);
497
7a6a740d
JS
498 qtest_send_prefix(chr);
499 qtest_send(chr, "OK\n");
500 } else if (strcmp(words[0], "b64write") == 0) {
501 uint64_t addr, len;
502 uint8_t *data;
503 size_t data_len;
504 gsize out_len;
505
506 g_assert(words[1] && words[2] && words[3]);
507 addr = strtoull(words[1], NULL, 0);
508 len = strtoull(words[2], NULL, 0);
509
510 data_len = strlen(words[3]);
511 if (data_len < 3) {
512 qtest_send(chr, "ERR invalid argument size\n");
513 return;
514 }
515
516 data = g_base64_decode_inplace(words[3], &out_len);
517 if (out_len != len) {
518 qtest_log_send("b64write: data length mismatch (told %"PRIu64", "
519 "found %zu)\n",
520 len, out_len);
521 out_len = MIN(out_len, len);
522 }
523
524 cpu_physical_memory_write(addr, data, out_len);
525
c7f0f3b1
AL
526 qtest_send_prefix(chr);
527 qtest_send(chr, "OK\n");
d4fce24f 528 } else if (qtest_enabled() && strcmp(words[0], "clock_step") == 0) {
8156be56
PB
529 int64_t ns;
530
531 if (words[1]) {
532 ns = strtoll(words[1], NULL, 0);
533 } else {
40daca54 534 ns = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);
8156be56 535 }
bc72ad67 536 qtest_clock_warp(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns);
8156be56 537 qtest_send_prefix(chr);
332cc7e9
JS
538 qtest_sendf(chr, "OK %"PRIi64"\n",
539 (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
d4fce24f 540 } else if (qtest_enabled() && strcmp(words[0], "clock_set") == 0) {
8156be56
PB
541 int64_t ns;
542
543 g_assert(words[1]);
544 ns = strtoll(words[1], NULL, 0);
545 qtest_clock_warp(ns);
546 qtest_send_prefix(chr);
332cc7e9
JS
547 qtest_sendf(chr, "OK %"PRIi64"\n",
548 (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
c7f0f3b1
AL
549 } else {
550 qtest_send_prefix(chr);
332cc7e9 551 qtest_sendf(chr, "FAIL Unknown command '%s'\n", words[0]);
c7f0f3b1
AL
552 }
553}
554
555static void qtest_process_inbuf(CharDriverState *chr, GString *inbuf)
556{
557 char *end;
558
559 while ((end = strchr(inbuf->str, '\n')) != NULL) {
560 size_t offset;
561 GString *cmd;
562 gchar **words;
563
564 offset = end - inbuf->str;
565
566 cmd = g_string_new_len(inbuf->str, offset);
567 g_string_erase(inbuf, 0, offset + 1);
568
569 words = g_strsplit(cmd->str, " ", 0);
570 qtest_process_command(chr, words);
571 g_strfreev(words);
572
573 g_string_free(cmd, TRUE);
574 }
575}
576
577static void qtest_read(void *opaque, const uint8_t *buf, int size)
578{
579 CharDriverState *chr = opaque;
580
581 g_string_append_len(inbuf, (const gchar *)buf, size);
582 qtest_process_inbuf(chr, inbuf);
583}
584
585static int qtest_can_read(void *opaque)
586{
587 return 1024;
588}
589
590static void qtest_event(void *opaque, int event)
591{
592 int i;
593
594 switch (event) {
595 case CHR_EVENT_OPENED:
ba646ff6
MA
596 /*
597 * We used to call qemu_system_reset() here, hoping we could
598 * use the same process for multiple tests that way. Never
599 * used. Injects an extra reset even when it's not used, and
600 * that can mess up tests, e.g. -boot once.
601 */
c7f0f3b1
AL
602 for (i = 0; i < ARRAY_SIZE(irq_levels); i++) {
603 irq_levels[i] = 0;
604 }
6e92466a 605 qemu_gettimeofday(&start_time);
c7f0f3b1
AL
606 qtest_opened = true;
607 if (qtest_log_fp) {
608 fprintf(qtest_log_fp, "[I " FMT_timeval "] OPENED\n",
35aa3fb3 609 (long) start_time.tv_sec, (long) start_time.tv_usec);
c7f0f3b1
AL
610 }
611 break;
612 case CHR_EVENT_CLOSED:
613 qtest_opened = false;
614 if (qtest_log_fp) {
6e92466a 615 qemu_timeval tv;
c7f0f3b1
AL
616 qtest_get_time(&tv);
617 fprintf(qtest_log_fp, "[I +" FMT_timeval "] CLOSED\n",
35aa3fb3 618 (long) tv.tv_sec, (long) tv.tv_usec);
c7f0f3b1
AL
619 }
620 break;
621 default:
622 break;
623 }
624}
625
b3adf5ac 626static int qtest_init_accel(MachineState *ms)
c7f0f3b1 627{
b3adf5ac
MA
628 QemuOpts *opts = qemu_opts_create(qemu_find_opts("icount"), NULL, 0,
629 &error_abort);
630 qemu_opt_set(opts, "shift", "0", &error_abort);
1ad9580b
ST
631 configure_icount(opts, &error_abort);
632 qemu_opts_del(opts);
d4fce24f
PB
633 return 0;
634}
635
23802b4f 636void qtest_init(const char *qtest_chrdev, const char *qtest_log, Error **errp)
d4fce24f
PB
637{
638 CharDriverState *chr;
c7f0f3b1
AL
639
640 chr = qemu_chr_new("qtest", qtest_chrdev, NULL);
641
23802b4f
FZ
642 if (chr == NULL) {
643 error_setg(errp, "Failed to initialize device for qtest: \"%s\"",
644 qtest_chrdev);
645 return;
646 }
647
c7f0f3b1
AL
648 if (qtest_log) {
649 if (strcmp(qtest_log, "none") != 0) {
650 qtest_log_fp = fopen(qtest_log, "w+");
651 }
652 } else {
653 qtest_log_fp = stderr;
654 }
655
107684c0
LL
656 qemu_chr_add_handlers(chr, qtest_can_read, qtest_read, qtest_event, chr);
657 qemu_chr_fe_set_echo(chr, true);
658
659 inbuf = g_string_new("");
c7f0f3b1 660 qtest_chr = chr;
c7f0f3b1 661}
b3be57c3
MT
662
663bool qtest_driver(void)
664{
665 return qtest_chr;
666}
3a6ce514
EH
667
668static void qtest_accel_class_init(ObjectClass *oc, void *data)
669{
670 AccelClass *ac = ACCEL_CLASS(oc);
671 ac->name = "QTest";
672 ac->available = qtest_available;
0d15da8e 673 ac->init_machine = qtest_init_accel;
3a6ce514
EH
674 ac->allowed = &qtest_allowed;
675}
676
677#define TYPE_QTEST_ACCEL ACCEL_CLASS_NAME("qtest")
678
679static const TypeInfo qtest_accel_type = {
680 .name = TYPE_QTEST_ACCEL,
681 .parent = TYPE_ACCEL,
682 .class_init = qtest_accel_class_init,
683};
684
685static void qtest_type_init(void)
686{
687 type_register_static(&qtest_accel_type);
688}
689
690type_init(qtest_type_init);