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1/*
2 * Software MMU support
5fafdf24 3 *
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4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#define DATA_SIZE (1 << SHIFT)
21
22#if DATA_SIZE == 8
23#define SUFFIX q
61382a50 24#define USUFFIX q
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25#define DATA_TYPE uint64_t
26#elif DATA_SIZE == 4
27#define SUFFIX l
61382a50 28#define USUFFIX l
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29#define DATA_TYPE uint32_t
30#elif DATA_SIZE == 2
31#define SUFFIX w
61382a50 32#define USUFFIX uw
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33#define DATA_TYPE uint16_t
34#elif DATA_SIZE == 1
35#define SUFFIX b
61382a50 36#define USUFFIX ub
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37#define DATA_TYPE uint8_t
38#else
39#error unsupported data size
40#endif
41
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42#ifdef SOFTMMU_CODE_ACCESS
43#define READ_ACCESS_TYPE 2
84b7b8e7 44#define ADDR_READ addr_code
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45#else
46#define READ_ACCESS_TYPE 0
84b7b8e7 47#define ADDR_READ addr_read
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48#endif
49
5fafdf24 50static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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51 int is_user,
52 void *retaddr);
5fafdf24 53static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
c27004ec 54 target_ulong tlb_addr)
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55{
56 DATA_TYPE res;
57 int index;
58
59 index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
60#if SHIFT <= 2
a4193c8a 61 res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
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62#else
63#ifdef TARGET_WORDS_BIGENDIAN
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64 res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
65 res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
b92e5a22 66#else
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67 res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
68 res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
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69#endif
70#endif /* SHIFT > 2 */
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71#ifdef USE_KQEMU
72 env->last_io_time = cpu_get_time_fast();
73#endif
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74 return res;
75}
76
b92e5a22 77/* handle all cases except unaligned access which span two pages */
c27004ec 78DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50 79 int is_user)
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80{
81 DATA_TYPE res;
61382a50 82 int index;
c27004ec 83 target_ulong tlb_addr;
108c49b8 84 target_phys_addr_t physaddr;
b92e5a22 85 void *retaddr;
3b46e624 86
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87 /* test if there is match for unaligned or IO access */
88 /* XXX: could done more in memory macro in a non portable way */
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89 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
90 redo:
84b7b8e7 91 tlb_addr = env->tlb_table[is_user][index].ADDR_READ;
b92e5a22 92 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
84b7b8e7 93 physaddr = addr + env->tlb_table[is_user][index].addend;
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94 if (tlb_addr & ~TARGET_PAGE_MASK) {
95 /* IO access */
96 if ((addr & (DATA_SIZE - 1)) != 0)
97 goto do_unaligned_access;
98 res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
98699967 99 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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100 /* slow unaligned access (it spans two pages or IO) */
101 do_unaligned_access:
61382a50 102 retaddr = GETPC();
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103#ifdef ALIGNED_ONLY
104 do_unaligned_access(addr, READ_ACCESS_TYPE, is_user, retaddr);
105#endif
5fafdf24 106 res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
61382a50 107 is_user, retaddr);
b92e5a22 108 } else {
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109 /* unaligned/aligned access in the same page */
110#ifdef ALIGNED_ONLY
111 if ((addr & (DATA_SIZE - 1)) != 0) {
112 retaddr = GETPC();
113 do_unaligned_access(addr, READ_ACCESS_TYPE, is_user, retaddr);
114 }
115#endif
108c49b8 116 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
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117 }
118 } else {
119 /* the page is not in the TLB : fill it */
61382a50 120 retaddr = GETPC();
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121#ifdef ALIGNED_ONLY
122 if ((addr & (DATA_SIZE - 1)) != 0)
123 do_unaligned_access(addr, READ_ACCESS_TYPE, is_user, retaddr);
124#endif
b769d8fe 125 tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr);
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126 goto redo;
127 }
128 return res;
129}
130
131/* handle all unaligned cases */
5fafdf24 132static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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133 int is_user,
134 void *retaddr)
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135{
136 DATA_TYPE res, res1, res2;
61382a50 137 int index, shift;
108c49b8 138 target_phys_addr_t physaddr;
c27004ec 139 target_ulong tlb_addr, addr1, addr2;
b92e5a22 140
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141 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
142 redo:
84b7b8e7 143 tlb_addr = env->tlb_table[is_user][index].ADDR_READ;
b92e5a22 144 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
84b7b8e7 145 physaddr = addr + env->tlb_table[is_user][index].addend;
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146 if (tlb_addr & ~TARGET_PAGE_MASK) {
147 /* IO access */
148 if ((addr & (DATA_SIZE - 1)) != 0)
149 goto do_unaligned_access;
150 res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
98699967 151 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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152 do_unaligned_access:
153 /* slow unaligned access (it spans two pages) */
154 addr1 = addr & ~(DATA_SIZE - 1);
155 addr2 = addr1 + DATA_SIZE;
5fafdf24 156 res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
61382a50 157 is_user, retaddr);
5fafdf24 158 res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
61382a50 159 is_user, retaddr);
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160 shift = (addr & (DATA_SIZE - 1)) * 8;
161#ifdef TARGET_WORDS_BIGENDIAN
162 res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
163#else
164 res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
165#endif
6986f88c 166 res = (DATA_TYPE)res;
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167 } else {
168 /* unaligned/aligned access in the same page */
108c49b8 169 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
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170 }
171 } else {
172 /* the page is not in the TLB : fill it */
b769d8fe 173 tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr);
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174 goto redo;
175 }
176 return res;
177}
178
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179#ifndef SOFTMMU_CODE_ACCESS
180
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181static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
182 DATA_TYPE val,
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183 int is_user,
184 void *retaddr);
185
5fafdf24 186static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
b769d8fe 187 DATA_TYPE val,
c27004ec 188 target_ulong tlb_addr,
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189 void *retaddr)
190{
191 int index;
192
193 index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
194 env->mem_write_vaddr = tlb_addr;
195 env->mem_write_pc = (unsigned long)retaddr;
196#if SHIFT <= 2
197 io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
198#else
199#ifdef TARGET_WORDS_BIGENDIAN
200 io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
201 io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
202#else
203 io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
204 io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
205#endif
206#endif /* SHIFT > 2 */
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207#ifdef USE_KQEMU
208 env->last_io_time = cpu_get_time_fast();
209#endif
b769d8fe 210}
b92e5a22 211
5fafdf24 212void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
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213 DATA_TYPE val,
214 int is_user)
b92e5a22 215{
108c49b8 216 target_phys_addr_t physaddr;
c27004ec 217 target_ulong tlb_addr;
b92e5a22 218 void *retaddr;
61382a50 219 int index;
3b46e624 220
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221 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
222 redo:
84b7b8e7 223 tlb_addr = env->tlb_table[is_user][index].addr_write;
b92e5a22 224 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
84b7b8e7 225 physaddr = addr + env->tlb_table[is_user][index].addend;
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226 if (tlb_addr & ~TARGET_PAGE_MASK) {
227 /* IO access */
228 if ((addr & (DATA_SIZE - 1)) != 0)
229 goto do_unaligned_access;
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230 retaddr = GETPC();
231 glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
98699967 232 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 233 do_unaligned_access:
61382a50 234 retaddr = GETPC();
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235#ifdef ALIGNED_ONLY
236 do_unaligned_access(addr, 1, is_user, retaddr);
237#endif
5fafdf24 238 glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
61382a50 239 is_user, retaddr);
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240 } else {
241 /* aligned/unaligned access in the same page */
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242#ifdef ALIGNED_ONLY
243 if ((addr & (DATA_SIZE - 1)) != 0) {
244 retaddr = GETPC();
245 do_unaligned_access(addr, 1, is_user, retaddr);
246 }
247#endif
108c49b8 248 glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
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249 }
250 } else {
251 /* the page is not in the TLB : fill it */
61382a50 252 retaddr = GETPC();
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253#ifdef ALIGNED_ONLY
254 if ((addr & (DATA_SIZE - 1)) != 0)
255 do_unaligned_access(addr, 1, is_user, retaddr);
256#endif
61382a50 257 tlb_fill(addr, 1, is_user, retaddr);
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258 goto redo;
259 }
260}
261
262/* handles all unaligned cases */
5fafdf24 263static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
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264 DATA_TYPE val,
265 int is_user,
266 void *retaddr)
b92e5a22 267{
108c49b8 268 target_phys_addr_t physaddr;
c27004ec 269 target_ulong tlb_addr;
61382a50 270 int index, i;
b92e5a22 271
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272 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
273 redo:
84b7b8e7 274 tlb_addr = env->tlb_table[is_user][index].addr_write;
b92e5a22 275 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
84b7b8e7 276 physaddr = addr + env->tlb_table[is_user][index].addend;
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277 if (tlb_addr & ~TARGET_PAGE_MASK) {
278 /* IO access */
279 if ((addr & (DATA_SIZE - 1)) != 0)
280 goto do_unaligned_access;
d720b93d 281 glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
98699967 282 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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283 do_unaligned_access:
284 /* XXX: not efficient, but simple */
285 for(i = 0;i < DATA_SIZE; i++) {
286#ifdef TARGET_WORDS_BIGENDIAN
5fafdf24 287 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
61382a50 288 is_user, retaddr);
b92e5a22 289#else
5fafdf24 290 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
61382a50 291 is_user, retaddr);
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292#endif
293 }
294 } else {
295 /* aligned/unaligned access in the same page */
108c49b8 296 glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
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297 }
298 } else {
299 /* the page is not in the TLB : fill it */
61382a50 300 tlb_fill(addr, 1, is_user, retaddr);
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301 goto redo;
302 }
303}
304
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305#endif /* !defined(SOFTMMU_CODE_ACCESS) */
306
307#undef READ_ACCESS_TYPE
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308#undef SHIFT
309#undef DATA_TYPE
310#undef SUFFIX
61382a50 311#undef USUFFIX
b92e5a22 312#undef DATA_SIZE
84b7b8e7 313#undef ADDR_READ