[mirror_qemu.git] / target-arm / cpu.h

/*
 * ARM virtual CPU header
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#ifndef CPU_ARM_H
#define CPU_ARM_H

#define TARGET_LONG_BITS 32

#define ELF_MACHINE	EM_ARM

#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_HAS_ICE 1

#define EXCP_UDEF            1   /* undefined instruction */
#define EXCP_SWI             2   /* software interrupt */
#define EXCP_PREFETCH_ABORT  3
#define EXCP_DATA_ABORT      4
#define EXCP_IRQ             5
#define EXCP_FIQ             6
#define EXCP_BKPT            7
#define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */

#define ARMV7M_EXCP_RESET   1
#define ARMV7M_EXCP_NMI     2
#define ARMV7M_EXCP_HARD    3
#define ARMV7M_EXCP_MEM     4
#define ARMV7M_EXCP_BUS     5
#define ARMV7M_EXCP_USAGE   6
#define ARMV7M_EXCP_SVC     11
#define ARMV7M_EXCP_DEBUG   12
#define ARMV7M_EXCP_PENDSV  14
#define ARMV7M_EXCP_SYSTICK 15

typedef void ARMWriteCPFunc(void *opaque, int cp_info,
                            int srcreg, int operand, uint32_t value);
typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
                               int dstreg, int operand);

#define NB_MMU_MODES 2

/* We currently assume float and double are IEEE single and double
   precision respectively.
   Doing runtime conversions is tricky because VFP registers may contain
   integer values (eg. as the result of a FTOSI instruction).
   s<2n> maps to the least significant half of d<n>
   s<2n+1> maps to the most significant half of d<n>
 */

typedef struct CPUARMState {
    /* Regs for current mode.  */
    uint32_t regs[16];
    /* Frequently accessed CPSR bits are stored separately for efficiently.
       This contains all the other bits.  Use cpsr_{read,write} to access
       the whole CPSR.  */
    uint32_t uncached_cpsr;
    uint32_t spsr;

    /* Banked registers.  */
    uint32_t banked_spsr[6];
    uint32_t banked_r13[6];
    uint32_t banked_r14[6];

    /* These hold r8-r12.  */
    uint32_t usr_regs[5];
    uint32_t fiq_regs[5];

    /* cpsr flag cache for faster execution */
    uint32_t CF; /* 0 or 1 */
    uint32_t VF; /* V is the bit 31. All other bits are undefined */
    uint32_t NZF; /* N is bit 31. Z is computed from NZF */
    uint32_t QF; /* 0 or 1 */
    uint32_t GE; /* cpsr[19:16] */
    int thumb; /* cprs[5]. 0 = arm mode, 1 = thumb mode. */
    uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */

    /* System control coprocessor (cp15) */
    struct {
        uint32_t c0_cpuid;
        uint32_t c0_cachetype;
        uint32_t c0_c1[8]; /* Feature registers.  */
        uint32_t c0_c2[8]; /* Instruction set registers.  */
        uint32_t c1_sys; /* System control register.  */
        uint32_t c1_coproc; /* Coprocessor access register.  */
        uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
        uint32_t c2_base0; /* MMU translation table base 0.  */
        uint32_t c2_base1; /* MMU translation table base 1.  */
        uint32_t c2_mask; /* MMU translation table base mask.  */
        uint32_t c2_data; /* MPU data cachable bits.  */
        uint32_t c2_insn; /* MPU instruction cachable bits.  */
        uint32_t c3; /* MMU domain access control register
                        MPU write buffer control.  */
        uint32_t c5_insn; /* Fault status registers.  */
        uint32_t c5_data;
        uint32_t c6_region[8]; /* MPU base/size registers.  */
        uint32_t c6_insn; /* Fault address registers.  */
        uint32_t c6_data;
        uint32_t c9_insn; /* Cache lockdown registers.  */
        uint32_t c9_data;
        uint32_t c13_fcse; /* FCSE PID.  */
        uint32_t c13_context; /* Context ID.  */
        uint32_t c13_tls1; /* User RW Thread register.  */
        uint32_t c13_tls2; /* User RO Thread register.  */
        uint32_t c13_tls3; /* Privileged Thread register.  */
        uint32_t c15_cpar; /* XScale Coprocessor Access Register */
        uint32_t c15_ticonfig; /* TI925T configuration byte.  */
        uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
        uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
        uint32_t c15_threadid; /* TI debugger thread-ID.  */
    } cp15;

    struct {
        uint32_t other_sp;
        uint32_t vecbase;
        uint32_t basepri;
        uint32_t control;
        int current_sp;
        int exception;
        int pending_exception;
        void *nvic;
    } v7m;

    /* Coprocessor IO used by peripherals */
    struct {
        ARMReadCPFunc *cp_read;
        ARMWriteCPFunc *cp_write;
        void *opaque;
    } cp[15];

    /* Internal CPU feature flags.  */
    uint32_t features;

    /* Callback for vectored interrupt controller.  */
    int (*get_irq_vector)(struct CPUARMState *);
    void *irq_opaque;

    /* exception/interrupt handling */
    jmp_buf jmp_env;
    int exception_index;
    int interrupt_request;
    int user_mode_only;
    int halted;

    /* VFP coprocessor state.  */
    struct {
        float64 regs[32];

        uint32_t xregs[16];
        /* We store these fpcsr fields separately for convenience.  */
        int vec_len;
        int vec_stride;

        /* Temporary variables if we don't have spare fp regs.  */
        float32 tmp0s, tmp1s;
        float64 tmp0d, tmp1d;
        /* scratch space when Tn are not sufficient.  */
        uint32_t scratch[8];

        float_status fp_status;
    } vfp;
#if defined(CONFIG_USER_ONLY)
    struct mmon_state *mmon_entry;
#else
    uint32_t mmon_addr;
#endif

    /* iwMMXt coprocessor state.  */
    struct {
        uint64_t regs[16];
        uint64_t val;

        uint32_t cregs[16];
    } iwmmxt;

#if defined(CONFIG_USER_ONLY)
    /* For usermode syscall translation.  */
    int eabi;
#endif

    CPU_COMMON

    /* These fields after the common ones so they are preserved on reset.  */
    int ram_size;
    const char *kernel_filename;
    const char *kernel_cmdline;
    const char *initrd_filename;
    int board_id;
    target_phys_addr_t loader_start;
} CPUARMState;

CPUARMState *cpu_arm_init(const char *cpu_model);
int cpu_arm_exec(CPUARMState *s);
void cpu_arm_close(CPUARMState *s);
void do_interrupt(CPUARMState *);
void switch_mode(CPUARMState *, int);
uint32_t do_arm_semihosting(CPUARMState *env);

/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
int cpu_arm_signal_handler(int host_signum, void *pinfo,
                           void *puc);

void cpu_lock(void);
void cpu_unlock(void);

#define CPSR_M (0x1f)
#define CPSR_T (1 << 5)
#define CPSR_F (1 << 6)
#define CPSR_I (1 << 7)
#define CPSR_A (1 << 8)
#define CPSR_E (1 << 9)
#define CPSR_IT_2_7 (0xfc00)
#define CPSR_GE (0xf << 16)
#define CPSR_RESERVED (0xf << 20)
#define CPSR_J (1 << 24)
#define CPSR_IT_0_1 (3 << 25)
#define CPSR_Q (1 << 27)
#define CPSR_V (1 << 28)
#define CPSR_C (1 << 29)
#define CPSR_Z (1 << 30)
#define CPSR_N (1 << 31)
#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)

#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
#define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
/* Bits writable in user mode.  */
#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
/* Execution state bits.  MRS read as zero, MSR writes ignored.  */
#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)

/* Return the current CPSR value.  */
static inline uint32_t cpsr_read(CPUARMState *env)
{
    int ZF;
    ZF = (env->NZF == 0);
    return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
        (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
        | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
        | ((env->condexec_bits & 0xfc) << 8)
        | (env->GE << 16);
}

/* Return the current xPSR value.  */
static inline uint32_t xpsr_read(CPUARMState *env)
{
    int ZF;
    ZF = (env->NZF == 0);
    return (env->NZF & 0x80000000) | (ZF << 30)
        | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
        | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
        | ((env->condexec_bits & 0xfc) << 8)
        | env->v7m.exception;
}

/* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
static inline void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
{
    /* NOTE: N = 1 and Z = 1 cannot be stored currently */
    if (mask & CPSR_NZCV) {
        env->NZF = (val & 0xc0000000) ^ 0x40000000;
        env->CF = (val >> 29) & 1;
        env->VF = (val << 3) & 0x80000000;
    }
    if (mask & CPSR_Q)
        env->QF = ((val & CPSR_Q) != 0);
    if (mask & CPSR_T)
        env->thumb = ((val & CPSR_T) != 0);
    if (mask & CPSR_IT_0_1) {
        env->condexec_bits &= ~3;
        env->condexec_bits |= (val >> 25) & 3;
    }
    if (mask & CPSR_IT_2_7) {
        env->condexec_bits &= 3;
        env->condexec_bits |= (val >> 8) & 0xfc;
    }
    if (mask & CPSR_GE) {
        env->GE = (val >> 16) & 0xf;
    }

    if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
        switch_mode(env, val & CPSR_M);
    }
    mask &= ~CACHED_CPSR_BITS;
    env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
}

/* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
{
    /* NOTE: N = 1 and Z = 1 cannot be stored currently */
    if (mask & CPSR_NZCV) {
        env->NZF = (val & 0xc0000000) ^ 0x40000000;
        env->CF = (val >> 29) & 1;
        env->VF = (val << 3) & 0x80000000;
    }
    if (mask & CPSR_Q)
        env->QF = ((val & CPSR_Q) != 0);
    if (mask & (1 << 24))
        env->thumb = ((val & (1 << 24)) != 0);
    if (mask & CPSR_IT_0_1) {
        env->condexec_bits &= ~3;
        env->condexec_bits |= (val >> 25) & 3;
    }
    if (mask & CPSR_IT_2_7) {
        env->condexec_bits &= 3;
        env->condexec_bits |= (val >> 8) & 0xfc;
    }
    if (mask & 0x1ff) {
        env->v7m.exception = val & 0x1ff;
    }
}

enum arm_cpu_mode {
  ARM_CPU_MODE_USR = 0x10,
  ARM_CPU_MODE_FIQ = 0x11,
  ARM_CPU_MODE_IRQ = 0x12,
  ARM_CPU_MODE_SVC = 0x13,
  ARM_CPU_MODE_ABT = 0x17,
  ARM_CPU_MODE_UND = 0x1b,
  ARM_CPU_MODE_SYS = 0x1f
};

/* VFP system registers.  */
#define ARM_VFP_FPSID   0
#define ARM_VFP_FPSCR   1
#define ARM_VFP_MVFR1   6
#define ARM_VFP_MVFR0   7
#define ARM_VFP_FPEXC   8
#define ARM_VFP_FPINST  9
#define ARM_VFP_FPINST2 10

/* iwMMXt coprocessor control registers.  */
#define ARM_IWMMXT_wCID		0
#define ARM_IWMMXT_wCon		1
#define ARM_IWMMXT_wCSSF	2
#define ARM_IWMMXT_wCASF	3
#define ARM_IWMMXT_wCGR0	8
#define ARM_IWMMXT_wCGR1	9
#define ARM_IWMMXT_wCGR2	10
#define ARM_IWMMXT_wCGR3	11

enum arm_features {
    ARM_FEATURE_VFP,
    ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
    ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
    ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
    ARM_FEATURE_V6,
    ARM_FEATURE_V6K,
    ARM_FEATURE_V7,
    ARM_FEATURE_THUMB2,
    ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
    ARM_FEATURE_VFP3,
    ARM_FEATURE_NEON,
    ARM_FEATURE_DIV,
    ARM_FEATURE_M, /* Microcontroller profile.  */
    ARM_FEATURE_OMAPCP  /* OMAP specific CP15 ops handling.  */
};

static inline int arm_feature(CPUARMState *env, int feature)
{
    return (env->features & (1u << feature)) != 0;
}

void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));

/* Interface between CPU and Interrupt controller.  */
void armv7m_nvic_set_pending(void *opaque, int irq);
int armv7m_nvic_acknowledge_irq(void *opaque);
void armv7m_nvic_complete_irq(void *opaque, int irq);

void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
                       ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
                       void *opaque);

/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
   Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
   conventional cores (ie. Application or Realtime profile).  */

#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
#define ARM_CPUID(env) (env->cp15.c0_cpuid)

#define ARM_CPUID_ARM1026     0x4106a262
#define ARM_CPUID_ARM926      0x41069265
#define ARM_CPUID_ARM946      0x41059461
#define ARM_CPUID_TI915T      0x54029152
#define ARM_CPUID_TI925T      0x54029252
#define ARM_CPUID_PXA250      0x69052100
#define ARM_CPUID_PXA255      0x69052d00
#define ARM_CPUID_PXA260      0x69052903
#define ARM_CPUID_PXA261      0x69052d05
#define ARM_CPUID_PXA262      0x69052d06
#define ARM_CPUID_PXA270      0x69054110
#define ARM_CPUID_PXA270_A0   0x69054110
#define ARM_CPUID_PXA270_A1   0x69054111
#define ARM_CPUID_PXA270_B0   0x69054112
#define ARM_CPUID_PXA270_B1   0x69054113
#define ARM_CPUID_PXA270_C0   0x69054114
#define ARM_CPUID_PXA270_C5   0x69054117
#define ARM_CPUID_ARM1136     0x4117b363
#define ARM_CPUID_ARM11MPCORE 0x410fb022
#define ARM_CPUID_CORTEXA8    0x410fc080
#define ARM_CPUID_CORTEXM3    0x410fc231
#define ARM_CPUID_ANY         0xffffffff

#if defined(CONFIG_USER_ONLY)
#define TARGET_PAGE_BITS 12
#else
/* The ARM MMU allows 1k pages.  */
/* ??? Linux doesn't actually use these, and they're deprecated in recent
   architecture revisions.  Maybe a configure option to disable them.  */
#define TARGET_PAGE_BITS 10
#endif

#define CPUState CPUARMState
#define cpu_init cpu_arm_init
#define cpu_exec cpu_arm_exec
#define cpu_gen_code cpu_arm_gen_code
#define cpu_signal_handler cpu_arm_signal_handler
#define cpu_list arm_cpu_list

#define ARM_CPU_SAVE_VERSION 1

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUState *env)
{
    return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
}

#include "cpu-all.h"

#endif
Commit	Line	Data
2c0262af FB	1	/*
2c0262af FB	2	* ARM virtual CPU header
5fafdf24	3	*
2c0262af FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#ifndef CPU_ARM_H
	21	#define CPU_ARM_H
	22
3cf1e035 FB	23	#define TARGET_LONG_BITS 32
3cf1e035 FB	24
9042c0e2 TS	25	#define ELF_MACHINE EM_ARM
9042c0e2 TS	26
2c0262af FB	27	#include "cpu-defs.h"
2c0262af FB	28
53cd6637 FB	29	#include "softfloat.h"
53cd6637 FB	30
1fddef4b FB	31	#define TARGET_HAS_ICE 1
1fddef4b FB	32
b8a9e8f1 FB	33	#define EXCP_UDEF 1 /* undefined instruction */
	34	#define EXCP_SWI 2 /* software interrupt */
	35	#define EXCP_PREFETCH_ABORT 3
	36	#define EXCP_DATA_ABORT 4
b5ff1b31 FB	37	#define EXCP_IRQ 5
b5ff1b31 FB	38	#define EXCP_FIQ 6
06c949e6	39	#define EXCP_BKPT 7
9ee6e8bb PB	40	#define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
	41
	42	#define ARMV7M_EXCP_RESET 1
	43	#define ARMV7M_EXCP_NMI 2
	44	#define ARMV7M_EXCP_HARD 3
	45	#define ARMV7M_EXCP_MEM 4
	46	#define ARMV7M_EXCP_BUS 5
	47	#define ARMV7M_EXCP_USAGE 6
	48	#define ARMV7M_EXCP_SVC 11
	49	#define ARMV7M_EXCP_DEBUG 12
	50	#define ARMV7M_EXCP_PENDSV 14
	51	#define ARMV7M_EXCP_SYSTICK 15
2c0262af	52
c1713132 AZ	53	typedef void ARMWriteCPFunc(void *opaque, int cp_info,
	54	int srcreg, int operand, uint32_t value);
	55	typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
	56	int dstreg, int operand);
	57
6ebbf390 JM	58	#define NB_MMU_MODES 2
6ebbf390 JM	59
b7bcbe95 FB	60	/* We currently assume float and double are IEEE single and double
	61	precision respectively.
	62	Doing runtime conversions is tricky because VFP registers may contain
	63	integer values (eg. as the result of a FTOSI instruction).
8e96005d FB	64	s<2n> maps to the least significant half of d<n>
	65	s<2n+1> maps to the most significant half of d<n>
	66	*/
b7bcbe95	67
2c0262af	68	typedef struct CPUARMState {
b5ff1b31	69	/* Regs for current mode. */
2c0262af	70	uint32_t regs[16];
b5ff1b31	71	/* Frequently accessed CPSR bits are stored separately for efficiently.
d37aca66	72	This contains all the other bits. Use cpsr_{read,write} to access
b5ff1b31 FB	73	the whole CPSR. */
	74	uint32_t uncached_cpsr;
	75	uint32_t spsr;
	76
	77	/* Banked registers. */
	78	uint32_t banked_spsr[6];
	79	uint32_t banked_r13[6];
	80	uint32_t banked_r14[6];
3b46e624	81
b5ff1b31 FB	82	/* These hold r8-r12. */
	83	uint32_t usr_regs[5];
	84	uint32_t fiq_regs[5];
3b46e624	85
2c0262af FB	86	/* cpsr flag cache for faster execution */
	87	uint32_t CF; /* 0 or 1 */
	88	uint32_t VF; /* V is the bit 31. All other bits are undefined */
	89	uint32_t NZF; /* N is bit 31. Z is computed from NZF */
99c475ab	90	uint32_t QF; /* 0 or 1 */
9ee6e8bb PB	91	uint32_t GE; /* cpsr[19:16] */
	92	int thumb; /* cprs[5]. 0 = arm mode, 1 = thumb mode. */
	93	uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
2c0262af	94
b5ff1b31 FB	95	/* System control coprocessor (cp15) */
b5ff1b31 FB	96	struct {
40f137e1	97	uint32_t c0_cpuid;
c1713132	98	uint32_t c0_cachetype;
9ee6e8bb PB	99	uint32_t c0_c1[8]; /* Feature registers. */
9ee6e8bb PB	100	uint32_t c0_c2[8]; /* Instruction set registers. */
b5ff1b31 FB	101	uint32_t c1_sys; /* System control register. */
b5ff1b31 FB	102	uint32_t c1_coproc; /* Coprocessor access register. */
610c3c8a	103	uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
9ee6e8bb PB	104	uint32_t c2_base0; /* MMU translation table base 0. */
	105	uint32_t c2_base1; /* MMU translation table base 1. */
	106	uint32_t c2_mask; /* MMU translation table base mask. */
ce819861 PB	107	uint32_t c2_data; /* MPU data cachable bits. */
	108	uint32_t c2_insn; /* MPU instruction cachable bits. */
	109	uint32_t c3; /* MMU domain access control register
	110	MPU write buffer control. */
b5ff1b31 FB	111	uint32_t c5_insn; /* Fault status registers. */
b5ff1b31 FB	112	uint32_t c5_data;
ce819861	113	uint32_t c6_region[8]; /* MPU base/size registers. */
b5ff1b31 FB	114	uint32_t c6_insn; /* Fault address registers. */
	115	uint32_t c6_data;
	116	uint32_t c9_insn; /* Cache lockdown registers. */
	117	uint32_t c9_data;
	118	uint32_t c13_fcse; /* FCSE PID. */
	119	uint32_t c13_context; /* Context ID. */
9ee6e8bb PB	120	uint32_t c13_tls1; /* User RW Thread register. */
	121	uint32_t c13_tls2; /* User RO Thread register. */
	122	uint32_t c13_tls3; /* Privileged Thread register. */
c1713132	123	uint32_t c15_cpar; /* XScale Coprocessor Access Register */
c3d2689d AZ	124	uint32_t c15_ticonfig; /* TI925T configuration byte. */
	125	uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
	126	uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
	127	uint32_t c15_threadid; /* TI debugger thread-ID. */
b5ff1b31	128	} cp15;
40f137e1	129
9ee6e8bb PB	130	struct {
	131	uint32_t other_sp;
	132	uint32_t vecbase;
	133	uint32_t basepri;
	134	uint32_t control;
	135	int current_sp;
	136	int exception;
	137	int pending_exception;
	138	void *nvic;
	139	} v7m;
	140
c1713132 AZ	141	/* Coprocessor IO used by peripherals */
	142	struct {
	143	ARMReadCPFunc *cp_read;
	144	ARMWriteCPFunc *cp_write;
	145	void *opaque;
	146	} cp[15];
	147
40f137e1 PB	148	/* Internal CPU feature flags. */
	149	uint32_t features;
	150
9ee6e8bb PB	151	/* Callback for vectored interrupt controller. */
	152	int (get_irq_vector)(struct CPUARMState );
	153	void *irq_opaque;
	154
2c0262af FB	155	/* exception/interrupt handling */
	156	jmp_buf jmp_env;
	157	int exception_index;
	158	int interrupt_request;
2c0262af	159	int user_mode_only;
9332f9da	160	int halted;
2c0262af	161
b7bcbe95 FB	162	/* VFP coprocessor state. */
b7bcbe95 FB	163	struct {
9ee6e8bb	164	float64 regs[32];
b7bcbe95	165
40f137e1	166	uint32_t xregs[16];
b7bcbe95 FB	167	/* We store these fpcsr fields separately for convenience. */
	168	int vec_len;
	169	int vec_stride;
	170
b7bcbe95	171	/* Temporary variables if we don't have spare fp regs. */
53cd6637 FB	172	float32 tmp0s, tmp1s;
53cd6637 FB	173	float64 tmp0d, tmp1d;
9ee6e8bb PB	174	/* scratch space when Tn are not sufficient. */
9ee6e8bb PB	175	uint32_t scratch[8];
3b46e624	176
53cd6637	177	float_status fp_status;
b7bcbe95	178	} vfp;
9ee6e8bb PB	179	#if defined(CONFIG_USER_ONLY)
	180	struct mmon_state *mmon_entry;
	181	#else
	182	uint32_t mmon_addr;
	183	#endif
b7bcbe95	184
18c9b560 AZ	185	/* iwMMXt coprocessor state. */
	186	struct {
	187	uint64_t regs[16];
	188	uint64_t val;
	189
	190	uint32_t cregs[16];
	191	} iwmmxt;
	192
ce4defa0 PB	193	#if defined(CONFIG_USER_ONLY)
	194	/* For usermode syscall translation. */
	195	int eabi;
	196	#endif
	197
a316d335 FB	198	CPU_COMMON
a316d335 FB	199
9d551997	200	/* These fields after the common ones so they are preserved on reset. */
f3d6b95e PB	201	int ram_size;
	202	const char *kernel_filename;
	203	const char *kernel_cmdline;
	204	const char *initrd_filename;
	205	int board_id;
9d551997	206	target_phys_addr_t loader_start;
2c0262af FB	207	} CPUARMState;
2c0262af FB	208
aaed909a	209	CPUARMState cpu_arm_init(const char cpu_model);
2c0262af FB	210	int cpu_arm_exec(CPUARMState *s);
2c0262af FB	211	void cpu_arm_close(CPUARMState *s);
b5ff1b31 FB	212	void do_interrupt(CPUARMState *);
b5ff1b31 FB	213	void switch_mode(CPUARMState *, int);
9ee6e8bb	214	uint32_t do_arm_semihosting(CPUARMState *env);
b5ff1b31	215
2c0262af FB	216	/* you can call this signal handler from your SIGBUS and SIGSEGV
	217	signal handlers to inform the virtual CPU of exceptions. non zero
	218	is returned if the signal was handled by the virtual CPU. */
5fafdf24	219	int cpu_arm_signal_handler(int host_signum, void *pinfo,
2c0262af FB	220	void *puc);
2c0262af FB	221
9ee6e8bb PB	222	void cpu_lock(void);
	223	void cpu_unlock(void);
	224
b5ff1b31 FB	225	#define CPSR_M (0x1f)
	226	#define CPSR_T (1 << 5)
	227	#define CPSR_F (1 << 6)
	228	#define CPSR_I (1 << 7)
	229	#define CPSR_A (1 << 8)
	230	#define CPSR_E (1 << 9)
	231	#define CPSR_IT_2_7 (0xfc00)
9ee6e8bb PB	232	#define CPSR_GE (0xf << 16)
9ee6e8bb PB	233	#define CPSR_RESERVED (0xf << 20)
b5ff1b31 FB	234	#define CPSR_J (1 << 24)
	235	#define CPSR_IT_0_1 (3 << 25)
	236	#define CPSR_Q (1 << 27)
9ee6e8bb PB	237	#define CPSR_V (1 << 28)
	238	#define CPSR_C (1 << 29)
	239	#define CPSR_Z (1 << 30)
	240	#define CPSR_N (1 << 31)
	241	#define CPSR_NZCV (CPSR_N \| CPSR_Z \| CPSR_C \| CPSR_V)
	242
	243	#define CPSR_IT (CPSR_IT_0_1 \| CPSR_IT_2_7)
	244	#define CACHED_CPSR_BITS (CPSR_T \| CPSR_GE \| CPSR_IT \| CPSR_Q \| CPSR_NZCV)
	245	/* Bits writable in user mode. */
	246	#define CPSR_USER (CPSR_NZCV \| CPSR_Q \| CPSR_GE)
	247	/* Execution state bits. MRS read as zero, MSR writes ignored. */
	248	#define CPSR_EXEC (CPSR_T \| CPSR_IT \| CPSR_J)
b5ff1b31	249
b5ff1b31 FB	250	/* Return the current CPSR value. */
	251	static inline uint32_t cpsr_read(CPUARMState *env)
	252	{
	253	int ZF;
	254	ZF = (env->NZF == 0);
5fafdf24	255	return env->uncached_cpsr \| (env->NZF & 0x80000000) \| (ZF << 30) \|
b5ff1b31	256	(env->CF << 29) \| ((env->VF & 0x80000000) >> 3) \| (env->QF << 27)
9ee6e8bb PB	257	\| (env->thumb << 5) \| ((env->condexec_bits & 3) << 25)
	258	\| ((env->condexec_bits & 0xfc) << 8)
	259	\| (env->GE << 16);
	260	}
	261
	262	/* Return the current xPSR value. */
	263	static inline uint32_t xpsr_read(CPUARMState *env)
	264	{
	265	int ZF;
	266	ZF = (env->NZF == 0);
	267	return (env->NZF & 0x80000000) \| (ZF << 30)
	268	\| (env->CF << 29) \| ((env->VF & 0x80000000) >> 3) \| (env->QF << 27)
	269	\| (env->thumb << 24) \| ((env->condexec_bits & 3) << 25)
	270	\| ((env->condexec_bits & 0xfc) << 8)
	271	\| env->v7m.exception;
b5ff1b31 FB	272	}
	273
	274	/* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
	275	static inline void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
	276	{
	277	/* NOTE: N = 1 and Z = 1 cannot be stored currently */
	278	if (mask & CPSR_NZCV) {
	279	env->NZF = (val & 0xc0000000) ^ 0x40000000;
	280	env->CF = (val >> 29) & 1;
	281	env->VF = (val << 3) & 0x80000000;
	282	}
	283	if (mask & CPSR_Q)
	284	env->QF = ((val & CPSR_Q) != 0);
	285	if (mask & CPSR_T)
	286	env->thumb = ((val & CPSR_T) != 0);
9ee6e8bb PB	287	if (mask & CPSR_IT_0_1) {
	288	env->condexec_bits &= ~3;
	289	env->condexec_bits \|= (val >> 25) & 3;
	290	}
	291	if (mask & CPSR_IT_2_7) {
	292	env->condexec_bits &= 3;
	293	env->condexec_bits \|= (val >> 8) & 0xfc;
	294	}
	295	if (mask & CPSR_GE) {
	296	env->GE = (val >> 16) & 0xf;
	297	}
b5ff1b31 FB	298
	299	if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
	300	switch_mode(env, val & CPSR_M);
	301	}
	302	mask &= ~CACHED_CPSR_BITS;
	303	env->uncached_cpsr = (env->uncached_cpsr & ~mask) \| (val & mask);
	304	}
	305
9ee6e8bb PB	306	/* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
	307	static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
	308	{
	309	/* NOTE: N = 1 and Z = 1 cannot be stored currently */
	310	if (mask & CPSR_NZCV) {
	311	env->NZF = (val & 0xc0000000) ^ 0x40000000;
	312	env->CF = (val >> 29) & 1;
	313	env->VF = (val << 3) & 0x80000000;
	314	}
	315	if (mask & CPSR_Q)
	316	env->QF = ((val & CPSR_Q) != 0);
	317	if (mask & (1 << 24))
	318	env->thumb = ((val & (1 << 24)) != 0);
	319	if (mask & CPSR_IT_0_1) {
	320	env->condexec_bits &= ~3;
	321	env->condexec_bits \|= (val >> 25) & 3;
	322	}
	323	if (mask & CPSR_IT_2_7) {
	324	env->condexec_bits &= 3;
	325	env->condexec_bits \|= (val >> 8) & 0xfc;
	326	}
	327	if (mask & 0x1ff) {
	328	env->v7m.exception = val & 0x1ff;
	329	}
	330	}
	331
b5ff1b31 FB	332	enum arm_cpu_mode {
	333	ARM_CPU_MODE_USR = 0x10,
	334	ARM_CPU_MODE_FIQ = 0x11,
	335	ARM_CPU_MODE_IRQ = 0x12,
	336	ARM_CPU_MODE_SVC = 0x13,
	337	ARM_CPU_MODE_ABT = 0x17,
	338	ARM_CPU_MODE_UND = 0x1b,
	339	ARM_CPU_MODE_SYS = 0x1f
	340	};
	341
40f137e1 PB	342	/* VFP system registers. */
	343	#define ARM_VFP_FPSID 0
	344	#define ARM_VFP_FPSCR 1
9ee6e8bb PB	345	#define ARM_VFP_MVFR1 6
9ee6e8bb PB	346	#define ARM_VFP_MVFR0 7
40f137e1 PB	347	#define ARM_VFP_FPEXC 8
	348	#define ARM_VFP_FPINST 9
	349	#define ARM_VFP_FPINST2 10
	350
18c9b560 AZ	351	/* iwMMXt coprocessor control registers. */
	352	#define ARM_IWMMXT_wCID 0
	353	#define ARM_IWMMXT_wCon 1
	354	#define ARM_IWMMXT_wCSSF 2
	355	#define ARM_IWMMXT_wCASF 3
	356	#define ARM_IWMMXT_wCGR0 8
	357	#define ARM_IWMMXT_wCGR1 9
	358	#define ARM_IWMMXT_wCGR2 10
	359	#define ARM_IWMMXT_wCGR3 11
	360
40f137e1 PB	361	enum arm_features {
40f137e1 PB	362	ARM_FEATURE_VFP,
c1713132 AZ	363	ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
c1713132 AZ	364	ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
ce819861	365	ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
9ee6e8bb PB	366	ARM_FEATURE_V6,
	367	ARM_FEATURE_V6K,
	368	ARM_FEATURE_V7,
	369	ARM_FEATURE_THUMB2,
c3d2689d	370	ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
9ee6e8bb PB	371	ARM_FEATURE_VFP3,
	372	ARM_FEATURE_NEON,
	373	ARM_FEATURE_DIV,
	374	ARM_FEATURE_M, /* Microcontroller profile. */
c3d2689d	375	ARM_FEATURE_OMAPCP /* OMAP specific CP15 ops handling. */
40f137e1 PB	376	};
	377
	378	static inline int arm_feature(CPUARMState *env, int feature)
	379	{
	380	return (env->features & (1u << feature)) != 0;
	381	}
	382
c732abe2	383	void arm_cpu_list(FILE f, int (cpu_fprintf)(FILE f, const char fmt, ...));
40f137e1	384
9ee6e8bb PB	385	/* Interface between CPU and Interrupt controller. */
	386	void armv7m_nvic_set_pending(void *opaque, int irq);
	387	int armv7m_nvic_acknowledge_irq(void *opaque);
	388	void armv7m_nvic_complete_irq(void *opaque, int irq);
	389
c1713132 AZ	390	void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
	391	ARMReadCPFunc cp_read, ARMWriteCPFunc cp_write,
	392	void *opaque);
	393
9ee6e8bb PB	394	/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
	395	Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
	396	conventional cores (ie. Application or Realtime profile). */
	397
	398	#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
	399	#define ARM_CPUID(env) (env->cp15.c0_cpuid)
	400
	401	#define ARM_CPUID_ARM1026 0x4106a262
	402	#define ARM_CPUID_ARM926 0x41069265
	403	#define ARM_CPUID_ARM946 0x41059461
	404	#define ARM_CPUID_TI915T 0x54029152
	405	#define ARM_CPUID_TI925T 0x54029252
	406	#define ARM_CPUID_PXA250 0x69052100
	407	#define ARM_CPUID_PXA255 0x69052d00
	408	#define ARM_CPUID_PXA260 0x69052903
	409	#define ARM_CPUID_PXA261 0x69052d05
	410	#define ARM_CPUID_PXA262 0x69052d06
	411	#define ARM_CPUID_PXA270 0x69054110
	412	#define ARM_CPUID_PXA270_A0 0x69054110
	413	#define ARM_CPUID_PXA270_A1 0x69054111
	414	#define ARM_CPUID_PXA270_B0 0x69054112
	415	#define ARM_CPUID_PXA270_B1 0x69054113
	416	#define ARM_CPUID_PXA270_C0 0x69054114
	417	#define ARM_CPUID_PXA270_C5 0x69054117
	418	#define ARM_CPUID_ARM1136 0x4117b363
	419	#define ARM_CPUID_ARM11MPCORE 0x410fb022
	420	#define ARM_CPUID_CORTEXA8 0x410fc080
	421	#define ARM_CPUID_CORTEXM3 0x410fc231
	422	#define ARM_CPUID_ANY 0xffffffff
40f137e1	423
b5ff1b31	424	#if defined(CONFIG_USER_ONLY)
2c0262af	425	#define TARGET_PAGE_BITS 12
b5ff1b31 FB	426	#else
	427	/* The ARM MMU allows 1k pages. */
	428	/* ??? Linux doesn't actually use these, and they're deprecated in recent
82d17978	429	architecture revisions. Maybe a configure option to disable them. */
b5ff1b31 FB	430	#define TARGET_PAGE_BITS 10
b5ff1b31 FB	431	#endif
9467d44c TS	432
	433	#define CPUState CPUARMState
	434	#define cpu_init cpu_arm_init
	435	#define cpu_exec cpu_arm_exec
	436	#define cpu_gen_code cpu_arm_gen_code
	437	#define cpu_signal_handler cpu_arm_signal_handler
c732abe2	438	#define cpu_list arm_cpu_list
9467d44c	439
9ee6e8bb PB	440	#define ARM_CPU_SAVE_VERSION 1
9ee6e8bb PB	441
6ebbf390 JM	442	/* MMU modes definitions */
	443	#define MMU_MODE0_SUFFIX _kernel
	444	#define MMU_MODE1_SUFFIX _user
	445	#define MMU_USER_IDX 1
	446	static inline int cpu_mmu_index (CPUState *env)
	447	{
	448	return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
	449	}
	450
2c0262af FB	451	#include "cpu-all.h"
	452
	453	#endif