[mirror_qemu.git] / target-arm / machine.c

#include "hw/hw.h"
#include "hw/boards.h"

void register_machines(void)
{
    qemu_register_machine(&integratorcp_machine);
    qemu_register_machine(&versatilepb_machine);
    qemu_register_machine(&versatileab_machine);
    qemu_register_machine(&realview_machine);
    qemu_register_machine(&akitapda_machine);
    qemu_register_machine(&spitzpda_machine);
    qemu_register_machine(&borzoipda_machine);
    qemu_register_machine(&terrierpda_machine);
    qemu_register_machine(&palmte_machine);
    qemu_register_machine(&n800_machine);
    qemu_register_machine(&n810_machine);
    qemu_register_machine(&lm3s811evb_machine);
    qemu_register_machine(&lm3s6965evb_machine);
    qemu_register_machine(&connex_machine);
    qemu_register_machine(&verdex_machine);
    qemu_register_machine(&mainstone2_machine);
    qemu_register_machine(&musicpal_machine);
}

void cpu_save(QEMUFile *f, void *opaque)
{
    int i;
    CPUARMState *env = (CPUARMState *)opaque;

    for (i = 0; i < 16; i++) {
        qemu_put_be32(f, env->regs[i]);
    }
    qemu_put_be32(f, cpsr_read(env));
    qemu_put_be32(f, env->spsr);
    for (i = 0; i < 6; i++) {
        qemu_put_be32(f, env->banked_spsr[i]);
        qemu_put_be32(f, env->banked_r13[i]);
        qemu_put_be32(f, env->banked_r14[i]);
    }
    for (i = 0; i < 5; i++) {
        qemu_put_be32(f, env->usr_regs[i]);
        qemu_put_be32(f, env->fiq_regs[i]);
    }
    qemu_put_be32(f, env->cp15.c0_cpuid);
    qemu_put_be32(f, env->cp15.c0_cachetype);
    qemu_put_be32(f, env->cp15.c1_sys);
    qemu_put_be32(f, env->cp15.c1_coproc);
    qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
    qemu_put_be32(f, env->cp15.c2_base0);
    qemu_put_be32(f, env->cp15.c2_base1);
    qemu_put_be32(f, env->cp15.c2_mask);
    qemu_put_be32(f, env->cp15.c2_data);
    qemu_put_be32(f, env->cp15.c2_insn);
    qemu_put_be32(f, env->cp15.c3);
    qemu_put_be32(f, env->cp15.c5_insn);
    qemu_put_be32(f, env->cp15.c5_data);
    for (i = 0; i < 8; i++) {
        qemu_put_be32(f, env->cp15.c6_region[i]);
    }
    qemu_put_be32(f, env->cp15.c6_insn);
    qemu_put_be32(f, env->cp15.c6_data);
    qemu_put_be32(f, env->cp15.c9_insn);
    qemu_put_be32(f, env->cp15.c9_data);
    qemu_put_be32(f, env->cp15.c13_fcse);
    qemu_put_be32(f, env->cp15.c13_context);
    qemu_put_be32(f, env->cp15.c13_tls1);
    qemu_put_be32(f, env->cp15.c13_tls2);
    qemu_put_be32(f, env->cp15.c13_tls3);
    qemu_put_be32(f, env->cp15.c15_cpar);

    qemu_put_be32(f, env->features);

    if (arm_feature(env, ARM_FEATURE_VFP)) {
        for (i = 0;  i < 16; i++) {
            CPU_DoubleU u;
            u.d = env->vfp.regs[i];
            qemu_put_be32(f, u.l.upper);
            qemu_put_be32(f, u.l.lower);
        }
        for (i = 0; i < 16; i++) {
            qemu_put_be32(f, env->vfp.xregs[i]);
        }

        /* TODO: Should use proper FPSCR access functions.  */
        qemu_put_be32(f, env->vfp.vec_len);
        qemu_put_be32(f, env->vfp.vec_stride);

        if (arm_feature(env, ARM_FEATURE_VFP3)) {
            for (i = 16;  i < 32; i++) {
                CPU_DoubleU u;
                u.d = env->vfp.regs[i];
                qemu_put_be32(f, u.l.upper);
                qemu_put_be32(f, u.l.lower);
            }
        }
    }

    if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
        for (i = 0; i < 16; i++) {
            qemu_put_be64(f, env->iwmmxt.regs[i]);
        }
        for (i = 0; i < 16; i++) {
            qemu_put_be32(f, env->iwmmxt.cregs[i]);
        }
    }

    if (arm_feature(env, ARM_FEATURE_M)) {
        qemu_put_be32(f, env->v7m.other_sp);
        qemu_put_be32(f, env->v7m.vecbase);
        qemu_put_be32(f, env->v7m.basepri);
        qemu_put_be32(f, env->v7m.control);
        qemu_put_be32(f, env->v7m.current_sp);
        qemu_put_be32(f, env->v7m.exception);
    }
}

int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
    CPUARMState *env = (CPUARMState *)opaque;
    int i;

    if (version_id != ARM_CPU_SAVE_VERSION)
        return -EINVAL;

    for (i = 0; i < 16; i++) {
        env->regs[i] = qemu_get_be32(f);
    }
    cpsr_write(env, qemu_get_be32(f), 0xffffffff);
    env->spsr = qemu_get_be32(f);
    for (i = 0; i < 6; i++) {
        env->banked_spsr[i] = qemu_get_be32(f);
        env->banked_r13[i] = qemu_get_be32(f);
        env->banked_r14[i] = qemu_get_be32(f);
    }
    for (i = 0; i < 5; i++) {
        env->usr_regs[i] = qemu_get_be32(f);
        env->fiq_regs[i] = qemu_get_be32(f);
    }
    env->cp15.c0_cpuid = qemu_get_be32(f);
    env->cp15.c0_cachetype = qemu_get_be32(f);
    env->cp15.c1_sys = qemu_get_be32(f);
    env->cp15.c1_coproc = qemu_get_be32(f);
    env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
    env->cp15.c2_base0 = qemu_get_be32(f);
    env->cp15.c2_base1 = qemu_get_be32(f);
    env->cp15.c2_mask = qemu_get_be32(f);
    env->cp15.c2_data = qemu_get_be32(f);
    env->cp15.c2_insn = qemu_get_be32(f);
    env->cp15.c3 = qemu_get_be32(f);
    env->cp15.c5_insn = qemu_get_be32(f);
    env->cp15.c5_data = qemu_get_be32(f);
    for (i = 0; i < 8; i++) {
        env->cp15.c6_region[i] = qemu_get_be32(f);
    }
    env->cp15.c6_insn = qemu_get_be32(f);
    env->cp15.c6_data = qemu_get_be32(f);
    env->cp15.c9_insn = qemu_get_be32(f);
    env->cp15.c9_data = qemu_get_be32(f);
    env->cp15.c13_fcse = qemu_get_be32(f);
    env->cp15.c13_context = qemu_get_be32(f);
    env->cp15.c13_tls1 = qemu_get_be32(f);
    env->cp15.c13_tls2 = qemu_get_be32(f);
    env->cp15.c13_tls3 = qemu_get_be32(f);
    env->cp15.c15_cpar = qemu_get_be32(f);

    env->features = qemu_get_be32(f);

    if (arm_feature(env, ARM_FEATURE_VFP)) {
        for (i = 0;  i < 16; i++) {
            CPU_DoubleU u;
            u.l.upper = qemu_get_be32(f);
            u.l.lower = qemu_get_be32(f);
            env->vfp.regs[i] = u.d;
        }
        for (i = 0; i < 16; i++) {
            env->vfp.xregs[i] = qemu_get_be32(f);
        }

        /* TODO: Should use proper FPSCR access functions.  */
        env->vfp.vec_len = qemu_get_be32(f);
        env->vfp.vec_stride = qemu_get_be32(f);

        if (arm_feature(env, ARM_FEATURE_VFP3)) {
            for (i = 0;  i < 16; i++) {
                CPU_DoubleU u;
                u.l.upper = qemu_get_be32(f);
                u.l.lower = qemu_get_be32(f);
                env->vfp.regs[i] = u.d;
            }
        }
    }

    if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
        for (i = 0; i < 16; i++) {
            env->iwmmxt.regs[i] = qemu_get_be64(f);
        }
        for (i = 0; i < 16; i++) {
            env->iwmmxt.cregs[i] = qemu_get_be32(f);
        }
    }

    if (arm_feature(env, ARM_FEATURE_M)) {
        env->v7m.other_sp = qemu_get_be32(f);
        env->v7m.vecbase = qemu_get_be32(f);
        env->v7m.basepri = qemu_get_be32(f);
        env->v7m.control = qemu_get_be32(f);
        env->v7m.current_sp = qemu_get_be32(f);
        env->v7m.exception = qemu_get_be32(f);
    }

    return 0;
}
Commit	Line	Data
8dd3dca3 AJ	1	#include "hw/hw.h"
	2	#include "hw/boards.h"
	3
	4	void register_machines(void)
	5	{
	6	qemu_register_machine(&integratorcp_machine);
	7	qemu_register_machine(&versatilepb_machine);
	8	qemu_register_machine(&versatileab_machine);
	9	qemu_register_machine(&realview_machine);
	10	qemu_register_machine(&akitapda_machine);
	11	qemu_register_machine(&spitzpda_machine);
	12	qemu_register_machine(&borzoipda_machine);
	13	qemu_register_machine(&terrierpda_machine);
	14	qemu_register_machine(&palmte_machine);
	15	qemu_register_machine(&n800_machine);
c30bb264	16	qemu_register_machine(&n810_machine);
8dd3dca3 AJ	17	qemu_register_machine(&lm3s811evb_machine);
	18	qemu_register_machine(&lm3s6965evb_machine);
	19	qemu_register_machine(&connex_machine);
	20	qemu_register_machine(&verdex_machine);
	21	qemu_register_machine(&mainstone2_machine);
	22	qemu_register_machine(&musicpal_machine);
	23	}
	24
	25	void cpu_save(QEMUFile f, void opaque)
	26	{
	27	int i;
	28	CPUARMState env = (CPUARMState )opaque;
	29
	30	for (i = 0; i < 16; i++) {
	31	qemu_put_be32(f, env->regs[i]);
	32	}
	33	qemu_put_be32(f, cpsr_read(env));
	34	qemu_put_be32(f, env->spsr);
	35	for (i = 0; i < 6; i++) {
	36	qemu_put_be32(f, env->banked_spsr[i]);
	37	qemu_put_be32(f, env->banked_r13[i]);
	38	qemu_put_be32(f, env->banked_r14[i]);
	39	}
	40	for (i = 0; i < 5; i++) {
	41	qemu_put_be32(f, env->usr_regs[i]);
	42	qemu_put_be32(f, env->fiq_regs[i]);
	43	}
	44	qemu_put_be32(f, env->cp15.c0_cpuid);
	45	qemu_put_be32(f, env->cp15.c0_cachetype);
	46	qemu_put_be32(f, env->cp15.c1_sys);
	47	qemu_put_be32(f, env->cp15.c1_coproc);
	48	qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
	49	qemu_put_be32(f, env->cp15.c2_base0);
	50	qemu_put_be32(f, env->cp15.c2_base1);
	51	qemu_put_be32(f, env->cp15.c2_mask);
	52	qemu_put_be32(f, env->cp15.c2_data);
	53	qemu_put_be32(f, env->cp15.c2_insn);
	54	qemu_put_be32(f, env->cp15.c3);
	55	qemu_put_be32(f, env->cp15.c5_insn);
	56	qemu_put_be32(f, env->cp15.c5_data);
	57	for (i = 0; i < 8; i++) {
	58	qemu_put_be32(f, env->cp15.c6_region[i]);
	59	}
	60	qemu_put_be32(f, env->cp15.c6_insn);
	61	qemu_put_be32(f, env->cp15.c6_data);
	62	qemu_put_be32(f, env->cp15.c9_insn);
	63	qemu_put_be32(f, env->cp15.c9_data);
	64	qemu_put_be32(f, env->cp15.c13_fcse);
	65	qemu_put_be32(f, env->cp15.c13_context);
	66	qemu_put_be32(f, env->cp15.c13_tls1);
	67	qemu_put_be32(f, env->cp15.c13_tls2);
	68	qemu_put_be32(f, env->cp15.c13_tls3);
	69	qemu_put_be32(f, env->cp15.c15_cpar);
	70
	71	qemu_put_be32(f, env->features);
	72
	73	if (arm_feature(env, ARM_FEATURE_VFP)) {
	74	for (i = 0; i < 16; i++) {
	75	CPU_DoubleU u;
	76	u.d = env->vfp.regs[i];
	77	qemu_put_be32(f, u.l.upper);
	78	qemu_put_be32(f, u.l.lower);
	79	}
	80	for (i = 0; i < 16; i++) {
81	qemu_put_be32(f, env->vfp.xregs[i]);
82	}
83
84	/* TODO: Should use proper FPSCR access functions. */
85	qemu_put_be32(f, env->vfp.vec_len);
86	qemu_put_be32(f, env->vfp.vec_stride);
87
88	if (arm_feature(env, ARM_FEATURE_VFP3)) {
89	for (i = 16; i < 32; i++) {
90	CPU_DoubleU u;
91	u.d = env->vfp.regs[i];
92	qemu_put_be32(f, u.l.upper);
93	qemu_put_be32(f, u.l.lower);
94	}
95	}
96	}
97
98	if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
99	for (i = 0; i < 16; i++) {
100	qemu_put_be64(f, env->iwmmxt.regs[i]);
101	}
102	for (i = 0; i < 16; i++) {
103	qemu_put_be32(f, env->iwmmxt.cregs[i]);
104	}
105	}
106
107	if (arm_feature(env, ARM_FEATURE_M)) {
108	qemu_put_be32(f, env->v7m.other_sp);
109	qemu_put_be32(f, env->v7m.vecbase);
110	qemu_put_be32(f, env->v7m.basepri);
111	qemu_put_be32(f, env->v7m.control);
112	qemu_put_be32(f, env->v7m.current_sp);
113	qemu_put_be32(f, env->v7m.exception);
114	}
115	}
116
117	int cpu_load(QEMUFile f, void opaque, int version_id)
118	{
119	CPUARMState env = (CPUARMState )opaque;
120	int i;
121
122	if (version_id != ARM_CPU_SAVE_VERSION)
123	return -EINVAL;
124
125	for (i = 0; i < 16; i++) {
126	env->regs[i] = qemu_get_be32(f);
127	}
128	cpsr_write(env, qemu_get_be32(f), 0xffffffff);
129	env->spsr = qemu_get_be32(f);
130	for (i = 0; i < 6; i++) {
131	env->banked_spsr[i] = qemu_get_be32(f);
132	env->banked_r13[i] = qemu_get_be32(f);
133	env->banked_r14[i] = qemu_get_be32(f);
134	}
135	for (i = 0; i < 5; i++) {
136	env->usr_regs[i] = qemu_get_be32(f);
137	env->fiq_regs[i] = qemu_get_be32(f);
138	}
139	env->cp15.c0_cpuid = qemu_get_be32(f);
140	env->cp15.c0_cachetype = qemu_get_be32(f);
141	env->cp15.c1_sys = qemu_get_be32(f);
142	env->cp15.c1_coproc = qemu_get_be32(f);
143	env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
144	env->cp15.c2_base0 = qemu_get_be32(f);
145	env->cp15.c2_base1 = qemu_get_be32(f);
146	env->cp15.c2_mask = qemu_get_be32(f);
147	env->cp15.c2_data = qemu_get_be32(f);
148	env->cp15.c2_insn = qemu_get_be32(f);
149	env->cp15.c3 = qemu_get_be32(f);
150	env->cp15.c5_insn = qemu_get_be32(f);
151	env->cp15.c5_data = qemu_get_be32(f);
152	for (i = 0; i < 8; i++) {
153	env->cp15.c6_region[i] = qemu_get_be32(f);
154	}
155	env->cp15.c6_insn = qemu_get_be32(f);
156	env->cp15.c6_data = qemu_get_be32(f);
157	env->cp15.c9_insn = qemu_get_be32(f);
158	env->cp15.c9_data = qemu_get_be32(f);
159	env->cp15.c13_fcse = qemu_get_be32(f);
160	env->cp15.c13_context = qemu_get_be32(f);
161	env->cp15.c13_tls1 = qemu_get_be32(f);
162	env->cp15.c13_tls2 = qemu_get_be32(f);
163	env->cp15.c13_tls3 = qemu_get_be32(f);
164	env->cp15.c15_cpar = qemu_get_be32(f);
165
166	env->features = qemu_get_be32(f);
167
168	if (arm_feature(env, ARM_FEATURE_VFP)) {
169	for (i = 0; i < 16; i++) {
170	CPU_DoubleU u;
171	u.l.upper = qemu_get_be32(f);
172	u.l.lower = qemu_get_be32(f);
173	env->vfp.regs[i] = u.d;
174	}
175	for (i = 0; i < 16; i++) {
176	env->vfp.xregs[i] = qemu_get_be32(f);
177	}
178
179	/* TODO: Should use proper FPSCR access functions. */
180	env->vfp.vec_len = qemu_get_be32(f);
181	env->vfp.vec_stride = qemu_get_be32(f);
182
183	if (arm_feature(env, ARM_FEATURE_VFP3)) {
184	for (i = 0; i < 16; i++) {
185	CPU_DoubleU u;
186	u.l.upper = qemu_get_be32(f);
187	u.l.lower = qemu_get_be32(f);
188	env->vfp.regs[i] = u.d;
189	}
190	}
191	}
192
193	if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
194	for (i = 0; i < 16; i++) {
195	env->iwmmxt.regs[i] = qemu_get_be64(f);
196	}
197	for (i = 0; i < 16; i++) {
198	env->iwmmxt.cregs[i] = qemu_get_be32(f);
199	}
200	}
201
202	if (arm_feature(env, ARM_FEATURE_M)) {
203	env->v7m.other_sp = qemu_get_be32(f);
204	env->v7m.vecbase = qemu_get_be32(f);
205	env->v7m.basepri = qemu_get_be32(f);
206	env->v7m.control = qemu_get_be32(f);
207	env->v7m.current_sp = qemu_get_be32(f);
208	env->v7m.exception = qemu_get_be32(f);
209	}
210
211	return 0;
212	}
213
214