[mirror_qemu.git] / target-mips / helper.c

/*
 *  MIPS emulation helpers for qemu.
 *
 *  Copyright (c) 2004-2005 Jocelyn Mayer
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include <assert.h>

#include "cpu.h"
#include "exec-all.h"

enum {
    TLBRET_DIRTY = -4,
    TLBRET_INVALID = -3,
    TLBRET_NOMATCH = -2,
    TLBRET_BADADDR = -1,
    TLBRET_MATCH = 0
};

/* no MMU emulation */
int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
                        target_ulong address, int rw, int access_type)
{
    *physical = address;
    *prot = PAGE_READ | PAGE_WRITE;
    return TLBRET_MATCH;
}

/* fixed mapping MMU emulation */
int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
                           target_ulong address, int rw, int access_type)
{
    if (address <= (int32_t)0x7FFFFFFFUL) {
        if (!(env->CP0_Status & (1 << CP0St_ERL)))
            *physical = address + 0x40000000UL;
        else
            *physical = address;
    } else if (address <= (int32_t)0xBFFFFFFFUL)
        *physical = address & 0x1FFFFFFF;
    else
        *physical = address;

    *prot = PAGE_READ | PAGE_WRITE;
    return TLBRET_MATCH;
}

/* MIPS32/MIPS64 R4000-style MMU emulation */
int r4k_map_address (CPUState *env, target_ulong *physical, int *prot,
                     target_ulong address, int rw, int access_type)
{
    uint8_t ASID = env->CP0_EntryHi & 0xFF;
    int i;

    for (i = 0; i < env->tlb->tlb_in_use; i++) {
        r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
        /* 1k pages are not supported. */
        target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
        target_ulong tag = address & ~mask;
        target_ulong VPN = tlb->VPN & ~mask;
#ifdef TARGET_MIPS64
        tag &= env->SEGMask;
#endif

        /* Check ASID, virtual page number & size */
        if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
            /* TLB match */
            int n = !!(address & mask & ~(mask >> 1));
            /* Check access rights */
            if (!(n ? tlb->V1 : tlb->V0))
                return TLBRET_INVALID;
            if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
                *physical = tlb->PFN[n] | (address & (mask >> 1));
                *prot = PAGE_READ;
                if (n ? tlb->D1 : tlb->D0)
                    *prot |= PAGE_WRITE;
                return TLBRET_MATCH;
            }
            return TLBRET_DIRTY;
        }
    }
    return TLBRET_NOMATCH;
}

static int get_physical_address (CPUState *env, target_ulong *physical,
                                int *prot, target_ulong address,
                                int rw, int access_type)
{
    /* User mode can only access useg/xuseg */
    int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
#ifdef TARGET_MIPS64
    int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
    int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
    int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
#endif
    int ret = TLBRET_MATCH;

#if 0
    if (logfile) {
        fprintf(logfile, "user mode %d h %08x\n",
                user_mode, env->hflags);
    }
#endif

#ifdef TARGET_MIPS64
    if (user_mode && address > 0x3FFFFFFFFFFFFFFFULL)
        return TLBRET_BADADDR;
#else
    if (user_mode && address > 0x7FFFFFFFUL)
        return TLBRET_BADADDR;
#endif

    if (address <= (int32_t)0x7FFFFFFFUL) {
        /* useg */
        if (env->CP0_Status & (1 << CP0St_ERL)) {
            *physical = address & 0xFFFFFFFF;
            *prot = PAGE_READ | PAGE_WRITE;
        } else {
            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
        }
#ifdef TARGET_MIPS64
/*
   XXX: Assuming :
   - PABITS = 36 (correct for MIPS64R1)
*/
    } else if (address < 0x3FFFFFFFFFFFFFFFULL) {
        /* xuseg */
	if (UX && address < (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
	} else {
	    ret = TLBRET_BADADDR;
        }
    } else if (address < 0x7FFFFFFFFFFFFFFFULL) {
        /* xsseg */
	if (SX && address < (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
	} else {
	    ret = TLBRET_BADADDR;
        }
    } else if (address < 0xBFFFFFFFFFFFFFFFULL) {
        /* xkphys */
        /* XXX: check supervisor mode */
        if (KX && (address & 0x07FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL)
	{
            *physical = address & 0X0000000FFFFFFFFFULL;
            *prot = PAGE_READ | PAGE_WRITE;
	} else {
	    ret = TLBRET_BADADDR;
	}
    } else if (address < 0xFFFFFFFF7FFFFFFFULL) {
        /* xkseg */
        /* XXX: check supervisor mode */
	if (KX && address < (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
	} else {
	    ret = TLBRET_BADADDR;
	}
#endif
    } else if (address < (int32_t)0xA0000000UL) {
        /* kseg0 */
        /* XXX: check supervisor mode */
        *physical = address - (int32_t)0x80000000UL;
        *prot = PAGE_READ | PAGE_WRITE;
    } else if (address < (int32_t)0xC0000000UL) {
        /* kseg1 */
        /* XXX: check supervisor mode */
        *physical = address - (int32_t)0xA0000000UL;
        *prot = PAGE_READ | PAGE_WRITE;
    } else if (address < (int32_t)0xE0000000UL) {
        /* kseg2 */
        ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
    } else {
        /* kseg3 */
        /* XXX: check supervisor mode */
        /* XXX: debug segment is not emulated */
        ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
    }
#if 0
    if (logfile) {
        fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
		address, rw, access_type, *physical, *prot, ret);
    }
#endif

    return ret;
}

#if defined(CONFIG_USER_ONLY)
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
    return addr;
}
#else
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
    target_ulong phys_addr;
    int prot;

    if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
        return -1;
    return phys_addr;
}

void cpu_mips_init_mmu (CPUState *env)
{
}
#endif /* !defined(CONFIG_USER_ONLY) */

int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                               int is_user, int is_softmmu)
{
    target_ulong physical;
    int prot;
    int exception = 0, error_code = 0;
    int access_type;
    int ret = 0;

    if (logfile) {
#if 0
        cpu_dump_state(env, logfile, fprintf, 0);
#endif
        fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n",
                __func__, env->PC[env->current_tc], address, rw, is_user, is_softmmu);
    }

    rw &= 1;

    /* data access */
    /* XXX: put correct access by using cpu_restore_state()
       correctly */
    access_type = ACCESS_INT;
    if (env->user_mode_only) {
        /* user mode only emulation */
        ret = TLBRET_NOMATCH;
        goto do_fault;
    }
    ret = get_physical_address(env, &physical, &prot,
                               address, rw, access_type);
    if (logfile) {
        fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
                __func__, address, ret, physical, prot);
    }
    if (ret == TLBRET_MATCH) {
       ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
                          physical & TARGET_PAGE_MASK, prot,
                          is_user, is_softmmu);
    } else if (ret < 0) {
    do_fault:
        switch (ret) {
        default:
        case TLBRET_BADADDR:
            /* Reference to kernel address from user mode or supervisor mode */
            /* Reference to supervisor address from user mode */
            if (rw)
                exception = EXCP_AdES;
            else
                exception = EXCP_AdEL;
            break;
        case TLBRET_NOMATCH:
            /* No TLB match for a mapped address */
            if (rw)
                exception = EXCP_TLBS;
            else
                exception = EXCP_TLBL;
            error_code = 1;
            break;
        case TLBRET_INVALID:
            /* TLB match with no valid bit */
            if (rw)
                exception = EXCP_TLBS;
            else
                exception = EXCP_TLBL;
            break;
        case TLBRET_DIRTY:
            /* TLB match but 'D' bit is cleared */
            exception = EXCP_LTLBL;
            break;

        }
        /* Raise exception */
        env->CP0_BadVAddr = address;
        env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
	                   ((address >> 9) &   0x007ffff0);
        env->CP0_EntryHi =
            (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
#ifdef TARGET_MIPS64
        env->CP0_EntryHi &= env->SEGMask;
        env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
                            ((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) |
                            ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
#endif
        env->exception_index = exception;
        env->error_code = error_code;
        ret = 1;
    }

    return ret;
}

#if defined(CONFIG_USER_ONLY)
void do_interrupt (CPUState *env)
{
    env->exception_index = EXCP_NONE;
}
#else
void do_interrupt (CPUState *env)
{
    target_ulong offset;
    int cause = -1;

    if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
        fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n",
                __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index);
    }
    if (env->exception_index == EXCP_EXT_INTERRUPT &&
        (env->hflags & MIPS_HFLAG_DM))
        env->exception_index = EXCP_DINT;
    offset = 0x180;
    switch (env->exception_index) {
    case EXCP_DSS:
        env->CP0_Debug |= 1 << CP0DB_DSS;
        /* Debug single step cannot be raised inside a delay slot and
         * resume will always occur on the next instruction
         * (but we assume the pc has always been updated during
         *  code translation).
         */
        env->CP0_DEPC = env->PC[env->current_tc];
        goto enter_debug_mode;
    case EXCP_DINT:
        env->CP0_Debug |= 1 << CP0DB_DINT;
        goto set_DEPC;
    case EXCP_DIB:
        env->CP0_Debug |= 1 << CP0DB_DIB;
        goto set_DEPC;
    case EXCP_DBp:
        env->CP0_Debug |= 1 << CP0DB_DBp;
        goto set_DEPC;
    case EXCP_DDBS:
        env->CP0_Debug |= 1 << CP0DB_DDBS;
        goto set_DEPC;
    case EXCP_DDBL:
        env->CP0_Debug |= 1 << CP0DB_DDBL;
    set_DEPC:
        if (env->hflags & MIPS_HFLAG_BMASK) {
            /* If the exception was raised from a delay slot,
               come back to the jump.  */
            env->CP0_DEPC = env->PC[env->current_tc] - 4;
            env->hflags &= ~MIPS_HFLAG_BMASK;
        } else {
            env->CP0_DEPC = env->PC[env->current_tc];
        }
    enter_debug_mode:
        env->hflags |= MIPS_HFLAG_DM;
        if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
            env->hflags |= MIPS_HFLAG_64;
        env->hflags &= ~MIPS_HFLAG_UM;
        /* EJTAG probe trap enable is not implemented... */
        if (!(env->CP0_Status & (1 << CP0St_EXL)))
            env->CP0_Cause &= ~(1 << CP0Ca_BD);
        env->PC[env->current_tc] = (int32_t)0xBFC00480;
        break;
    case EXCP_RESET:
        cpu_reset(env);
        break;
    case EXCP_SRESET:
        env->CP0_Status |= (1 << CP0St_SR);
        memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
        goto set_error_EPC;
    case EXCP_NMI:
        env->CP0_Status |= (1 << CP0St_NMI);
    set_error_EPC:
        if (env->hflags & MIPS_HFLAG_BMASK) {
            /* If the exception was raised from a delay slot,
               come back to the jump.  */
            env->CP0_ErrorEPC = env->PC[env->current_tc] - 4;
            env->hflags &= ~MIPS_HFLAG_BMASK;
        } else {
            env->CP0_ErrorEPC = env->PC[env->current_tc];
        }
        env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
        if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
            env->hflags |= MIPS_HFLAG_64;
        env->hflags &= ~MIPS_HFLAG_UM;
        if (!(env->CP0_Status & (1 << CP0St_EXL)))
            env->CP0_Cause &= ~(1 << CP0Ca_BD);
        env->PC[env->current_tc] = (int32_t)0xBFC00000;
        break;
    case EXCP_MCHECK:
        cause = 24;
        goto set_EPC;
    case EXCP_EXT_INTERRUPT:
        cause = 0;
        if (env->CP0_Cause & (1 << CP0Ca_IV))
            offset = 0x200;
        goto set_EPC;
    case EXCP_DWATCH:
        cause = 23;
        /* XXX: TODO: manage defered watch exceptions */
        goto set_EPC;
    case EXCP_AdEL:
        cause = 4;
        goto set_EPC;
    case EXCP_AdES:
        cause = 5;
        goto set_EPC;
    case EXCP_TLBL:
        cause = 2;
        if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
#ifdef TARGET_MIPS64
            int R = env->CP0_BadVAddr >> 62;
            int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
            int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
            int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;

            if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
                offset = 0x080;
            else
#endif
                offset = 0x000;
        }
        goto set_EPC;
    case EXCP_IBE:
        cause = 6;
        goto set_EPC;
    case EXCP_DBE:
        cause = 7;
        goto set_EPC;
    case EXCP_SYSCALL:
        cause = 8;
        goto set_EPC;
    case EXCP_BREAK:
        cause = 9;
        goto set_EPC;
    case EXCP_RI:
        cause = 10;
        goto set_EPC;
    case EXCP_CpU:
        cause = 11;
        env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
                         (env->error_code << CP0Ca_CE);
        goto set_EPC;
    case EXCP_OVERFLOW:
        cause = 12;
        goto set_EPC;
    case EXCP_TRAP:
        cause = 13;
        goto set_EPC;
    case EXCP_FPE:
        cause = 15;
        goto set_EPC;
    case EXCP_LTLBL:
        cause = 1;
        goto set_EPC;
    case EXCP_TLBS:
        cause = 3;
        goto set_EPC;
    case EXCP_THREAD:
        cause = 25;
        if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
#ifdef TARGET_MIPS64
            int R = env->CP0_BadVAddr >> 62;
            int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
            int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
            int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;

            if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
                offset = 0x080;
            else
#endif
                offset = 0x000;
        }
    set_EPC:
        if (!(env->CP0_Status & (1 << CP0St_EXL))) {
            if (env->hflags & MIPS_HFLAG_BMASK) {
                /* If the exception was raised from a delay slot,
                   come back to the jump.  */
                env->CP0_EPC = env->PC[env->current_tc] - 4;
                env->CP0_Cause |= (1 << CP0Ca_BD);
            } else {
                env->CP0_EPC = env->PC[env->current_tc];
                env->CP0_Cause &= ~(1 << CP0Ca_BD);
            }
            env->CP0_Status |= (1 << CP0St_EXL);
            if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
                env->hflags |= MIPS_HFLAG_64;
            env->hflags &= ~MIPS_HFLAG_UM;
        }
        env->hflags &= ~MIPS_HFLAG_BMASK;
        if (env->CP0_Status & (1 << CP0St_BEV)) {
            env->PC[env->current_tc] = (int32_t)0xBFC00200;
        } else {
            env->PC[env->current_tc] = (int32_t)(env->CP0_EBase & ~0x3ff);
        }
        env->PC[env->current_tc] += offset;
        env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
        break;
    default:
        if (logfile) {
            fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
                    env->exception_index);
        }
        printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
        exit(1);
    }
    if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
        fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n"
                "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
                __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index,
                env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
                env->CP0_DEPC);
    }
    env->exception_index = EXCP_NONE;
}
#endif /* !defined(CONFIG_USER_ONLY) */

void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
{
    r4k_tlb_t *tlb;
    target_ulong addr;
    target_ulong end;
    uint8_t ASID = env->CP0_EntryHi & 0xFF;
    target_ulong mask;

    tlb = &env->tlb->mmu.r4k.tlb[idx];
    /* The qemu TLB is flushed when the ASID changes, so no need to
       flush these entries again.  */
    if (tlb->G == 0 && tlb->ASID != ASID) {
        return;
    }

    if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
        /* For tlbwr, we can shadow the discarded entry into
	   a new (fake) TLB entry, as long as the guest can not
	   tell that it's there.  */
        env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
        env->tlb->tlb_in_use++;
        return;
    }

    /* 1k pages are not supported. */
    mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
    if (tlb->V0) {
        addr = tlb->VPN & ~mask;
#ifdef TARGET_MIPS64
        if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
            addr |= 0x3FFFFF0000000000ULL;
        }
#endif
        end = addr | (mask >> 1);
        while (addr < end) {
            tlb_flush_page (env, addr);
            addr += TARGET_PAGE_SIZE;
        }
    }
    if (tlb->V1) {
        addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
#ifdef TARGET_MIPS64
        if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
            addr |= 0x3FFFFF0000000000ULL;
        }
#endif
        end = addr | mask;
        while (addr < end) {
            tlb_flush_page (env, addr);
            addr += TARGET_PAGE_SIZE;
        }
    }
}
Commit	Line	Data
6af0bf9c FB	1	/*
6af0bf9c FB	2	* MIPS emulation helpers for qemu.
5fafdf24	3	*
6af0bf9c FB	4	* Copyright (c) 2004-2005 Jocelyn Mayer
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
e37e863f FB	20	#include <stdarg.h>
	21	#include <stdlib.h>
	22	#include <stdio.h>
	23	#include <string.h>
	24	#include <inttypes.h>
	25	#include <signal.h>
	26	#include <assert.h>
	27
	28	#include "cpu.h"
	29	#include "exec-all.h"
6af0bf9c	30
43057ab1 FB	31	enum {
	32	TLBRET_DIRTY = -4,
	33	TLBRET_INVALID = -3,
	34	TLBRET_NOMATCH = -2,
	35	TLBRET_BADADDR = -1,
	36	TLBRET_MATCH = 0
	37	};
	38
29929e34 TS	39	/* no MMU emulation */
29929e34 TS	40	int no_mmu_map_address (CPUState env, target_ulong physical, int *prot,
6af0bf9c	41	target_ulong address, int rw, int access_type)
29929e34 TS	42	{
	43	*physical = address;
	44	*prot = PAGE_READ \| PAGE_WRITE;
	45	return TLBRET_MATCH;
	46	}
	47
	48	/* fixed mapping MMU emulation */
	49	int fixed_mmu_map_address (CPUState env, target_ulong physical, int *prot,
	50	target_ulong address, int rw, int access_type)
	51	{
	52	if (address <= (int32_t)0x7FFFFFFFUL) {
	53	if (!(env->CP0_Status & (1 << CP0St_ERL)))
	54	*physical = address + 0x40000000UL;
	55	else
	56	*physical = address;
	57	} else if (address <= (int32_t)0xBFFFFFFFUL)
	58	*physical = address & 0x1FFFFFFF;
	59	else
	60	*physical = address;
	61
	62	*prot = PAGE_READ \| PAGE_WRITE;
	63	return TLBRET_MATCH;
	64	}
	65
	66	/* MIPS32/MIPS64 R4000-style MMU emulation */
	67	int r4k_map_address (CPUState env, target_ulong physical, int *prot,
	68	target_ulong address, int rw, int access_type)
6af0bf9c	69	{
925fd0f2	70	uint8_t ASID = env->CP0_EntryHi & 0xFF;
3b1c8be4	71	int i;
6af0bf9c	72
ead9360e TS	73	for (i = 0; i < env->tlb->tlb_in_use; i++) {
ead9360e TS	74	r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
3b1c8be4	75	/* 1k pages are not supported. */
f2e9ebef	76	target_ulong mask = tlb->PageMask \| ~(TARGET_PAGE_MASK << 1);
3b1c8be4	77	target_ulong tag = address & ~mask;
f2e9ebef	78	target_ulong VPN = tlb->VPN & ~mask;
100ce988	79	#ifdef TARGET_MIPS64
e034e2c3	80	tag &= env->SEGMask;
100ce988	81	#endif
3b1c8be4	82
6af0bf9c	83	/* Check ASID, virtual page number & size */
f2e9ebef	84	if ((tlb->G == 1 \|\| tlb->ASID == ASID) && VPN == tag) {
6af0bf9c	85	/* TLB match */
f2e9ebef	86	int n = !!(address & mask & ~(mask >> 1));
6af0bf9c	87	/* Check access rights */
f2e9ebef	88	if (!(n ? tlb->V1 : tlb->V0))
43057ab1	89	return TLBRET_INVALID;
f2e9ebef	90	if (rw == 0 \|\| (n ? tlb->D1 : tlb->D0)) {
3b1c8be4	91	*physical = tlb->PFN[n] \| (address & (mask >> 1));
9fb63ac2	92	*prot = PAGE_READ;
98c1b82b	93	if (n ? tlb->D1 : tlb->D0)
9fb63ac2	94	*prot \|= PAGE_WRITE;
43057ab1	95	return TLBRET_MATCH;
6af0bf9c	96	}
43057ab1	97	return TLBRET_DIRTY;
6af0bf9c FB	98	}
6af0bf9c FB	99	}
43057ab1	100	return TLBRET_NOMATCH;
6af0bf9c	101	}
6af0bf9c	102
43057ab1 FB	103	static int get_physical_address (CPUState env, target_ulong physical,
	104	int *prot, target_ulong address,
	105	int rw, int access_type)
6af0bf9c	106	{
b4ab4b4e	107	/* User mode can only access useg/xuseg */
43057ab1	108	int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
b4ab4b4e TS	109	#ifdef TARGET_MIPS64
	110	int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
	111	int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
	112	int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
	113	#endif
43057ab1 FB	114	int ret = TLBRET_MATCH;
43057ab1 FB	115
6af0bf9c FB	116	#if 0
	117	if (logfile) {
	118	fprintf(logfile, "user mode %d h %08x\n",
	119	user_mode, env->hflags);
	120	}
	121	#endif
b4ab4b4e TS	122
	123	#ifdef TARGET_MIPS64
	124	if (user_mode && address > 0x3FFFFFFFFFFFFFFFULL)
	125	return TLBRET_BADADDR;
	126	#else
6af0bf9c	127	if (user_mode && address > 0x7FFFFFFFUL)
43057ab1	128	return TLBRET_BADADDR;
b4ab4b4e TS	129	#endif
	130
	131	if (address <= (int32_t)0x7FFFFFFFUL) {
	132	/* useg */
996ba2cc	133	if (env->CP0_Status & (1 << CP0St_ERL)) {
29929e34	134	*physical = address & 0xFFFFFFFF;
6af0bf9c	135	*prot = PAGE_READ \| PAGE_WRITE;
996ba2cc	136	} else {
ead9360e	137	ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
6af0bf9c	138	}
b4ab4b4e TS	139	#ifdef TARGET_MIPS64
	140	/*
	141	XXX: Assuming :
	142	- PABITS = 36 (correct for MIPS64R1)
b4ab4b4e TS	143	*/
	144	} else if (address < 0x3FFFFFFFFFFFFFFFULL) {
	145	/* xuseg */
e034e2c3	146	if (UX && address < (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
ead9360e	147	ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
b4ab4b4e TS	148	} else {
	149	ret = TLBRET_BADADDR;
	150	}
	151	} else if (address < 0x7FFFFFFFFFFFFFFFULL) {
	152	/* xsseg */
e034e2c3	153	if (SX && address < (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
ead9360e	154	ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
b4ab4b4e TS	155	} else {
	156	ret = TLBRET_BADADDR;
	157	}
	158	} else if (address < 0xBFFFFFFFFFFFFFFFULL) {
	159	/* xkphys */
	160	/* XXX: check supervisor mode */
e034e2c3	161	if (KX && (address & 0x07FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL)
b4ab4b4e	162	{
e034e2c3	163	*physical = address & 0X0000000FFFFFFFFFULL;
b4ab4b4e TS	164	*prot = PAGE_READ \| PAGE_WRITE;
	165	} else {
	166	ret = TLBRET_BADADDR;
	167	}
	168	} else if (address < 0xFFFFFFFF7FFFFFFFULL) {
	169	/* xkseg */
	170	/* XXX: check supervisor mode */
e034e2c3	171	if (KX && address < (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
ead9360e	172	ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
b4ab4b4e TS	173	} else {
	174	ret = TLBRET_BADADDR;
	175	}
	176	#endif
5dc4b744	177	} else if (address < (int32_t)0xA0000000UL) {
6af0bf9c FB	178	/* kseg0 */
6af0bf9c FB	179	/* XXX: check supervisor mode */
5dc4b744	180	*physical = address - (int32_t)0x80000000UL;
6af0bf9c	181	*prot = PAGE_READ \| PAGE_WRITE;
5dc4b744	182	} else if (address < (int32_t)0xC0000000UL) {
6af0bf9c FB	183	/* kseg1 */
6af0bf9c FB	184	/* XXX: check supervisor mode */
5dc4b744	185	*physical = address - (int32_t)0xA0000000UL;
6af0bf9c	186	*prot = PAGE_READ \| PAGE_WRITE;
5dc4b744	187	} else if (address < (int32_t)0xE0000000UL) {
6af0bf9c	188	/* kseg2 */
ead9360e	189	ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
6af0bf9c FB	190	} else {
	191	/* kseg3 */
	192	/* XXX: check supervisor mode */
	193	/* XXX: debug segment is not emulated */
ead9360e	194	ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
6af0bf9c FB	195	}
	196	#if 0
	197	if (logfile) {
3594c774	198	fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
c570fd16	199	address, rw, access_type, physical, prot, ret);
6af0bf9c FB	200	}
	201	#endif
	202
	203	return ret;
	204	}
	205
5fafdf24	206	#if defined(CONFIG_USER_ONLY)
9b3c35e0	207	target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
6af0bf9c FB	208	{
	209	return addr;
	210	}
	211	#else
9b3c35e0	212	target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
6af0bf9c FB	213	{
	214	target_ulong phys_addr;
	215	int prot;
	216
	217	if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
	218	return -1;
	219	return phys_addr;
	220	}
6af0bf9c FB	221
	222	void cpu_mips_init_mmu (CPUState *env)
	223	{
	224	}
6af0bf9c FB	225	#endif /* !defined(CONFIG_USER_ONLY) */
	226
	227	int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
	228	int is_user, int is_softmmu)
	229	{
	230	target_ulong physical;
	231	int prot;
	232	int exception = 0, error_code = 0;
	233	int access_type;
	234	int ret = 0;
	235
	236	if (logfile) {
4ad40f36	237	#if 0
6af0bf9c	238	cpu_dump_state(env, logfile, fprintf, 0);
4ad40f36	239	#endif
3594c774	240	fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n",
ead9360e	241	__func__, env->PC[env->current_tc], address, rw, is_user, is_softmmu);
6af0bf9c	242	}
4ad40f36 FB	243
	244	rw &= 1;
	245
6af0bf9c FB	246	/* data access */
	247	/* XXX: put correct access by using cpu_restore_state()
	248	correctly */
	249	access_type = ACCESS_INT;
	250	if (env->user_mode_only) {
	251	/* user mode only emulation */
43057ab1	252	ret = TLBRET_NOMATCH;
6af0bf9c FB	253	goto do_fault;
	254	}
	255	ret = get_physical_address(env, &physical, &prot,
	256	address, rw, access_type);
	257	if (logfile) {
3594c774	258	fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
6af0bf9c FB	259	__func__, address, ret, physical, prot);
6af0bf9c FB	260	}
43057ab1 FB	261	if (ret == TLBRET_MATCH) {
	262	ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
	263	physical & TARGET_PAGE_MASK, prot,
	264	is_user, is_softmmu);
6af0bf9c FB	265	} else if (ret < 0) {
	266	do_fault:
	267	switch (ret) {
	268	default:
43057ab1	269	case TLBRET_BADADDR:
6af0bf9c FB	270	/* Reference to kernel address from user mode or supervisor mode */
	271	/* Reference to supervisor address from user mode */
	272	if (rw)
	273	exception = EXCP_AdES;
	274	else
	275	exception = EXCP_AdEL;
	276	break;
43057ab1	277	case TLBRET_NOMATCH:
6af0bf9c FB	278	/* No TLB match for a mapped address */
	279	if (rw)
	280	exception = EXCP_TLBS;
	281	else
	282	exception = EXCP_TLBL;
	283	error_code = 1;
	284	break;
43057ab1	285	case TLBRET_INVALID:
6af0bf9c FB	286	/* TLB match with no valid bit */
	287	if (rw)
	288	exception = EXCP_TLBS;
	289	else
	290	exception = EXCP_TLBL;
6af0bf9c	291	break;
43057ab1	292	case TLBRET_DIRTY:
6af0bf9c FB	293	/* TLB match but 'D' bit is cleared */
	294	exception = EXCP_LTLBL;
	295	break;
3b46e624	296
6af0bf9c	297	}
6af0bf9c FB	298	/* Raise exception */
6af0bf9c FB	299	env->CP0_BadVAddr = address;
100ce988	300	env->CP0_Context = (env->CP0_Context & ~0x007fffff) \|
4ad40f36	301	((address >> 9) & 0x007ffff0);
6af0bf9c	302	env->CP0_EntryHi =
43057ab1	303	(env->CP0_EntryHi & 0xFF) \| (address & (TARGET_PAGE_MASK << 1));
100ce988	304	#ifdef TARGET_MIPS64
e034e2c3 TS	305	env->CP0_EntryHi &= env->SEGMask;
	306	env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) \|
	307	((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) \|
	308	((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
100ce988	309	#endif
6af0bf9c FB	310	env->exception_index = exception;
	311	env->error_code = error_code;
	312	ret = 1;
	313	}
	314
	315	return ret;
	316	}
	317
ca7c2b1b TS	318	#if defined(CONFIG_USER_ONLY)
	319	void do_interrupt (CPUState *env)
	320	{
	321	env->exception_index = EXCP_NONE;
	322	}
	323	#else
6af0bf9c FB	324	void do_interrupt (CPUState *env)
6af0bf9c FB	325	{
aa328add	326	target_ulong offset;
6af0bf9c FB	327	int cause = -1;
	328
	329	if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
3594c774	330	fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n",
ead9360e	331	__func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index);
6af0bf9c FB	332	}
	333	if (env->exception_index == EXCP_EXT_INTERRUPT &&
	334	(env->hflags & MIPS_HFLAG_DM))
	335	env->exception_index = EXCP_DINT;
	336	offset = 0x180;
	337	switch (env->exception_index) {
	338	case EXCP_DSS:
	339	env->CP0_Debug \|= 1 << CP0DB_DSS;
	340	/* Debug single step cannot be raised inside a delay slot and
	341	* resume will always occur on the next instruction
	342	* (but we assume the pc has always been updated during
	343	* code translation).
	344	*/
ead9360e	345	env->CP0_DEPC = env->PC[env->current_tc];
6af0bf9c FB	346	goto enter_debug_mode;
	347	case EXCP_DINT:
	348	env->CP0_Debug \|= 1 << CP0DB_DINT;
	349	goto set_DEPC;
	350	case EXCP_DIB:
	351	env->CP0_Debug \|= 1 << CP0DB_DIB;
	352	goto set_DEPC;
	353	case EXCP_DBp:
	354	env->CP0_Debug \|= 1 << CP0DB_DBp;
	355	goto set_DEPC;
	356	case EXCP_DDBS:
	357	env->CP0_Debug \|= 1 << CP0DB_DDBS;
	358	goto set_DEPC;
	359	case EXCP_DDBL:
	360	env->CP0_Debug \|= 1 << CP0DB_DDBL;
6af0bf9c	361	set_DEPC:
4ad40f36	362	if (env->hflags & MIPS_HFLAG_BMASK) {
6af0bf9c	363	/* If the exception was raised from a delay slot,
aa328add	364	come back to the jump. */
ead9360e	365	env->CP0_DEPC = env->PC[env->current_tc] - 4;
4ad40f36	366	env->hflags &= ~MIPS_HFLAG_BMASK;
6af0bf9c	367	} else {
ead9360e	368	env->CP0_DEPC = env->PC[env->current_tc];
6af0bf9c FB	369	}
	370	enter_debug_mode:
	371	env->hflags \|= MIPS_HFLAG_DM;
3ddf0b5c TS	372	if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
3ddf0b5c TS	373	env->hflags \|= MIPS_HFLAG_64;
24c7b0e3	374	env->hflags &= ~MIPS_HFLAG_UM;
6af0bf9c	375	/* EJTAG probe trap enable is not implemented... */
0a6de750 TS	376	if (!(env->CP0_Status & (1 << CP0St_EXL)))
0a6de750 TS	377	env->CP0_Cause &= ~(1 << CP0Ca_BD);
ead9360e	378	env->PC[env->current_tc] = (int32_t)0xBFC00480;
6af0bf9c FB	379	break;
6af0bf9c FB	380	case EXCP_RESET:
aa328add TS	381	cpu_reset(env);
aa328add TS	382	break;
6af0bf9c	383	case EXCP_SRESET:
24c7b0e3	384	env->CP0_Status \|= (1 << CP0St_SR);
fd88b6ab	385	memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
6af0bf9c FB	386	goto set_error_EPC;
6af0bf9c FB	387	case EXCP_NMI:
24c7b0e3	388	env->CP0_Status \|= (1 << CP0St_NMI);
6af0bf9c	389	set_error_EPC:
4ad40f36	390	if (env->hflags & MIPS_HFLAG_BMASK) {
6af0bf9c	391	/* If the exception was raised from a delay slot,
aa328add	392	come back to the jump. */
ead9360e	393	env->CP0_ErrorEPC = env->PC[env->current_tc] - 4;
ecd78a0a	394	env->hflags &= ~MIPS_HFLAG_BMASK;
6af0bf9c	395	} else {
ead9360e	396	env->CP0_ErrorEPC = env->PC[env->current_tc];
6af0bf9c	397	}
24c7b0e3	398	env->CP0_Status \|= (1 << CP0St_ERL) \| (1 << CP0St_BEV);
3ddf0b5c TS	399	if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
3ddf0b5c TS	400	env->hflags \|= MIPS_HFLAG_64;
24c7b0e3	401	env->hflags &= ~MIPS_HFLAG_UM;
0a6de750 TS	402	if (!(env->CP0_Status & (1 << CP0St_EXL)))
0a6de750 TS	403	env->CP0_Cause &= ~(1 << CP0Ca_BD);
ead9360e	404	env->PC[env->current_tc] = (int32_t)0xBFC00000;
6af0bf9c FB	405	break;
	406	case EXCP_MCHECK:
	407	cause = 24;
	408	goto set_EPC;
	409	case EXCP_EXT_INTERRUPT:
	410	cause = 0;
	411	if (env->CP0_Cause & (1 << CP0Ca_IV))
	412	offset = 0x200;
	413	goto set_EPC;
	414	case EXCP_DWATCH:
	415	cause = 23;
	416	/* XXX: TODO: manage defered watch exceptions */
	417	goto set_EPC;
	418	case EXCP_AdEL:
6af0bf9c FB	419	cause = 4;
6af0bf9c FB	420	goto set_EPC;
beb811bd TS	421	case EXCP_AdES:
	422	cause = 5;
	423	goto set_EPC;
6af0bf9c	424	case EXCP_TLBL:
6af0bf9c	425	cause = 2;
100ce988 TS	426	if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
	427	#ifdef TARGET_MIPS64
	428	int R = env->CP0_BadVAddr >> 62;
	429	int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
	430	int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
	431	int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
	432
	433	if ((R == 0 && UX) \|\| (R == 1 && SX) \|\| (R == 3 && KX))
	434	offset = 0x080;
	435	else
	436	#endif
	437	offset = 0x000;
	438	}
6af0bf9c FB	439	goto set_EPC;
	440	case EXCP_IBE:
	441	cause = 6;
	442	goto set_EPC;
	443	case EXCP_DBE:
	444	cause = 7;
	445	goto set_EPC;
	446	case EXCP_SYSCALL:
	447	cause = 8;
	448	goto set_EPC;
	449	case EXCP_BREAK:
	450	cause = 9;
	451	goto set_EPC;
	452	case EXCP_RI:
	453	cause = 10;
	454	goto set_EPC;
	455	case EXCP_CpU:
	456	cause = 11;
39d51eb8 TS	457	env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) \|
39d51eb8 TS	458	(env->error_code << CP0Ca_CE);
6af0bf9c FB	459	goto set_EPC;
	460	case EXCP_OVERFLOW:
	461	cause = 12;
	462	goto set_EPC;
	463	case EXCP_TRAP:
	464	cause = 13;
	465	goto set_EPC;
5a5012ec TS	466	case EXCP_FPE:
	467	cause = 15;
	468	goto set_EPC;
6af0bf9c FB	469	case EXCP_LTLBL:
	470	cause = 1;
	471	goto set_EPC;
	472	case EXCP_TLBS:
	473	cause = 3;
ead9360e TS	474	goto set_EPC;
	475	case EXCP_THREAD:
	476	cause = 25;
100ce988 TS	477	if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
	478	#ifdef TARGET_MIPS64
	479	int R = env->CP0_BadVAddr >> 62;
	480	int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
	481	int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
	482	int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
	483
	484	if ((R == 0 && UX) \|\| (R == 1 && SX) \|\| (R == 3 && KX))
	485	offset = 0x080;
	486	else
	487	#endif
	488	offset = 0x000;
	489	}
6af0bf9c	490	set_EPC:
24c7b0e3 TS	491	if (!(env->CP0_Status & (1 << CP0St_EXL))) {
	492	if (env->hflags & MIPS_HFLAG_BMASK) {
	493	/* If the exception was raised from a delay slot,
	494	come back to the jump. */
ead9360e	495	env->CP0_EPC = env->PC[env->current_tc] - 4;
39d51eb8	496	env->CP0_Cause \|= (1 << CP0Ca_BD);
24c7b0e3	497	} else {
ead9360e	498	env->CP0_EPC = env->PC[env->current_tc];
24c7b0e3 TS	499	env->CP0_Cause &= ~(1 << CP0Ca_BD);
24c7b0e3 TS	500	}
24c7b0e3	501	env->CP0_Status \|= (1 << CP0St_EXL);
3ddf0b5c TS	502	if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
3ddf0b5c TS	503	env->hflags \|= MIPS_HFLAG_64;
24c7b0e3	504	env->hflags &= ~MIPS_HFLAG_UM;
6af0bf9c	505	}
c53f4a62	506	env->hflags &= ~MIPS_HFLAG_BMASK;
aa328add	507	if (env->CP0_Status & (1 << CP0St_BEV)) {
ead9360e	508	env->PC[env->current_tc] = (int32_t)0xBFC00200;
aa328add	509	} else {
ead9360e	510	env->PC[env->current_tc] = (int32_t)(env->CP0_EBase & ~0x3ff);
aa328add	511	}
ead9360e	512	env->PC[env->current_tc] += offset;
e58c8ba5	513	env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) \| (cause << CP0Ca_EC);
6af0bf9c FB	514	break;
	515	default:
	516	if (logfile) {
	517	fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
	518	env->exception_index);
	519	}
	520	printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
	521	exit(1);
	522	}
6af0bf9c	523	if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
3594c774 TS	524	fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n"
3594c774 TS	525	" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
ead9360e	526	__func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index,
6af0bf9c FB	527	env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
	528	env->CP0_DEPC);
	529	}
	530	env->exception_index = EXCP_NONE;
	531	}
ca7c2b1b	532	#endif /* !defined(CONFIG_USER_ONLY) */
2ee4aed8	533
29929e34	534	void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
2ee4aed8	535	{
29929e34	536	r4k_tlb_t *tlb;
3b1c8be4 TS	537	target_ulong addr;
	538	target_ulong end;
	539	uint8_t ASID = env->CP0_EntryHi & 0xFF;
	540	target_ulong mask;
2ee4aed8	541
ead9360e	542	tlb = &env->tlb->mmu.r4k.tlb[idx];
f2e9ebef	543	/* The qemu TLB is flushed when the ASID changes, so no need to
2ee4aed8 FB	544	flush these entries again. */
	545	if (tlb->G == 0 && tlb->ASID != ASID) {
	546	return;
	547	}
	548
ead9360e	549	if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
2ee4aed8 FB	550	/* For tlbwr, we can shadow the discarded entry into
	551	a new (fake) TLB entry, as long as the guest can not
	552	tell that it's there. */
ead9360e TS	553	env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
ead9360e TS	554	env->tlb->tlb_in_use++;
2ee4aed8 FB	555	return;
	556	}
	557
3b1c8be4	558	/* 1k pages are not supported. */
f2e9ebef	559	mask = tlb->PageMask \| ~(TARGET_PAGE_MASK << 1);
3b1c8be4	560	if (tlb->V0) {
f2e9ebef	561	addr = tlb->VPN & ~mask;
100ce988	562	#ifdef TARGET_MIPS64
e034e2c3	563	if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
100ce988 TS	564	addr \|= 0x3FFFFF0000000000ULL;
	565	}
	566	#endif
3b1c8be4 TS	567	end = addr \| (mask >> 1);
	568	while (addr < end) {
	569	tlb_flush_page (env, addr);
	570	addr += TARGET_PAGE_SIZE;
	571	}
	572	}
	573	if (tlb->V1) {
f2e9ebef	574	addr = (tlb->VPN & ~mask) \| ((mask >> 1) + 1);
100ce988	575	#ifdef TARGET_MIPS64
e034e2c3	576	if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
100ce988 TS	577	addr \|= 0x3FFFFF0000000000ULL;
	578	}
	579	#endif
3b1c8be4 TS	580	end = addr \| mask;
	581	while (addr < end) {
	582	tlb_flush_page (env, addr);
	583	addr += TARGET_PAGE_SIZE;
	584	}
	585	}
2ee4aed8	586	}