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25ebd80f AF |
1 | /* |
2 | * QEMU Alpha CPU | |
3 | * | |
9444006f | 4 | * Copyright (c) 2007 Jocelyn Mayer |
25ebd80f AF |
5 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2.1 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see | |
19 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
20 | */ | |
21 | ||
e2e5e114 | 22 | #include "qemu/osdep.h" |
da34e65c | 23 | #include "qapi/error.h" |
0442428a | 24 | #include "qemu/qemu-print.h" |
3993c6bd | 25 | #include "cpu.h" |
63c91552 | 26 | #include "exec/exec-all.h" |
25ebd80f AF |
27 | |
28 | ||
f45748f1 AF |
29 | static void alpha_cpu_set_pc(CPUState *cs, vaddr value) |
30 | { | |
31 | AlphaCPU *cpu = ALPHA_CPU(cs); | |
32 | ||
33 | cpu->env.pc = value; | |
34 | } | |
35 | ||
e4fdf9df RH |
36 | static vaddr alpha_cpu_get_pc(CPUState *cs) |
37 | { | |
38 | AlphaCPU *cpu = ALPHA_CPU(cs); | |
39 | ||
40 | return cpu->env.pc; | |
41 | } | |
42 | ||
c0cd068f RH |
43 | static void alpha_restore_state_to_opc(CPUState *cs, |
44 | const TranslationBlock *tb, | |
45 | const uint64_t *data) | |
46 | { | |
47 | AlphaCPU *cpu = ALPHA_CPU(cs); | |
48 | ||
49 | cpu->env.pc = data[0]; | |
50 | } | |
e4fdf9df | 51 | |
8c2e1b00 AF |
52 | static bool alpha_cpu_has_work(CPUState *cs) |
53 | { | |
54 | /* Here we are checking to see if the CPU should wake up from HALT. | |
55 | We will have gotten into this state only for WTINT from PALmode. */ | |
56 | /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU | |
57 | asleep even if (some) interrupts have been asserted. For now, | |
58 | assume that if a CPU really wants to stay asleep, it will mask | |
59 | interrupts at the chipset level, which will prevent these bits | |
60 | from being set in the first place. */ | |
61 | return cs->interrupt_request & (CPU_INTERRUPT_HARD | |
62 | | CPU_INTERRUPT_TIMER | |
63 | | CPU_INTERRUPT_SMP | |
64 | | CPU_INTERRUPT_MCHK); | |
65 | } | |
66 | ||
0960be7c PC |
67 | static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) |
68 | { | |
69 | info->mach = bfd_mach_alpha_ev6; | |
70 | info->print_insn = print_insn_alpha; | |
71 | } | |
72 | ||
bd1b2828 | 73 | static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) |
0c28246f | 74 | { |
14a10fc3 | 75 | CPUState *cs = CPU(dev); |
bd1b2828 | 76 | AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev); |
ce5b1bbf LV |
77 | Error *local_err = NULL; |
78 | ||
79 | cpu_exec_realizefn(cs, &local_err); | |
80 | if (local_err != NULL) { | |
81 | error_propagate(errp, local_err); | |
82 | return; | |
83 | } | |
0c28246f | 84 | |
14a10fc3 AF |
85 | qemu_init_vcpu(cs); |
86 | ||
bd1b2828 | 87 | acc->parent_realize(dev, errp); |
0c28246f AF |
88 | } |
89 | ||
90 | /* Models */ | |
0c28246f AF |
91 | typedef struct AlphaCPUAlias { |
92 | const char *alias; | |
93 | const char *typename; | |
94 | } AlphaCPUAlias; | |
95 | ||
96 | static const AlphaCPUAlias alpha_cpu_aliases[] = { | |
73a25e83 IM |
97 | { "21064", ALPHA_CPU_TYPE_NAME("ev4") }, |
98 | { "21164", ALPHA_CPU_TYPE_NAME("ev5") }, | |
99 | { "21164a", ALPHA_CPU_TYPE_NAME("ev56") }, | |
100 | { "21164pc", ALPHA_CPU_TYPE_NAME("pca56") }, | |
101 | { "21264", ALPHA_CPU_TYPE_NAME("ev6") }, | |
102 | { "21264a", ALPHA_CPU_TYPE_NAME("ev67") }, | |
0c28246f AF |
103 | }; |
104 | ||
105 | static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model) | |
106 | { | |
8301ea44 | 107 | ObjectClass *oc; |
0c28246f AF |
108 | char *typename; |
109 | int i; | |
110 | ||
0c28246f | 111 | oc = object_class_by_name(cpu_model); |
3a9d0d7b | 112 | if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL) { |
0c28246f AF |
113 | return oc; |
114 | } | |
115 | ||
116 | for (i = 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) { | |
117 | if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) == 0) { | |
118 | oc = object_class_by_name(alpha_cpu_aliases[i].typename); | |
a120c287 | 119 | assert(oc != NULL && !object_class_is_abstract(oc)); |
0c28246f AF |
120 | return oc; |
121 | } | |
122 | } | |
123 | ||
73a25e83 | 124 | typename = g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model); |
0c28246f AF |
125 | oc = object_class_by_name(typename); |
126 | g_free(typename); | |
bd1b2828 | 127 | |
82a3d1f8 | 128 | return oc; |
0c28246f AF |
129 | } |
130 | ||
131 | static void ev4_cpu_initfn(Object *obj) | |
132 | { | |
133 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
134 | CPUAlphaState *env = &cpu->env; | |
135 | ||
136 | env->implver = IMPLVER_2106x; | |
137 | } | |
138 | ||
0c28246f AF |
139 | static void ev5_cpu_initfn(Object *obj) |
140 | { | |
141 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
142 | CPUAlphaState *env = &cpu->env; | |
143 | ||
144 | env->implver = IMPLVER_21164; | |
145 | } | |
146 | ||
0c28246f AF |
147 | static void ev56_cpu_initfn(Object *obj) |
148 | { | |
149 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
150 | CPUAlphaState *env = &cpu->env; | |
151 | ||
152 | env->amask |= AMASK_BWX; | |
153 | } | |
154 | ||
0c28246f AF |
155 | static void pca56_cpu_initfn(Object *obj) |
156 | { | |
157 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
158 | CPUAlphaState *env = &cpu->env; | |
159 | ||
160 | env->amask |= AMASK_MVI; | |
161 | } | |
162 | ||
0c28246f AF |
163 | static void ev6_cpu_initfn(Object *obj) |
164 | { | |
165 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
166 | CPUAlphaState *env = &cpu->env; | |
167 | ||
168 | env->implver = IMPLVER_21264; | |
169 | env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP; | |
170 | } | |
171 | ||
0c28246f AF |
172 | static void ev67_cpu_initfn(Object *obj) |
173 | { | |
174 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
175 | CPUAlphaState *env = &cpu->env; | |
176 | ||
177 | env->amask |= AMASK_CIX | AMASK_PREFETCH; | |
178 | } | |
179 | ||
9444006f AF |
180 | static void alpha_cpu_initfn(Object *obj) |
181 | { | |
182 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
183 | CPUAlphaState *env = &cpu->env; | |
184 | ||
bcd2625d | 185 | env->lock_addr = -1; |
9444006f | 186 | #if defined(CONFIG_USER_ONLY) |
bcd2625d | 187 | env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN; |
29eb5280 RH |
188 | cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD |
189 | | FPCR_UNFD | FPCR_INED | FPCR_DNOD | |
190 | | FPCR_DYN_NORMAL) << 32); | |
bcd2625d RH |
191 | #else |
192 | env->flags = ENV_FLAG_PAL_MODE | ENV_FLAG_FEN; | |
9444006f | 193 | #endif |
9444006f AF |
194 | } |
195 | ||
8b80bd28 PMD |
196 | #ifndef CONFIG_USER_ONLY |
197 | #include "hw/core/sysemu-cpu-ops.h" | |
198 | ||
199 | static const struct SysemuCPUOps alpha_sysemu_ops = { | |
08928c6d | 200 | .get_phys_page_debug = alpha_cpu_get_phys_page_debug, |
8b80bd28 PMD |
201 | }; |
202 | #endif | |
203 | ||
78271684 CF |
204 | #include "hw/core/tcg-cpu-ops.h" |
205 | ||
1764ad70 | 206 | static const TCGCPUOps alpha_tcg_ops = { |
78271684 | 207 | .initialize = alpha_translate_init, |
c0cd068f | 208 | .restore_state_to_opc = alpha_restore_state_to_opc, |
78271684 | 209 | |
90113883 RH |
210 | #ifdef CONFIG_USER_ONLY |
211 | .record_sigsegv = alpha_cpu_record_sigsegv, | |
e7424abc | 212 | .record_sigbus = alpha_cpu_record_sigbus, |
90113883 RH |
213 | #else |
214 | .tlb_fill = alpha_cpu_tlb_fill, | |
9354e694 | 215 | .cpu_exec_interrupt = alpha_cpu_exec_interrupt, |
78271684 CF |
216 | .do_interrupt = alpha_cpu_do_interrupt, |
217 | .do_transaction_failed = alpha_cpu_do_transaction_failed, | |
218 | .do_unaligned_access = alpha_cpu_do_unaligned_access, | |
219 | #endif /* !CONFIG_USER_ONLY */ | |
220 | }; | |
221 | ||
2b8c2754 AF |
222 | static void alpha_cpu_class_init(ObjectClass *oc, void *data) |
223 | { | |
bd1b2828 | 224 | DeviceClass *dc = DEVICE_CLASS(oc); |
2b8c2754 | 225 | CPUClass *cc = CPU_CLASS(oc); |
bd1b2828 AF |
226 | AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc); |
227 | ||
bf853881 PMD |
228 | device_class_set_parent_realize(dc, alpha_cpu_realizefn, |
229 | &acc->parent_realize); | |
2b8c2754 AF |
230 | |
231 | cc->class_by_name = alpha_cpu_class_by_name; | |
8c2e1b00 | 232 | cc->has_work = alpha_cpu_has_work; |
878096ee | 233 | cc->dump_state = alpha_cpu_dump_state; |
f45748f1 | 234 | cc->set_pc = alpha_cpu_set_pc; |
e4fdf9df | 235 | cc->get_pc = alpha_cpu_get_pc; |
5b50e790 AF |
236 | cc->gdb_read_register = alpha_cpu_gdb_read_register; |
237 | cc->gdb_write_register = alpha_cpu_gdb_write_register; | |
e41c9452 | 238 | #ifndef CONFIG_USER_ONLY |
00b941e5 | 239 | dc->vmsd = &vmstate_alpha_cpu; |
8b80bd28 | 240 | cc->sysemu_ops = &alpha_sysemu_ops; |
00b941e5 | 241 | #endif |
0960be7c PC |
242 | cc->disas_set_info = alpha_cpu_disas_set_info; |
243 | ||
78271684 | 244 | cc->tcg_ops = &alpha_tcg_ops; |
a0e372f0 | 245 | cc->gdb_num_core_regs = 67; |
2b8c2754 AF |
246 | } |
247 | ||
73a25e83 IM |
248 | #define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \ |
249 | { \ | |
250 | .parent = base_type, \ | |
251 | .instance_init = initfn, \ | |
252 | .name = ALPHA_CPU_TYPE_NAME(cpu_model), \ | |
253 | } | |
254 | ||
255 | static const TypeInfo alpha_cpu_type_infos[] = { | |
256 | { | |
257 | .name = TYPE_ALPHA_CPU, | |
258 | .parent = TYPE_CPU, | |
259 | .instance_size = sizeof(AlphaCPU), | |
f669c992 | 260 | .instance_align = __alignof(AlphaCPU), |
73a25e83 IM |
261 | .instance_init = alpha_cpu_initfn, |
262 | .abstract = true, | |
263 | .class_size = sizeof(AlphaCPUClass), | |
264 | .class_init = alpha_cpu_class_init, | |
265 | }, | |
266 | DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev4", ev4_cpu_initfn), | |
267 | DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev5", ev5_cpu_initfn), | |
268 | DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev5"), "ev56", ev56_cpu_initfn), | |
269 | DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev56"), "pca56", | |
270 | pca56_cpu_initfn), | |
271 | DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev6", ev6_cpu_initfn), | |
272 | DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev6"), "ev67", ev67_cpu_initfn), | |
273 | DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev67"), "ev68", NULL), | |
25ebd80f AF |
274 | }; |
275 | ||
73a25e83 | 276 | DEFINE_TYPES(alpha_cpu_type_infos) |