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61766fe9 RH |
1 | /* |
2 | * PA-RISC emulation cpu definitions for qemu. | |
3 | * | |
4 | * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef HPPA_CPU_H | |
21 | #define HPPA_CPU_H | |
22 | ||
61766fe9 | 23 | #include "cpu-qom.h" |
74433bf0 | 24 | #include "exec/cpu-defs.h" |
61766fe9 | 25 | |
61766fe9 | 26 | |
7b93dab5 RH |
27 | /* PA-RISC 1.x processors have a strong memory model. */ |
28 | /* ??? While we do not yet implement PA-RISC 2.0, those processors have | |
29 | a weak memory model, but with TLB bits that force ordering on a per-page | |
30 | basis. It's probably easier to fall back to a strong memory model. */ | |
31 | #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL | |
32 | ||
61766fe9 | 33 | #define ALIGNED_ONLY |
3d68ee7b RH |
34 | #define MMU_KERNEL_IDX 0 |
35 | #define MMU_USER_IDX 3 | |
36 | #define MMU_PHYS_IDX 4 | |
61766fe9 RH |
37 | #define TARGET_INSN_START_EXTRA_WORDS 1 |
38 | ||
2986721d RH |
39 | /* Hardware exceptions, interupts, faults, and traps. */ |
40 | #define EXCP_HPMC 1 /* high priority machine check */ | |
41 | #define EXCP_POWER_FAIL 2 | |
42 | #define EXCP_RC 3 /* recovery counter */ | |
43 | #define EXCP_EXT_INTERRUPT 4 /* external interrupt */ | |
44 | #define EXCP_LPMC 5 /* low priority machine check */ | |
45 | #define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */ | |
46 | #define EXCP_IMP 7 /* instruction memory protection trap */ | |
47 | #define EXCP_ILL 8 /* illegal instruction trap */ | |
48 | #define EXCP_BREAK 9 /* break instruction */ | |
49 | #define EXCP_PRIV_OPR 10 /* privileged operation trap */ | |
50 | #define EXCP_PRIV_REG 11 /* privileged register trap */ | |
51 | #define EXCP_OVERFLOW 12 /* signed overflow trap */ | |
52 | #define EXCP_COND 13 /* trap-on-condition */ | |
53 | #define EXCP_ASSIST 14 /* assist exception trap */ | |
54 | #define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */ | |
55 | #define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */ | |
56 | #define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */ | |
57 | #define EXCP_DMP 18 /* data memory protection trap */ | |
58 | #define EXCP_DMB 19 /* data memory break trap */ | |
59 | #define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */ | |
60 | #define EXCP_PAGE_REF 21 /* page reference trap */ | |
61 | #define EXCP_ASSIST_EMU 22 /* assist emulation trap */ | |
62 | #define EXCP_HPT 23 /* high-privilege transfer trap */ | |
63 | #define EXCP_LPT 24 /* low-privilege transfer trap */ | |
64 | #define EXCP_TB 25 /* taken branch trap */ | |
65 | #define EXCP_DMAR 26 /* data memory access rights trap */ | |
66 | #define EXCP_DMPI 27 /* data memory protection id trap */ | |
67 | #define EXCP_UNALIGN 28 /* unaligned data reference trap */ | |
68 | #define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */ | |
69 | ||
70 | /* Exceptions for linux-user emulation. */ | |
71 | #define EXCP_SYSCALL 30 | |
72 | #define EXCP_SYSCALL_LWS 31 | |
61766fe9 | 73 | |
fa57e327 RH |
74 | /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ |
75 | #define PSW_I 0x00000001 | |
76 | #define PSW_D 0x00000002 | |
77 | #define PSW_P 0x00000004 | |
78 | #define PSW_Q 0x00000008 | |
79 | #define PSW_R 0x00000010 | |
80 | #define PSW_F 0x00000020 | |
81 | #define PSW_G 0x00000040 /* PA1.x only */ | |
82 | #define PSW_O 0x00000080 /* PA2.0 only */ | |
83 | #define PSW_CB 0x0000ff00 | |
84 | #define PSW_M 0x00010000 | |
85 | #define PSW_V 0x00020000 | |
86 | #define PSW_C 0x00040000 | |
87 | #define PSW_B 0x00080000 | |
88 | #define PSW_X 0x00100000 | |
89 | #define PSW_N 0x00200000 | |
90 | #define PSW_L 0x00400000 | |
91 | #define PSW_H 0x00800000 | |
92 | #define PSW_T 0x01000000 | |
93 | #define PSW_S 0x02000000 | |
94 | #define PSW_E 0x04000000 | |
95 | #ifdef TARGET_HPPA64 | |
96 | #define PSW_W 0x08000000 /* PA2.0 only */ | |
97 | #else | |
98 | #define PSW_W 0 | |
99 | #endif | |
100 | #define PSW_Z 0x40000000 /* PA1.x only */ | |
101 | #define PSW_Y 0x80000000 /* PA1.x only */ | |
102 | ||
103 | #define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \ | |
104 | | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I) | |
105 | ||
106 | /* ssm/rsm instructions number PSW_W and PSW_E differently */ | |
107 | #define PSW_SM_I PSW_I /* Enable External Interrupts */ | |
108 | #define PSW_SM_D PSW_D | |
109 | #define PSW_SM_P PSW_P | |
110 | #define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */ | |
111 | #define PSW_SM_R PSW_R /* Enable Recover Counter Trap */ | |
112 | #ifdef TARGET_HPPA64 | |
113 | #define PSW_SM_E 0x100 | |
114 | #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ | |
115 | #else | |
116 | #define PSW_SM_E 0 | |
117 | #define PSW_SM_W 0 | |
118 | #endif | |
119 | ||
35136a77 | 120 | #define CR_RC 0 |
d5de20bd SS |
121 | #define CR_PID1 8 |
122 | #define CR_PID2 9 | |
123 | #define CR_PID3 12 | |
124 | #define CR_PID4 13 | |
35136a77 RH |
125 | #define CR_SCRCCR 10 |
126 | #define CR_SAR 11 | |
127 | #define CR_IVA 14 | |
128 | #define CR_EIEM 15 | |
129 | #define CR_IT 16 | |
130 | #define CR_IIASQ 17 | |
131 | #define CR_IIAOQ 18 | |
132 | #define CR_IIR 19 | |
133 | #define CR_ISR 20 | |
134 | #define CR_IOR 21 | |
135 | #define CR_IPSW 22 | |
136 | #define CR_EIRR 23 | |
137 | ||
61766fe9 RH |
138 | typedef struct CPUHPPAState CPUHPPAState; |
139 | ||
eaa3783b RH |
140 | #if TARGET_REGISTER_BITS == 32 |
141 | typedef uint32_t target_ureg; | |
142 | typedef int32_t target_sreg; | |
143 | #define TREG_FMT_lx "%08"PRIx32 | |
144 | #define TREG_FMT_ld "%"PRId32 | |
145 | #else | |
146 | typedef uint64_t target_ureg; | |
147 | typedef int64_t target_sreg; | |
148 | #define TREG_FMT_lx "%016"PRIx64 | |
149 | #define TREG_FMT_ld "%"PRId64 | |
150 | #endif | |
151 | ||
650cdb2a RH |
152 | typedef struct { |
153 | uint64_t va_b; | |
154 | uint64_t va_e; | |
155 | target_ureg pa; | |
156 | unsigned u : 1; | |
157 | unsigned t : 1; | |
158 | unsigned d : 1; | |
159 | unsigned b : 1; | |
160 | unsigned page_size : 4; | |
161 | unsigned ar_type : 3; | |
162 | unsigned ar_pl1 : 2; | |
163 | unsigned ar_pl2 : 2; | |
164 | unsigned entry_valid : 1; | |
165 | unsigned access_id : 16; | |
166 | } hppa_tlb_entry; | |
167 | ||
61766fe9 | 168 | struct CPUHPPAState { |
eaa3783b | 169 | target_ureg gr[32]; |
61766fe9 | 170 | uint64_t fr[32]; |
33423472 | 171 | uint64_t sr[8]; /* stored shifted into place for gva */ |
61766fe9 | 172 | |
eaa3783b RH |
173 | target_ureg psw; /* All psw bits except the following: */ |
174 | target_ureg psw_n; /* boolean */ | |
175 | target_sreg psw_v; /* in most significant bit */ | |
61766fe9 RH |
176 | |
177 | /* Splitting the carry-borrow field into the MSB and "the rest", allows | |
178 | * for "the rest" to be deleted when it is unused, but the MSB is in use. | |
179 | * In addition, it's easier to compute carry-in for bit B+1 than it is to | |
180 | * compute carry-out for bit B (3 vs 4 insns for addition, assuming the | |
181 | * host has the appropriate add-with-carry insn to compute the msb). | |
182 | * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110. | |
183 | */ | |
eaa3783b RH |
184 | target_ureg psw_cb; /* in least significant bit of next nibble */ |
185 | target_ureg psw_cb_msb; /* boolean */ | |
61766fe9 | 186 | |
eaa3783b RH |
187 | target_ureg iaoq_f; /* front */ |
188 | target_ureg iaoq_b; /* back, aka next instruction */ | |
c301f34e RH |
189 | uint64_t iasq_f; |
190 | uint64_t iasq_b; | |
61766fe9 | 191 | |
61766fe9 RH |
192 | uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ |
193 | float_status fp_status; | |
194 | ||
35136a77 RH |
195 | target_ureg cr[32]; /* control registers */ |
196 | target_ureg cr_back[2]; /* back of cr17/cr18 */ | |
f49b3537 | 197 | target_ureg shadow[7]; /* shadow registers */ |
35136a77 | 198 | |
650cdb2a RH |
199 | /* ??? The number of entries isn't specified by the architecture. */ |
200 | /* ??? Implement a unified itlb/dtlb for the moment. */ | |
201 | /* ??? We should use a more intelligent data structure. */ | |
202 | hppa_tlb_entry tlb[256]; | |
203 | uint32_t tlb_last; | |
61766fe9 RH |
204 | }; |
205 | ||
206 | /** | |
207 | * HPPACPU: | |
208 | * @env: #CPUHPPAState | |
209 | * | |
210 | * An HPPA CPU. | |
211 | */ | |
212 | struct HPPACPU { | |
213 | /*< private >*/ | |
214 | CPUState parent_obj; | |
215 | /*< public >*/ | |
216 | ||
5b146dc7 | 217 | CPUNegativeOffsetState neg; |
61766fe9 | 218 | CPUHPPAState env; |
49c29d6c | 219 | QEMUTimer *alarm_timer; |
61766fe9 RH |
220 | }; |
221 | ||
61766fe9 | 222 | |
4f7c64b3 | 223 | typedef CPUHPPAState CPUArchState; |
2161a612 | 224 | typedef HPPACPU ArchCPU; |
4f7c64b3 | 225 | |
61766fe9 RH |
226 | #include "exec/cpu-all.h" |
227 | ||
228 | static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) | |
229 | { | |
3d68ee7b RH |
230 | #ifdef CONFIG_USER_ONLY |
231 | return MMU_USER_IDX; | |
232 | #else | |
233 | if (env->psw & (ifetch ? PSW_C : PSW_D)) { | |
234 | return env->iaoq_f & 3; | |
235 | } | |
236 | return MMU_PHYS_IDX; /* mmu disabled */ | |
237 | #endif | |
61766fe9 RH |
238 | } |
239 | ||
240 | void hppa_translate_init(void); | |
241 | ||
0dacec87 | 242 | #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU |
61766fe9 | 243 | |
c301f34e RH |
244 | static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc, |
245 | target_ureg off) | |
246 | { | |
247 | #ifdef CONFIG_USER_ONLY | |
248 | return off; | |
249 | #else | |
250 | off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull); | |
251 | return spc | off; | |
252 | #endif | |
253 | } | |
254 | ||
255 | static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, | |
256 | target_ureg off) | |
257 | { | |
258 | return hppa_form_gva_psw(env->psw, spc, off); | |
259 | } | |
260 | ||
494737b7 RH |
261 | /* Since PSW_{I,CB} will never need to be in tb->flags, reuse them. |
262 | * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the | |
263 | * same value. | |
264 | */ | |
265 | #define TB_FLAG_SR_SAME PSW_I | |
c301f34e RH |
266 | #define TB_FLAG_PRIV_SHIFT 8 |
267 | ||
61766fe9 RH |
268 | static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, |
269 | target_ulong *cs_base, | |
270 | uint32_t *pflags) | |
271 | { | |
c301f34e RH |
272 | uint32_t flags = env->psw_n * PSW_N; |
273 | ||
274 | /* TB lookup assumes that PC contains the complete virtual address. | |
275 | If we leave space+offset separate, we'll get ITLB misses to an | |
276 | incomplete virtual address. This also means that we must separate | |
277 | out current cpu priviledge from the low bits of IAOQ_F. */ | |
278 | #ifdef CONFIG_USER_ONLY | |
ebd0e151 RH |
279 | *pc = env->iaoq_f & -4; |
280 | *cs_base = env->iaoq_b & -4; | |
c301f34e | 281 | #else |
3d68ee7b | 282 | /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ |
c301f34e RH |
283 | flags |= env->psw & (PSW_W | PSW_C | PSW_D); |
284 | flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; | |
285 | ||
286 | *pc = (env->psw & PSW_C | |
287 | ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) | |
288 | : env->iaoq_f & -4); | |
289 | *cs_base = env->iasq_f; | |
290 | ||
291 | /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero | |
292 | low 32-bits of CS_BASE. This will succeed for all direct branches, | |
293 | which is the primary case we care about -- using goto_tb within a page. | |
294 | Failure is indicated by a zero difference. */ | |
295 | if (env->iasq_f == env->iasq_b) { | |
296 | target_sreg diff = env->iaoq_b - env->iaoq_f; | |
297 | if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) { | |
298 | *cs_base |= (uint32_t)diff; | |
299 | } | |
300 | } | |
494737b7 RH |
301 | if ((env->sr[4] == env->sr[5]) |
302 | & (env->sr[4] == env->sr[6]) | |
303 | & (env->sr[4] == env->sr[7])) { | |
304 | flags |= TB_FLAG_SR_SAME; | |
305 | } | |
c301f34e RH |
306 | #endif |
307 | ||
308 | *pflags = flags; | |
61766fe9 RH |
309 | } |
310 | ||
eaa3783b RH |
311 | target_ureg cpu_hppa_get_psw(CPUHPPAState *env); |
312 | void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg); | |
61766fe9 RH |
313 | void cpu_hppa_loaded_fr0(CPUHPPAState *env); |
314 | ||
d5de20bd SS |
315 | #ifdef CONFIG_USER_ONLY |
316 | static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { } | |
317 | #else | |
318 | void cpu_hppa_change_prot_id(CPUHPPAState *env); | |
319 | #endif | |
320 | ||
61766fe9 RH |
321 | #define cpu_signal_handler cpu_hppa_signal_handler |
322 | ||
323 | int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); | |
813dff13 | 324 | hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); |
61766fe9 RH |
325 | int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); |
326 | int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | |
327 | void hppa_cpu_do_interrupt(CPUState *cpu); | |
328 | bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); | |
90c84c56 | 329 | void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); |
3c7bef03 RH |
330 | bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
331 | MMUAccessType access_type, int mmu_idx, | |
332 | bool probe, uintptr_t retaddr); | |
333 | #ifndef CONFIG_USER_ONLY | |
650cdb2a RH |
334 | int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, |
335 | int type, hwaddr *pphys, int *pprot); | |
4f5f2548 | 336 | extern const MemoryRegionOps hppa_io_eir_ops; |
c643603a | 337 | extern const struct VMStateDescription vmstate_hppa_cpu; |
49c29d6c | 338 | void hppa_cpu_alarm_timer(void *); |
43e05652 | 339 | int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr); |
650cdb2a | 340 | #endif |
2dfcca9f | 341 | void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); |
61766fe9 RH |
342 | |
343 | #endif /* HPPA_CPU_H */ |