[mirror_qemu.git] / target / loongarch / cpu.c

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * QEMU LoongArch CPU
 *
 * Copyright (c) 2021 Loongson Technology Corporation Limited
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/qemu-print.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "sysemu/qtest.h"
#include "exec/exec-all.h"
#include "qapi/qapi-commands-machine-target.h"
#include "cpu.h"
#include "internals.h"
#include "fpu/softfloat-helpers.h"
#include "cpu-csr.h"

const char * const regnames[32] = {
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
    "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
    "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
};

const char * const fregnames[32] = {
    "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
    "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
    "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
    "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
};

static const char * const excp_names[] = {
    [EXCCODE_INT] = "Interrupt",
    [EXCCODE_PIL] = "Page invalid exception for load",
    [EXCCODE_PIS] = "Page invalid exception for store",
    [EXCCODE_PIF] = "Page invalid exception for fetch",
    [EXCCODE_PME] = "Page modified exception",
    [EXCCODE_PNR] = "Page Not Readable exception",
    [EXCCODE_PNX] = "Page Not Executable exception",
    [EXCCODE_PPI] = "Page Privilege error",
    [EXCCODE_ADEF] = "Address error for instruction fetch",
    [EXCCODE_ADEM] = "Address error for Memory access",
    [EXCCODE_SYS] = "Syscall",
    [EXCCODE_BRK] = "Break",
    [EXCCODE_INE] = "Instruction Non-Existent",
    [EXCCODE_IPE] = "Instruction privilege error",
    [EXCCODE_FPE] = "Floating Point Exception",
    [EXCCODE_DBP] = "Debug breakpoint",
};

const char *loongarch_exception_name(int32_t exception)
{
    assert(excp_names[exception]);
    return excp_names[exception];
}

void G_NORETURN do_raise_exception(CPULoongArchState *env,
                                   uint32_t exception,
                                   uintptr_t pc)
{
    CPUState *cs = env_cpu(env);

    qemu_log_mask(CPU_LOG_INT, "%s: %d (%s)\n",
                  __func__,
                  exception,
                  loongarch_exception_name(exception));
    cs->exception_index = exception;

    cpu_loop_exit_restore(cs, pc);
}

static void loongarch_cpu_set_pc(CPUState *cs, vaddr value)
{
    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
    CPULoongArchState *env = &cpu->env;

    env->pc = value;
}

void loongarch_cpu_set_irq(void *opaque, int irq, int level)
{
    LoongArchCPU *cpu = opaque;
    CPULoongArchState *env = &cpu->env;
    CPUState *cs = CPU(cpu);

    if (irq < 0 || irq >= N_IRQS) {
        return;
    }

    env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0);

    if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) {
        cpu_interrupt(cs, CPU_INTERRUPT_HARD);
    } else {
        cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
    }
}

static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env)
{
    bool ret = 0;

    ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) &&
          !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)));

    return ret;
}

/* Check if there is pending and not masked out interrupt */
static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env)
{
    uint32_t pending;
    uint32_t status;
    bool r;

    pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS);
    status  = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE);

    r = (pending & status) != 0;
    return r;
}

static void loongarch_cpu_do_interrupt(CPUState *cs)
{
    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
    CPULoongArchState *env = &cpu->env;
    bool update_badinstr = 1;
    int cause = -1;
    const char *name;
    bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR);
    uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS);

    if (cs->exception_index != EXCCODE_INT) {
        if (cs->exception_index < 0 ||
            cs->exception_index > ARRAY_SIZE(excp_names)) {
            name = "unknown";
        } else {
            name = excp_names[cs->exception_index];
        }

        qemu_log_mask(CPU_LOG_INT,
                     "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx
                     " TLBRERA " TARGET_FMT_lx " %s exception\n", __func__,
                     env->pc, env->CSR_ERA, env->CSR_TLBRERA, name);
    }

    switch (cs->exception_index) {
    case EXCCODE_DBP:
        env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1);
        env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC);
        goto set_DERA;
    set_DERA:
        env->CSR_DERA = env->pc;
        env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1);
        env->pc = env->CSR_EENTRY + 0x480;
        break;
    case EXCCODE_INT:
        if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
            env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1);
            goto set_DERA;
        }
        QEMU_FALLTHROUGH;
    case EXCCODE_PIF:
        cause = cs->exception_index;
        update_badinstr = 0;
        break;
    case EXCCODE_ADEM:
    case EXCCODE_SYS:
    case EXCCODE_BRK:
    case EXCCODE_PIL:
    case EXCCODE_PIS:
    case EXCCODE_PME:
    case EXCCODE_PNR:
    case EXCCODE_PNX:
    case EXCCODE_PPI:
    case EXCCODE_INE:
    case EXCCODE_IPE:
    case EXCCODE_FPE:
        cause = cs->exception_index;
        break;
    default:
        qemu_log("Error: exception(%d) '%s' has not been supported\n",
                 cs->exception_index, excp_names[cs->exception_index]);
        abort();
    }

    if (update_badinstr) {
        env->CSR_BADI = cpu_ldl_code(env, env->pc);
    }

    /* Save PLV and IE */
    if (tlbfill) {
        env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV,
                                       FIELD_EX64(env->CSR_CRMD,
                                       CSR_CRMD, PLV));
        env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE,
                                       FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
        /* set the DA mode */
        env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1);
        env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0);
        env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,
                                      PC, (env->pc >> 2));
    } else {
        env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, cause);
        env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,
                                   FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
        env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,
                                   FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
        env->CSR_ERA = env->pc;
    }

    env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
    env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);

    if  (cs->exception_index == EXCCODE_INT) {
        /* Interrupt */
        uint32_t vector = 0;
        uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS);
        pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE);

        /* Find the highest-priority interrupt. */
        vector = 31 - clz32(pending);
        env->pc = env->CSR_EENTRY + (EXCCODE_EXTERNAL_INT + vector) * vec_size;
        qemu_log_mask(CPU_LOG_INT,
                      "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
                      " cause %d\n" "    A " TARGET_FMT_lx " D "
                      TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS"
                      TARGET_FMT_lx "\n",
                      __func__, env->pc, env->CSR_ERA,
                      cause, env->CSR_BADV, env->CSR_DERA, vector,
                      env->CSR_ECFG, env->CSR_ESTAT);
    } else {
        if (tlbfill) {
            env->pc = env->CSR_TLBRENTRY;
        } else {
            env->pc = env->CSR_EENTRY;
            env->pc += cause * vec_size;
        }
        qemu_log_mask(CPU_LOG_INT,
                      "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
                      " cause %d%s\n, ESTAT " TARGET_FMT_lx
                      " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx
                      "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu
                      " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc,
                      tlbfill ? env->CSR_TLBRERA : env->CSR_ERA,
                      cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT,
                      env->CSR_ECFG,
                      tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV,
                      env->CSR_BADI, env->gpr[11], cs->cpu_index,
                      env->CSR_ASID);
    }
    cs->exception_index = -1;
}

static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
                                                vaddr addr, unsigned size,
                                                MMUAccessType access_type,
                                                int mmu_idx, MemTxAttrs attrs,
                                                MemTxResult response,
                                                uintptr_t retaddr)
{
    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
    CPULoongArchState *env = &cpu->env;

    if (access_type == MMU_INST_FETCH) {
        do_raise_exception(env, EXCCODE_ADEF, retaddr);
    } else {
        do_raise_exception(env, EXCCODE_ADEM, retaddr);
    }
}

static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
    if (interrupt_request & CPU_INTERRUPT_HARD) {
        LoongArchCPU *cpu = LOONGARCH_CPU(cs);
        CPULoongArchState *env = &cpu->env;

        if (cpu_loongarch_hw_interrupts_enabled(env) &&
            cpu_loongarch_hw_interrupts_pending(env)) {
            /* Raise it */
            cs->exception_index = EXCCODE_INT;
            loongarch_cpu_do_interrupt(cs);
            return true;
        }
    }
    return false;
}

#ifdef CONFIG_TCG
static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
                                              const TranslationBlock *tb)
{
    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
    CPULoongArchState *env = &cpu->env;

    env->pc = tb->pc;
}
#endif /* CONFIG_TCG */

static bool loongarch_cpu_has_work(CPUState *cs)
{
    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
    CPULoongArchState *env = &cpu->env;
    bool has_work = false;

    if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
        cpu_loongarch_hw_interrupts_pending(env)) {
        has_work = true;
    }

    return has_work;
}

static void loongarch_la464_initfn(Object *obj)
{
    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
    CPULoongArchState *env = &cpu->env;
    int i;

    for (i = 0; i < 21; i++) {
        env->cpucfg[i] = 0x0;
    }

    env->cpucfg[0] = 0x14c010;  /* PRID */

    uint32_t data = 0;
    data = FIELD_DP32(data, CPUCFG1, ARCH, 2);
    data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
    data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
    data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f);
    data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f);
    data = FIELD_DP32(data, CPUCFG1, UAL, 1);
    data = FIELD_DP32(data, CPUCFG1, RI, 1);
    data = FIELD_DP32(data, CPUCFG1, EP, 1);
    data = FIELD_DP32(data, CPUCFG1, RPLV, 1);
    data = FIELD_DP32(data, CPUCFG1, HP, 1);
    data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1);
    env->cpucfg[1] = data;

    data = 0;
    data = FIELD_DP32(data, CPUCFG2, FP, 1);
    data = FIELD_DP32(data, CPUCFG2, FP_SP, 1);
    data = FIELD_DP32(data, CPUCFG2, FP_DP, 1);
    data = FIELD_DP32(data, CPUCFG2, FP_VER, 1);
    data = FIELD_DP32(data, CPUCFG2, LLFTP, 1);
    data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1);
    data = FIELD_DP32(data, CPUCFG2, LAM, 1);
    env->cpucfg[2] = data;

    env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */

    data = 0;
    data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1);
    data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1);
    env->cpucfg[5] = data;

    data = 0;
    data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1);
    data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1);
    data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1);
    data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1);
    data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1);
    data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1);
    data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1);
    data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1);
    env->cpucfg[16] = data;

    data = 0;
    data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3);
    data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8);
    data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6);
    env->cpucfg[17] = data;

    data = 0;
    data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3);
    data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8);
    data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6);
    env->cpucfg[18] = data;

    data = 0;
    data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15);
    data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8);
    data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6);
    env->cpucfg[19] = data;

    data = 0;
    data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15);
    data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14);
    data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 6);
    env->cpucfg[20] = data;

    env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
}

static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
{
    const char *typename = object_class_get_name(OBJECT_CLASS(data));

    qemu_printf("%s\n", typename);
}

void loongarch_cpu_list(void)
{
    GSList *list;
    list = object_class_get_list_sorted(TYPE_LOONGARCH_CPU, false);
    g_slist_foreach(list, loongarch_cpu_list_entry, NULL);
    g_slist_free(list);
}

static void loongarch_cpu_reset(DeviceState *dev)
{
    CPUState *cs = CPU(dev);
    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
    LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu);
    CPULoongArchState *env = &cpu->env;

    lacc->parent_reset(dev);

    env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3;
    env->fcsr0 = 0x0;

    int n;
    /* Set csr registers value after reset */
    env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
    env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
    env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1);
    env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0);
    env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 1);
    env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 1);

    env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0);
    env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0);
    env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0);
    env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0);

    env->CSR_MISC = 0;

    env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0);
    env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0);

    env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2));
    env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0);
    env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0);
    env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0);
    env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
    env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0);

    env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2);
    env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63);
    env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7);
    env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8);

    for (n = 0; n < 4; n++) {
        env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0);
        env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0);
        env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0);
        env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0);
    }

    env->pc = 0x1c000000;

    restore_fp_status(env);
    cs->exception_index = -1;
}

static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
    info->print_insn = print_insn_loongarch;
}

static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
{
    CPUState *cs = CPU(dev);
    LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev);
    Error *local_err = NULL;

    cpu_exec_realizefn(cs, &local_err);
    if (local_err != NULL) {
        error_propagate(errp, local_err);
        return;
    }

    cpu_reset(cs);
    qemu_init_vcpu(cs);

    lacc->parent_realize(dev, errp);
}

static void loongarch_cpu_init(Object *obj)
{
    LoongArchCPU *cpu = LOONGARCH_CPU(obj);

    cpu_set_cpustate_pointers(cpu);
    qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS);
}

static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model)
{
    ObjectClass *oc;
    char *typename;

    typename = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model);
    oc = object_class_by_name(typename);
    g_free(typename);
    return oc;
}

void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
    LoongArchCPU *cpu = LOONGARCH_CPU(cs);
    CPULoongArchState *env = &cpu->env;
    int i;

    qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
    qemu_fprintf(f, " FCSR0 0x%08x  fp_status 0x%02x\n", env->fcsr0,
                 get_float_exception_flags(&env->fp_status));

    /* gpr */
    for (i = 0; i < 32; i++) {
        if ((i & 3) == 0) {
            qemu_fprintf(f, " GPR%02d:", i);
        }
        qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]);
        if ((i & 3) == 3) {
            qemu_fprintf(f, "\n");
        }
    }

    qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD);
    qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD);
    qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN);
    qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT);
    qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA);
    qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV);
    qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI);
    qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY);
    qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 ","
                 " PRCFG3=%016" PRIx64 "\n",
                 env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3);
    qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY);
    qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV);
    qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);

    /* fpr */
    if (flags & CPU_DUMP_FPU) {
        for (i = 0; i < 32; i++) {
            qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i]);
            if ((i & 3) == 3) {
                qemu_fprintf(f, "\n");
            }
        }
    }
}

#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"

static struct TCGCPUOps loongarch_tcg_ops = {
    .initialize = loongarch_translate_init,
    .synchronize_from_tb = loongarch_cpu_synchronize_from_tb,

    .tlb_fill = loongarch_cpu_tlb_fill,
    .cpu_exec_interrupt = loongarch_cpu_exec_interrupt,
    .do_interrupt = loongarch_cpu_do_interrupt,
    .do_transaction_failed = loongarch_cpu_do_transaction_failed,
};
#endif /* CONFIG_TCG */

#include "hw/core/sysemu-cpu-ops.h"

static const struct SysemuCPUOps loongarch_sysemu_ops = {
    .get_phys_page_debug = loongarch_cpu_get_phys_page_debug,
};

static void loongarch_cpu_class_init(ObjectClass *c, void *data)
{
    LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c);
    CPUClass *cc = CPU_CLASS(c);
    DeviceClass *dc = DEVICE_CLASS(c);

    device_class_set_parent_realize(dc, loongarch_cpu_realizefn,
                                    &lacc->parent_realize);
    device_class_set_parent_reset(dc, loongarch_cpu_reset, &lacc->parent_reset);

    cc->class_by_name = loongarch_cpu_class_by_name;
    cc->has_work = loongarch_cpu_has_work;
    cc->dump_state = loongarch_cpu_dump_state;
    cc->set_pc = loongarch_cpu_set_pc;
    dc->vmsd = &vmstate_loongarch_cpu;
    cc->sysemu_ops = &loongarch_sysemu_ops;
    cc->disas_set_info = loongarch_cpu_disas_set_info;
#ifdef CONFIG_TCG
    cc->tcg_ops = &loongarch_tcg_ops;
#endif
}

#define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \
    { \
        .parent = TYPE_LOONGARCH_CPU, \
        .instance_init = initfn, \
        .name = LOONGARCH_CPU_TYPE_NAME(model), \
    }

static const TypeInfo loongarch_cpu_type_infos[] = {
    {
        .name = TYPE_LOONGARCH_CPU,
        .parent = TYPE_CPU,
        .instance_size = sizeof(LoongArchCPU),
        .instance_init = loongarch_cpu_init,

        .abstract = true,
        .class_size = sizeof(LoongArchCPUClass),
        .class_init = loongarch_cpu_class_init,
    },
    DEFINE_LOONGARCH_CPU_TYPE("la464", loongarch_la464_initfn),
};

DEFINE_TYPES(loongarch_cpu_type_infos)

static void loongarch_cpu_add_definition(gpointer data, gpointer user_data)
{
    ObjectClass *oc = data;
    CpuDefinitionInfoList **cpu_list = user_data;
    CpuDefinitionInfo *info = g_new0(CpuDefinitionInfo, 1);
    const char *typename = object_class_get_name(oc);

    info->name = g_strndup(typename,
                           strlen(typename) - strlen("-" TYPE_LOONGARCH_CPU));
    info->q_typename = g_strdup(typename);

    QAPI_LIST_PREPEND(*cpu_list, info);
}

CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
{
    CpuDefinitionInfoList *cpu_list = NULL;
    GSList *list;

    list = object_class_get_list(TYPE_LOONGARCH_CPU, false);
    g_slist_foreach(list, loongarch_cpu_add_definition, &cpu_list);
    g_slist_free(list);

    return cpu_list;
}
Commit	Line	Data
228021f0 SG	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
	2	/*
	3	* QEMU LoongArch CPU
	4	*
	5	* Copyright (c) 2021 Loongson Technology Corporation Limited
	6	*/
	7
	8	#include "qemu/osdep.h"
	9	#include "qemu/log.h"
	10	#include "qemu/qemu-print.h"
	11	#include "qapi/error.h"
	12	#include "qemu/module.h"
	13	#include "sysemu/qtest.h"
	14	#include "exec/exec-all.h"
	15	#include "qapi/qapi-commands-machine-target.h"
	16	#include "cpu.h"
	17	#include "internals.h"
	18	#include "fpu/softfloat-helpers.h"
398cecb9	19	#include "cpu-csr.h"
228021f0 SG	20
	21	const char * const regnames[32] = {
	22	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
	23	"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
	24	"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
	25	"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
	26	};
	27
	28	const char * const fregnames[32] = {
	29	"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
	30	"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
	31	"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
	32	"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
	33	};
	34
	35	static const char * const excp_names[] = {
	36	[EXCCODE_INT] = "Interrupt",
	37	[EXCCODE_PIL] = "Page invalid exception for load",
	38	[EXCCODE_PIS] = "Page invalid exception for store",
	39	[EXCCODE_PIF] = "Page invalid exception for fetch",
	40	[EXCCODE_PME] = "Page modified exception",
	41	[EXCCODE_PNR] = "Page Not Readable exception",
	42	[EXCCODE_PNX] = "Page Not Executable exception",
	43	[EXCCODE_PPI] = "Page Privilege error",
	44	[EXCCODE_ADEF] = "Address error for instruction fetch",
	45	[EXCCODE_ADEM] = "Address error for Memory access",
	46	[EXCCODE_SYS] = "Syscall",
	47	[EXCCODE_BRK] = "Break",
	48	[EXCCODE_INE] = "Instruction Non-Existent",
	49	[EXCCODE_IPE] = "Instruction privilege error",
	50	[EXCCODE_FPE] = "Floating Point Exception",
	51	[EXCCODE_DBP] = "Debug breakpoint",
	52	};
	53
	54	const char *loongarch_exception_name(int32_t exception)
	55	{
	56	assert(excp_names[exception]);
	57	return excp_names[exception];
	58	}
	59
	60	void G_NORETURN do_raise_exception(CPULoongArchState *env,
	61	uint32_t exception,
	62	uintptr_t pc)
	63	{
	64	CPUState *cs = env_cpu(env);
	65
	66	qemu_log_mask(CPU_LOG_INT, "%s: %d (%s)\n",
	67	__func__,
	68	exception,
	69	loongarch_exception_name(exception));
	70	cs->exception_index = exception;
	71
	72	cpu_loop_exit_restore(cs, pc);
	73	}
	74
	75	static void loongarch_cpu_set_pc(CPUState *cs, vaddr value)
	76	{
	77	LoongArchCPU *cpu = LOONGARCH_CPU(cs);
	78	CPULoongArchState *env = &cpu->env;
	79
	80	env->pc = value;
	81	}
	82
f757a2cd XY	83	void loongarch_cpu_set_irq(void *opaque, int irq, int level)
	84	{
	85	LoongArchCPU *cpu = opaque;
	86	CPULoongArchState *env = &cpu->env;
	87	CPUState *cs = CPU(cpu);
	88
	89	if (irq < 0 \|\| irq >= N_IRQS) {
	90	return;
	91	}
	92
	93	env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0);
	94
	95	if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) {
	96	cpu_interrupt(cs, CPU_INTERRUPT_HARD);
	97	} else {
	98	cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
	99	}
	100	}
	101
	102	static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env)
	103	{
	104	bool ret = 0;
	105
	106	ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) &&
	107	!(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)));
	108
	109	return ret;
	110	}
	111
	112	/* Check if there is pending and not masked out interrupt */
	113	static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env)
	114	{
	115	uint32_t pending;
	116	uint32_t status;
	117	bool r;
	118
	119	pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS);
	120	status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE);
	121
	122	r = (pending & status) != 0;
	123	return r;
	124	}
	125
	126	static void loongarch_cpu_do_interrupt(CPUState *cs)
	127	{
	128	LoongArchCPU *cpu = LOONGARCH_CPU(cs);
	129	CPULoongArchState *env = &cpu->env;
	130	bool update_badinstr = 1;
	131	int cause = -1;
	132	const char *name;
	133	bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR);
	134	uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS);
	135
	136	if (cs->exception_index != EXCCODE_INT) {
	137	if (cs->exception_index < 0 \|\|
	138	cs->exception_index > ARRAY_SIZE(excp_names)) {
	139	name = "unknown";
	140	} else {
	141	name = excp_names[cs->exception_index];
	142	}
	143
	144	qemu_log_mask(CPU_LOG_INT,
	145	"%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx
	146	" TLBRERA " TARGET_FMT_lx " %s exception\n", __func__,
147	env->pc, env->CSR_ERA, env->CSR_TLBRERA, name);
148	}
149
150	switch (cs->exception_index) {
151	case EXCCODE_DBP:
152	env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1);
153	env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC);
154	goto set_DERA;
155	set_DERA:
156	env->CSR_DERA = env->pc;
157	env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1);
158	env->pc = env->CSR_EENTRY + 0x480;
159	break;
160	case EXCCODE_INT:
161	if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
162	env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1);
163	goto set_DERA;
164	}
165	QEMU_FALLTHROUGH;
166	case EXCCODE_PIF:
167	cause = cs->exception_index;
168	update_badinstr = 0;
169	break;
170	case EXCCODE_ADEM:
171	case EXCCODE_SYS:
172	case EXCCODE_BRK:
173	case EXCCODE_PIL:
174	case EXCCODE_PIS:
175	case EXCCODE_PME:
176	case EXCCODE_PNR:
177	case EXCCODE_PNX:
178	case EXCCODE_PPI:
179	case EXCCODE_INE:
180	case EXCCODE_IPE:
181	case EXCCODE_FPE:
182	cause = cs->exception_index;
183	break;
184	default:
185	qemu_log("Error: exception(%d) '%s' has not been supported\n",
186	cs->exception_index, excp_names[cs->exception_index]);
187	abort();
188	}
189
190	if (update_badinstr) {
191	env->CSR_BADI = cpu_ldl_code(env, env->pc);
192	}
193
194	/* Save PLV and IE */
195	if (tlbfill) {
196	env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV,
197	FIELD_EX64(env->CSR_CRMD,
198	CSR_CRMD, PLV));
199	env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE,
200	FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
201	/* set the DA mode */
202	env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1);
203	env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0);
204	env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,
205	PC, (env->pc >> 2));
206	} else {
207	env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, cause);
208	env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,
209	FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
210	env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,
211	FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
212	env->CSR_ERA = env->pc;
213	}
214
215	env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
216	env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
217
218	if (cs->exception_index == EXCCODE_INT) {
219	/* Interrupt */
220	uint32_t vector = 0;
221	uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS);
222	pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE);
223
224	/* Find the highest-priority interrupt. */
225	vector = 31 - clz32(pending);
226	env->pc = env->CSR_EENTRY + (EXCCODE_EXTERNAL_INT + vector) * vec_size;
227	qemu_log_mask(CPU_LOG_INT,
228	"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
229	" cause %d\n" " A " TARGET_FMT_lx " D "
230	TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS"
231	TARGET_FMT_lx "\n",
232	__func__, env->pc, env->CSR_ERA,
233	cause, env->CSR_BADV, env->CSR_DERA, vector,
234	env->CSR_ECFG, env->CSR_ESTAT);
235	} else {
236	if (tlbfill) {
237	env->pc = env->CSR_TLBRENTRY;
238	} else {
239	env->pc = env->CSR_EENTRY;
240	env->pc += cause * vec_size;
241	}
242	qemu_log_mask(CPU_LOG_INT,
243	"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
244	" cause %d%s\n, ESTAT " TARGET_FMT_lx
245	" EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx
246	"BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu
247	" cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc,
248	tlbfill ? env->CSR_TLBRERA : env->CSR_ERA,
249	cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT,
250	env->CSR_ECFG,
251	tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV,
252	env->CSR_BADI, env->gpr[11], cs->cpu_index,
253	env->CSR_ASID);
254	}
255	cs->exception_index = -1;
256	}
257
258	static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
259	vaddr addr, unsigned size,
260	MMUAccessType access_type,
261	int mmu_idx, MemTxAttrs attrs,
262	MemTxResult response,
263	uintptr_t retaddr)
264	{
265	LoongArchCPU *cpu = LOONGARCH_CPU(cs);
266	CPULoongArchState *env = &cpu->env;
267
268	if (access_type == MMU_INST_FETCH) {
269	do_raise_exception(env, EXCCODE_ADEF, retaddr);
270	} else {
271	do_raise_exception(env, EXCCODE_ADEM, retaddr);
272	}
273	}
274
275	static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
276	{
277	if (interrupt_request & CPU_INTERRUPT_HARD) {
278	LoongArchCPU *cpu = LOONGARCH_CPU(cs);
279	CPULoongArchState *env = &cpu->env;
280
281	if (cpu_loongarch_hw_interrupts_enabled(env) &&
282	cpu_loongarch_hw_interrupts_pending(env)) {
283	/* Raise it */
284	cs->exception_index = EXCCODE_INT;
285	loongarch_cpu_do_interrupt(cs);
286	return true;
287	}
288	}
289	return false;
290	}
291
228021f0 SG	292	#ifdef CONFIG_TCG
	293	static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
	294	const TranslationBlock *tb)
	295	{
	296	LoongArchCPU *cpu = LOONGARCH_CPU(cs);
	297	CPULoongArchState *env = &cpu->env;
	298
	299	env->pc = tb->pc;
	300	}
	301	#endif /* CONFIG_TCG */
	302
f757a2cd XY	303	static bool loongarch_cpu_has_work(CPUState *cs)
	304	{
	305	LoongArchCPU *cpu = LOONGARCH_CPU(cs);
	306	CPULoongArchState *env = &cpu->env;
	307	bool has_work = false;
	308
	309	if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
	310	cpu_loongarch_hw_interrupts_pending(env)) {
	311	has_work = true;
	312	}
	313
	314	return has_work;
	315	}
	316
228021f0 SG	317	static void loongarch_la464_initfn(Object *obj)
	318	{
	319	LoongArchCPU *cpu = LOONGARCH_CPU(obj);
	320	CPULoongArchState *env = &cpu->env;
	321	int i;
	322
	323	for (i = 0; i < 21; i++) {
	324	env->cpucfg[i] = 0x0;
	325	}
	326
	327	env->cpucfg[0] = 0x14c010; /* PRID */
	328
	329	uint32_t data = 0;
	330	data = FIELD_DP32(data, CPUCFG1, ARCH, 2);
	331	data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
	332	data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
	333	data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f);
	334	data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f);
	335	data = FIELD_DP32(data, CPUCFG1, UAL, 1);
	336	data = FIELD_DP32(data, CPUCFG1, RI, 1);
	337	data = FIELD_DP32(data, CPUCFG1, EP, 1);
	338	data = FIELD_DP32(data, CPUCFG1, RPLV, 1);
	339	data = FIELD_DP32(data, CPUCFG1, HP, 1);
	340	data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1);
	341	env->cpucfg[1] = data;
	342
	343	data = 0;
	344	data = FIELD_DP32(data, CPUCFG2, FP, 1);
	345	data = FIELD_DP32(data, CPUCFG2, FP_SP, 1);
	346	data = FIELD_DP32(data, CPUCFG2, FP_DP, 1);
	347	data = FIELD_DP32(data, CPUCFG2, FP_VER, 1);
	348	data = FIELD_DP32(data, CPUCFG2, LLFTP, 1);
	349	data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1);
	350	data = FIELD_DP32(data, CPUCFG2, LAM, 1);
	351	env->cpucfg[2] = data;
	352
	353	env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */
	354
	355	data = 0;
	356	data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1);
	357	data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1);
	358	env->cpucfg[5] = data;
	359
	360	data = 0;
	361	data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1);
	362	data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1);
	363	data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1);
	364	data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1);
	365	data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1);
	366	data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1);
	367	data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1);
	368	data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1);
	369	env->cpucfg[16] = data;
	370
	371	data = 0;
	372	data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3);
	373	data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8);
	374	data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6);
	375	env->cpucfg[17] = data;
	376
	377	data = 0;
	378	data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3);
	379	data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8);
	380	data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6);
381	env->cpucfg[18] = data;
382
383	data = 0;
384	data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15);
385	data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8);
386	data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6);
387	env->cpucfg[19] = data;
388
389	data = 0;
390	data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15);
391	data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14);
392	data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 6);
393	env->cpucfg[20] = data;
398cecb9 XY	394
398cecb9 XY	395	env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
228021f0 SG	396	}
	397
	398	static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
	399	{
	400	const char *typename = object_class_get_name(OBJECT_CLASS(data));
	401
	402	qemu_printf("%s\n", typename);
	403	}
	404
	405	void loongarch_cpu_list(void)
	406	{
	407	GSList *list;
	408	list = object_class_get_list_sorted(TYPE_LOONGARCH_CPU, false);
	409	g_slist_foreach(list, loongarch_cpu_list_entry, NULL);
	410	g_slist_free(list);
	411	}
	412
	413	static void loongarch_cpu_reset(DeviceState *dev)
	414	{
	415	CPUState *cs = CPU(dev);
	416	LoongArchCPU *cpu = LOONGARCH_CPU(cs);
	417	LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu);
	418	CPULoongArchState *env = &cpu->env;
	419
	420	lacc->parent_reset(dev);
	421
	422	env->fcsr0_mask = FCSR0_M1 \| FCSR0_M2 \| FCSR0_M3;
	423	env->fcsr0 = 0x0;
	424
398cecb9 XY	425	int n;
	426	/* Set csr registers value after reset */
	427	env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
	428	env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
	429	env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1);
	430	env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0);
	431	env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 1);
	432	env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 1);
	433
	434	env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0);
	435	env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0);
	436	env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0);
	437	env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0);
	438
	439	env->CSR_MISC = 0;
	440
	441	env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0);
	442	env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0);
	443
	444	env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2));
	445	env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0);
	446	env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0);
	447	env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0);
	448	env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
	449	env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0);
	450
	451	env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2);
	452	env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63);
	453	env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7);
	454	env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8);
	455
	456	for (n = 0; n < 4; n++) {
	457	env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0);
	458	env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0);
	459	env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0);
	460	env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0);
	461	}
	462
f757a2cd XY	463	env->pc = 0x1c000000;
f757a2cd XY	464
d578ca6c	465	restore_fp_status(env);
228021f0 SG	466	cs->exception_index = -1;
	467	}
	468
	469	static void loongarch_cpu_disas_set_info(CPUState s, disassemble_info info)
	470	{
	471	info->print_insn = print_insn_loongarch;
	472	}
	473
	474	static void loongarch_cpu_realizefn(DeviceState dev, Error *errp)
	475	{
	476	CPUState *cs = CPU(dev);
	477	LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev);
	478	Error *local_err = NULL;
	479
	480	cpu_exec_realizefn(cs, &local_err);
	481	if (local_err != NULL) {
	482	error_propagate(errp, local_err);
	483	return;
	484	}
	485
	486	cpu_reset(cs);
	487	qemu_init_vcpu(cs);
	488
	489	lacc->parent_realize(dev, errp);
	490	}
	491
	492	static void loongarch_cpu_init(Object *obj)
	493	{
	494	LoongArchCPU *cpu = LOONGARCH_CPU(obj);
	495
	496	cpu_set_cpustate_pointers(cpu);
f757a2cd	497	qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS);
228021f0 SG	498	}
	499
	500	static ObjectClass loongarch_cpu_class_by_name(const char cpu_model)
	501	{
	502	ObjectClass *oc;
	503	char *typename;
	504
	505	typename = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model);
	506	oc = object_class_by_name(typename);
	507	g_free(typename);
	508	return oc;
	509	}
	510
	511	void loongarch_cpu_dump_state(CPUState cs, FILE f, int flags)
	512	{
	513	LoongArchCPU *cpu = LOONGARCH_CPU(cs);
	514	CPULoongArchState *env = &cpu->env;
	515	int i;
	516
	517	qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
	518	qemu_fprintf(f, " FCSR0 0x%08x fp_status 0x%02x\n", env->fcsr0,
	519	get_float_exception_flags(&env->fp_status));
	520
	521	/* gpr */
	522	for (i = 0; i < 32; i++) {
	523	if ((i & 3) == 0) {
	524	qemu_fprintf(f, " GPR%02d:", i);
	525	}
	526	qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]);
	527	if ((i & 3) == 3) {
	528	qemu_fprintf(f, "\n");
	529	}
	530	}
	531
7e1c521e XY	532	qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD);
	533	qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD);
	534	qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN);
	535	qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT);
	536	qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA);
	537	qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV);
	538	qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI);
	539	qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY);
	540	qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 ","
	541	" PRCFG3=%016" PRIx64 "\n",
	542	env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3);
	543	qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY);
	544	qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV);
	545	qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);
	546
228021f0 SG	547	/* fpr */
	548	if (flags & CPU_DUMP_FPU) {
	549	for (i = 0; i < 32; i++) {
	550	qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i]);
	551	if ((i & 3) == 3) {
	552	qemu_fprintf(f, "\n");
	553	}
	554	}
	555	}
	556	}
	557
	558	#ifdef CONFIG_TCG
	559	#include "hw/core/tcg-cpu-ops.h"
	560
	561	static struct TCGCPUOps loongarch_tcg_ops = {
	562	.initialize = loongarch_translate_init,
	563	.synchronize_from_tb = loongarch_cpu_synchronize_from_tb,
7e1c521e XY	564
7e1c521e XY	565	.tlb_fill = loongarch_cpu_tlb_fill,
f757a2cd XY	566	.cpu_exec_interrupt = loongarch_cpu_exec_interrupt,
	567	.do_interrupt = loongarch_cpu_do_interrupt,
	568	.do_transaction_failed = loongarch_cpu_do_transaction_failed,
228021f0 SG	569	};
	570	#endif /* CONFIG_TCG */
	571
7e1c521e XY	572	#include "hw/core/sysemu-cpu-ops.h"
	573
	574	static const struct SysemuCPUOps loongarch_sysemu_ops = {
	575	.get_phys_page_debug = loongarch_cpu_get_phys_page_debug,
	576	};
	577
228021f0 SG	578	static void loongarch_cpu_class_init(ObjectClass c, void data)
	579	{
	580	LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c);
	581	CPUClass *cc = CPU_CLASS(c);
	582	DeviceClass *dc = DEVICE_CLASS(c);
	583
	584	device_class_set_parent_realize(dc, loongarch_cpu_realizefn,
	585	&lacc->parent_realize);
	586	device_class_set_parent_reset(dc, loongarch_cpu_reset, &lacc->parent_reset);
	587
	588	cc->class_by_name = loongarch_cpu_class_by_name;
f757a2cd	589	cc->has_work = loongarch_cpu_has_work;
228021f0 SG	590	cc->dump_state = loongarch_cpu_dump_state;
228021f0 SG	591	cc->set_pc = loongarch_cpu_set_pc;
67ebd42a	592	dc->vmsd = &vmstate_loongarch_cpu;
7e1c521e	593	cc->sysemu_ops = &loongarch_sysemu_ops;
228021f0 SG	594	cc->disas_set_info = loongarch_cpu_disas_set_info;
	595	#ifdef CONFIG_TCG
	596	cc->tcg_ops = &loongarch_tcg_ops;
	597	#endif
	598	}
	599
	600	#define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \
	601	{ \
	602	.parent = TYPE_LOONGARCH_CPU, \
	603	.instance_init = initfn, \
	604	.name = LOONGARCH_CPU_TYPE_NAME(model), \
	605	}
	606
	607	static const TypeInfo loongarch_cpu_type_infos[] = {
	608	{
	609	.name = TYPE_LOONGARCH_CPU,
	610	.parent = TYPE_CPU,
	611	.instance_size = sizeof(LoongArchCPU),
	612	.instance_init = loongarch_cpu_init,
	613
	614	.abstract = true,
	615	.class_size = sizeof(LoongArchCPUClass),
	616	.class_init = loongarch_cpu_class_init,
	617	},
	618	DEFINE_LOONGARCH_CPU_TYPE("la464", loongarch_la464_initfn),
	619	};
	620
	621	DEFINE_TYPES(loongarch_cpu_type_infos)
425876f5 XY	622
	623	static void loongarch_cpu_add_definition(gpointer data, gpointer user_data)
	624	{
	625	ObjectClass *oc = data;
	626	CpuDefinitionInfoList **cpu_list = user_data;
	627	CpuDefinitionInfo *info = g_new0(CpuDefinitionInfo, 1);
	628	const char *typename = object_class_get_name(oc);
	629
	630	info->name = g_strndup(typename,
	631	strlen(typename) - strlen("-" TYPE_LOONGARCH_CPU));
	632	info->q_typename = g_strdup(typename);
	633
	634	QAPI_LIST_PREPEND(*cpu_list, info);
	635	}
	636
	637	CpuDefinitionInfoList qmp_query_cpu_definitions(Error *errp)
	638	{
	639	CpuDefinitionInfoList *cpu_list = NULL;
	640	GSList *list;
	641
	642	list = object_class_get_list(TYPE_LOONGARCH_CPU, false);
	643	g_slist_foreach(list, loongarch_cpu_add_definition, &cpu_list);
	644	g_slist_free(list);
	645
	646	return cpu_list;
	647	}