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Commit | Line | Data |
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07f5a258 MA |
1 | #ifndef MIPS_CPU_H |
2 | #define MIPS_CPU_H | |
6af0bf9c | 3 | |
d94f0a8e | 4 | #define ALIGNED_ONLY |
4ad40f36 | 5 | |
9349b4f9 | 6 | #define CPUArchState struct CPUMIPSState |
c2764719 | 7 | |
9a78eead | 8 | #include "qemu-common.h" |
416bf936 | 9 | #include "cpu-qom.h" |
6af0bf9c | 10 | #include "mips-defs.h" |
022c62cb | 11 | #include "exec/cpu-defs.h" |
6b4c305c | 12 | #include "fpu/softfloat.h" |
6af0bf9c | 13 | |
ead9360e | 14 | struct CPUMIPSState; |
6af0bf9c | 15 | |
ead9360e | 16 | typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; |
51b2772f | 17 | |
e97a391d YK |
18 | /* MSA Context */ |
19 | #define MSA_WRLEN (128) | |
20 | ||
e97a391d YK |
21 | typedef union wr_t wr_t; |
22 | union wr_t { | |
23 | int8_t b[MSA_WRLEN/8]; | |
24 | int16_t h[MSA_WRLEN/16]; | |
25 | int32_t w[MSA_WRLEN/32]; | |
26 | int64_t d[MSA_WRLEN/64]; | |
27 | }; | |
28 | ||
c227f099 AL |
29 | typedef union fpr_t fpr_t; |
30 | union fpr_t { | |
ead9360e TS |
31 | float64 fd; /* ieee double precision */ |
32 | float32 fs[2];/* ieee single precision */ | |
33 | uint64_t d; /* binary double fixed-point */ | |
34 | uint32_t w[2]; /* binary single fixed-point */ | |
e97a391d YK |
35 | /* FPU/MSA register mapping is not tested on big-endian hosts. */ |
36 | wr_t wr; /* vector data */ | |
ead9360e TS |
37 | }; |
38 | /* define FP_ENDIAN_IDX to access the same location | |
4ff9786c | 39 | * in the fpr_t union regardless of the host endianness |
ead9360e | 40 | */ |
e2542fe2 | 41 | #if defined(HOST_WORDS_BIGENDIAN) |
ead9360e TS |
42 | # define FP_ENDIAN_IDX 1 |
43 | #else | |
44 | # define FP_ENDIAN_IDX 0 | |
c570fd16 | 45 | #endif |
ead9360e TS |
46 | |
47 | typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; | |
48 | struct CPUMIPSFPUContext { | |
6af0bf9c | 49 | /* Floating point registers */ |
c227f099 | 50 | fpr_t fpr[32]; |
6ea83fed | 51 | float_status fp_status; |
5a5012ec | 52 | /* fpu implementation/revision register (fir) */ |
6af0bf9c | 53 | uint32_t fcr0; |
7c979afd | 54 | #define FCR0_FREP 29 |
b4dd99a3 | 55 | #define FCR0_UFRP 28 |
ba5c79f2 | 56 | #define FCR0_HAS2008 23 |
5a5012ec TS |
57 | #define FCR0_F64 22 |
58 | #define FCR0_L 21 | |
59 | #define FCR0_W 20 | |
60 | #define FCR0_3D 19 | |
61 | #define FCR0_PS 18 | |
62 | #define FCR0_D 17 | |
63 | #define FCR0_S 16 | |
64 | #define FCR0_PRID 8 | |
65 | #define FCR0_REV 0 | |
6ea83fed | 66 | /* fcsr */ |
599bc5e8 | 67 | uint32_t fcr31_rw_bitmask; |
6ea83fed | 68 | uint32_t fcr31; |
77be4199 | 69 | #define FCR31_FS 24 |
ba5c79f2 LA |
70 | #define FCR31_ABS2008 19 |
71 | #define FCR31_NAN2008 18 | |
f01be154 TS |
72 | #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) |
73 | #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) | |
74 | #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1)) | |
5a5012ec TS |
75 | #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) |
76 | #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) | |
77 | #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) | |
78 | #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0) | |
79 | #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0) | |
80 | #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0) | |
81 | #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0) | |
6ea83fed FB |
82 | #define FP_INEXACT 1 |
83 | #define FP_UNDERFLOW 2 | |
84 | #define FP_OVERFLOW 4 | |
85 | #define FP_DIV0 8 | |
86 | #define FP_INVALID 16 | |
87 | #define FP_UNIMPLEMENTED 32 | |
ead9360e TS |
88 | }; |
89 | ||
42c86612 | 90 | #define NB_MMU_MODES 4 |
c20d594e | 91 | #define TARGET_INSN_START_EXTRA_WORDS 2 |
6ebbf390 | 92 | |
ead9360e TS |
93 | typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; |
94 | struct CPUMIPSMVPContext { | |
95 | int32_t CP0_MVPControl; | |
96 | #define CP0MVPCo_CPA 3 | |
97 | #define CP0MVPCo_STLB 2 | |
98 | #define CP0MVPCo_VPC 1 | |
99 | #define CP0MVPCo_EVP 0 | |
100 | int32_t CP0_MVPConf0; | |
101 | #define CP0MVPC0_M 31 | |
102 | #define CP0MVPC0_TLBS 29 | |
103 | #define CP0MVPC0_GS 28 | |
104 | #define CP0MVPC0_PCP 27 | |
105 | #define CP0MVPC0_PTLBE 16 | |
106 | #define CP0MVPC0_TCA 15 | |
107 | #define CP0MVPC0_PVPE 10 | |
108 | #define CP0MVPC0_PTC 0 | |
109 | int32_t CP0_MVPConf1; | |
110 | #define CP0MVPC1_CIM 31 | |
111 | #define CP0MVPC1_CIF 30 | |
112 | #define CP0MVPC1_PCX 20 | |
113 | #define CP0MVPC1_PCP2 10 | |
114 | #define CP0MVPC1_PCP1 0 | |
115 | }; | |
116 | ||
c227f099 | 117 | typedef struct mips_def_t mips_def_t; |
ead9360e TS |
118 | |
119 | #define MIPS_SHADOW_SET_MAX 16 | |
120 | #define MIPS_TC_MAX 5 | |
f01be154 | 121 | #define MIPS_FPU_MAX 1 |
ead9360e | 122 | #define MIPS_DSP_ACC 4 |
e98c0d17 | 123 | #define MIPS_KSCRATCH_NUM 6 |
f6d4dd81 | 124 | #define MIPS_MAAR_MAX 16 /* Must be an even number. */ |
ead9360e | 125 | |
b5dc7732 TS |
126 | typedef struct TCState TCState; |
127 | struct TCState { | |
128 | target_ulong gpr[32]; | |
129 | target_ulong PC; | |
130 | target_ulong HI[MIPS_DSP_ACC]; | |
131 | target_ulong LO[MIPS_DSP_ACC]; | |
132 | target_ulong ACX[MIPS_DSP_ACC]; | |
133 | target_ulong DSPControl; | |
134 | int32_t CP0_TCStatus; | |
135 | #define CP0TCSt_TCU3 31 | |
136 | #define CP0TCSt_TCU2 30 | |
137 | #define CP0TCSt_TCU1 29 | |
138 | #define CP0TCSt_TCU0 28 | |
139 | #define CP0TCSt_TMX 27 | |
140 | #define CP0TCSt_RNST 23 | |
141 | #define CP0TCSt_TDS 21 | |
142 | #define CP0TCSt_DT 20 | |
143 | #define CP0TCSt_DA 15 | |
144 | #define CP0TCSt_A 13 | |
145 | #define CP0TCSt_TKSU 11 | |
146 | #define CP0TCSt_IXMT 10 | |
147 | #define CP0TCSt_TASID 0 | |
148 | int32_t CP0_TCBind; | |
149 | #define CP0TCBd_CurTC 21 | |
150 | #define CP0TCBd_TBE 17 | |
151 | #define CP0TCBd_CurVPE 0 | |
152 | target_ulong CP0_TCHalt; | |
153 | target_ulong CP0_TCContext; | |
154 | target_ulong CP0_TCSchedule; | |
155 | target_ulong CP0_TCScheFBack; | |
156 | int32_t CP0_Debug_tcstatus; | |
d279279e | 157 | target_ulong CP0_UserLocal; |
e97a391d YK |
158 | |
159 | int32_t msacsr; | |
160 | ||
161 | #define MSACSR_FS 24 | |
162 | #define MSACSR_FS_MASK (1 << MSACSR_FS) | |
163 | #define MSACSR_NX 18 | |
164 | #define MSACSR_NX_MASK (1 << MSACSR_NX) | |
165 | #define MSACSR_CEF 2 | |
166 | #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF) | |
167 | #define MSACSR_RM 0 | |
168 | #define MSACSR_RM_MASK (0x3 << MSACSR_RM) | |
169 | #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \ | |
170 | MSACSR_FS_MASK) | |
171 | ||
172 | float_status msa_fp_status; | |
b5dc7732 TS |
173 | }; |
174 | ||
ead9360e TS |
175 | typedef struct CPUMIPSState CPUMIPSState; |
176 | struct CPUMIPSState { | |
b5dc7732 | 177 | TCState active_tc; |
f01be154 | 178 | CPUMIPSFPUContext active_fpu; |
b5dc7732 | 179 | |
ead9360e | 180 | uint32_t current_tc; |
f01be154 | 181 | uint32_t current_fpu; |
36d23958 | 182 | |
e034e2c3 | 183 | uint32_t SEGBITS; |
6d35524c | 184 | uint32_t PABITS; |
e117f526 LA |
185 | #if defined(TARGET_MIPS64) |
186 | # define PABITS_BASE 36 | |
187 | #else | |
188 | # define PABITS_BASE 32 | |
189 | #endif | |
b6d96bed | 190 | target_ulong SEGMask; |
284b731a | 191 | uint64_t PAMask; |
e117f526 | 192 | #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1) |
29929e34 | 193 | |
e97a391d YK |
194 | int32_t msair; |
195 | #define MSAIR_ProcID 8 | |
196 | #define MSAIR_Rev 0 | |
197 | ||
9c2149c8 | 198 | int32_t CP0_Index; |
ead9360e | 199 | /* CP0_MVP* are per MVP registers. */ |
01bc435b YK |
200 | int32_t CP0_VPControl; |
201 | #define CP0VPCtl_DIS 0 | |
9c2149c8 | 202 | int32_t CP0_Random; |
ead9360e TS |
203 | int32_t CP0_VPEControl; |
204 | #define CP0VPECo_YSI 21 | |
205 | #define CP0VPECo_GSI 20 | |
206 | #define CP0VPECo_EXCPT 16 | |
207 | #define CP0VPECo_TE 15 | |
208 | #define CP0VPECo_TargTC 0 | |
209 | int32_t CP0_VPEConf0; | |
210 | #define CP0VPEC0_M 31 | |
211 | #define CP0VPEC0_XTC 21 | |
212 | #define CP0VPEC0_TCS 19 | |
213 | #define CP0VPEC0_SCS 18 | |
214 | #define CP0VPEC0_DSC 17 | |
215 | #define CP0VPEC0_ICS 16 | |
216 | #define CP0VPEC0_MVP 1 | |
217 | #define CP0VPEC0_VPA 0 | |
218 | int32_t CP0_VPEConf1; | |
219 | #define CP0VPEC1_NCX 20 | |
220 | #define CP0VPEC1_NCP2 10 | |
221 | #define CP0VPEC1_NCP1 0 | |
222 | target_ulong CP0_YQMask; | |
223 | target_ulong CP0_VPESchedule; | |
224 | target_ulong CP0_VPEScheFBack; | |
225 | int32_t CP0_VPEOpt; | |
226 | #define CP0VPEOpt_IWX7 15 | |
227 | #define CP0VPEOpt_IWX6 14 | |
228 | #define CP0VPEOpt_IWX5 13 | |
229 | #define CP0VPEOpt_IWX4 12 | |
230 | #define CP0VPEOpt_IWX3 11 | |
231 | #define CP0VPEOpt_IWX2 10 | |
232 | #define CP0VPEOpt_IWX1 9 | |
233 | #define CP0VPEOpt_IWX0 8 | |
234 | #define CP0VPEOpt_DWX7 7 | |
235 | #define CP0VPEOpt_DWX6 6 | |
236 | #define CP0VPEOpt_DWX5 5 | |
237 | #define CP0VPEOpt_DWX4 4 | |
238 | #define CP0VPEOpt_DWX3 3 | |
239 | #define CP0VPEOpt_DWX2 2 | |
240 | #define CP0VPEOpt_DWX1 1 | |
241 | #define CP0VPEOpt_DWX0 0 | |
284b731a LA |
242 | uint64_t CP0_EntryLo0; |
243 | uint64_t CP0_EntryLo1; | |
2fb58b73 LA |
244 | #if defined(TARGET_MIPS64) |
245 | # define CP0EnLo_RI 63 | |
246 | # define CP0EnLo_XI 62 | |
247 | #else | |
248 | # define CP0EnLo_RI 31 | |
249 | # define CP0EnLo_XI 30 | |
250 | #endif | |
01bc435b YK |
251 | int32_t CP0_GlobalNumber; |
252 | #define CP0GN_VPId 0 | |
9c2149c8 | 253 | target_ulong CP0_Context; |
e98c0d17 | 254 | target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; |
9c2149c8 | 255 | int32_t CP0_PageMask; |
7207c7f9 | 256 | int32_t CP0_PageGrain_rw_bitmask; |
9c2149c8 | 257 | int32_t CP0_PageGrain; |
7207c7f9 LA |
258 | #define CP0PG_RIE 31 |
259 | #define CP0PG_XIE 30 | |
e117f526 | 260 | #define CP0PG_ELPA 29 |
92ceb440 | 261 | #define CP0PG_IEC 27 |
cec56a73 JH |
262 | target_ulong CP0_SegCtl0; |
263 | target_ulong CP0_SegCtl1; | |
264 | target_ulong CP0_SegCtl2; | |
265 | #define CP0SC_PA 9 | |
266 | #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA) | |
267 | #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA) | |
268 | #define CP0SC_AM 4 | |
269 | #define CP0SC_AM_MASK (0x7ULL << CP0SC_AM) | |
270 | #define CP0SC_AM_UK 0ULL | |
271 | #define CP0SC_AM_MK 1ULL | |
272 | #define CP0SC_AM_MSK 2ULL | |
273 | #define CP0SC_AM_MUSK 3ULL | |
274 | #define CP0SC_AM_MUSUK 4ULL | |
275 | #define CP0SC_AM_USK 5ULL | |
276 | #define CP0SC_AM_UUSK 7ULL | |
277 | #define CP0SC_EU 3 | |
278 | #define CP0SC_EU_MASK (1ULL << CP0SC_EU) | |
279 | #define CP0SC_C 0 | |
280 | #define CP0SC_C_MASK (0x7ULL << CP0SC_C) | |
281 | #define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ | |
282 | CP0SC_PA_MASK) | |
283 | #define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ | |
284 | CP0SC_PA_1GMASK) | |
285 | #define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16)) | |
286 | #define CP0SC1_XAM 59 | |
287 | #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM) | |
288 | #define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK) | |
289 | #define CP0SC2_XR 56 | |
290 | #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR) | |
291 | #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK) | |
9c2149c8 | 292 | int32_t CP0_Wired; |
ead9360e TS |
293 | int32_t CP0_SRSConf0_rw_bitmask; |
294 | int32_t CP0_SRSConf0; | |
295 | #define CP0SRSC0_M 31 | |
296 | #define CP0SRSC0_SRS3 20 | |
297 | #define CP0SRSC0_SRS2 10 | |
298 | #define CP0SRSC0_SRS1 0 | |
299 | int32_t CP0_SRSConf1_rw_bitmask; | |
300 | int32_t CP0_SRSConf1; | |
301 | #define CP0SRSC1_M 31 | |
302 | #define CP0SRSC1_SRS6 20 | |
303 | #define CP0SRSC1_SRS5 10 | |
304 | #define CP0SRSC1_SRS4 0 | |
305 | int32_t CP0_SRSConf2_rw_bitmask; | |
306 | int32_t CP0_SRSConf2; | |
307 | #define CP0SRSC2_M 31 | |
308 | #define CP0SRSC2_SRS9 20 | |
309 | #define CP0SRSC2_SRS8 10 | |
310 | #define CP0SRSC2_SRS7 0 | |
311 | int32_t CP0_SRSConf3_rw_bitmask; | |
312 | int32_t CP0_SRSConf3; | |
313 | #define CP0SRSC3_M 31 | |
314 | #define CP0SRSC3_SRS12 20 | |
315 | #define CP0SRSC3_SRS11 10 | |
316 | #define CP0SRSC3_SRS10 0 | |
317 | int32_t CP0_SRSConf4_rw_bitmask; | |
318 | int32_t CP0_SRSConf4; | |
319 | #define CP0SRSC4_SRS15 20 | |
320 | #define CP0SRSC4_SRS14 10 | |
321 | #define CP0SRSC4_SRS13 0 | |
9c2149c8 | 322 | int32_t CP0_HWREna; |
c570fd16 | 323 | target_ulong CP0_BadVAddr; |
aea14095 LA |
324 | uint32_t CP0_BadInstr; |
325 | uint32_t CP0_BadInstrP; | |
9c2149c8 TS |
326 | int32_t CP0_Count; |
327 | target_ulong CP0_EntryHi; | |
9456c2fb | 328 | #define CP0EnHi_EHINV 10 |
6ec98bd7 | 329 | target_ulong CP0_EntryHi_ASID_mask; |
9c2149c8 TS |
330 | int32_t CP0_Compare; |
331 | int32_t CP0_Status; | |
6af0bf9c FB |
332 | #define CP0St_CU3 31 |
333 | #define CP0St_CU2 30 | |
334 | #define CP0St_CU1 29 | |
335 | #define CP0St_CU0 28 | |
336 | #define CP0St_RP 27 | |
6ea83fed | 337 | #define CP0St_FR 26 |
6af0bf9c | 338 | #define CP0St_RE 25 |
7a387fff TS |
339 | #define CP0St_MX 24 |
340 | #define CP0St_PX 23 | |
6af0bf9c FB |
341 | #define CP0St_BEV 22 |
342 | #define CP0St_TS 21 | |
343 | #define CP0St_SR 20 | |
344 | #define CP0St_NMI 19 | |
345 | #define CP0St_IM 8 | |
7a387fff TS |
346 | #define CP0St_KX 7 |
347 | #define CP0St_SX 6 | |
348 | #define CP0St_UX 5 | |
623a930e | 349 | #define CP0St_KSU 3 |
6af0bf9c FB |
350 | #define CP0St_ERL 2 |
351 | #define CP0St_EXL 1 | |
352 | #define CP0St_IE 0 | |
9c2149c8 | 353 | int32_t CP0_IntCtl; |
ead9360e | 354 | #define CP0IntCtl_IPTI 29 |
88991299 | 355 | #define CP0IntCtl_IPPCI 26 |
ead9360e | 356 | #define CP0IntCtl_VS 5 |
9c2149c8 | 357 | int32_t CP0_SRSCtl; |
ead9360e TS |
358 | #define CP0SRSCtl_HSS 26 |
359 | #define CP0SRSCtl_EICSS 18 | |
360 | #define CP0SRSCtl_ESS 12 | |
361 | #define CP0SRSCtl_PSS 6 | |
362 | #define CP0SRSCtl_CSS 0 | |
9c2149c8 | 363 | int32_t CP0_SRSMap; |
ead9360e TS |
364 | #define CP0SRSMap_SSV7 28 |
365 | #define CP0SRSMap_SSV6 24 | |
366 | #define CP0SRSMap_SSV5 20 | |
367 | #define CP0SRSMap_SSV4 16 | |
368 | #define CP0SRSMap_SSV3 12 | |
369 | #define CP0SRSMap_SSV2 8 | |
370 | #define CP0SRSMap_SSV1 4 | |
371 | #define CP0SRSMap_SSV0 0 | |
9c2149c8 | 372 | int32_t CP0_Cause; |
7a387fff TS |
373 | #define CP0Ca_BD 31 |
374 | #define CP0Ca_TI 30 | |
375 | #define CP0Ca_CE 28 | |
376 | #define CP0Ca_DC 27 | |
377 | #define CP0Ca_PCI 26 | |
6af0bf9c | 378 | #define CP0Ca_IV 23 |
7a387fff TS |
379 | #define CP0Ca_WP 22 |
380 | #define CP0Ca_IP 8 | |
4de9b249 | 381 | #define CP0Ca_IP_mask 0x0000FF00 |
7a387fff | 382 | #define CP0Ca_EC 2 |
c570fd16 | 383 | target_ulong CP0_EPC; |
9c2149c8 | 384 | int32_t CP0_PRid; |
74dbf824 JH |
385 | target_ulong CP0_EBase; |
386 | target_ulong CP0_EBaseWG_rw_bitmask; | |
387 | #define CP0EBase_WG 11 | |
c870e3f5 | 388 | target_ulong CP0_CMGCRBase; |
9c2149c8 | 389 | int32_t CP0_Config0; |
6af0bf9c FB |
390 | #define CP0C0_M 31 |
391 | #define CP0C0_K23 28 | |
392 | #define CP0C0_KU 25 | |
393 | #define CP0C0_MDU 20 | |
aff2bc6d | 394 | #define CP0C0_MM 18 |
6af0bf9c FB |
395 | #define CP0C0_BM 16 |
396 | #define CP0C0_BE 15 | |
397 | #define CP0C0_AT 13 | |
398 | #define CP0C0_AR 10 | |
399 | #define CP0C0_MT 7 | |
7a387fff | 400 | #define CP0C0_VI 3 |
6af0bf9c | 401 | #define CP0C0_K0 0 |
9c2149c8 | 402 | int32_t CP0_Config1; |
7a387fff | 403 | #define CP0C1_M 31 |
6af0bf9c FB |
404 | #define CP0C1_MMU 25 |
405 | #define CP0C1_IS 22 | |
406 | #define CP0C1_IL 19 | |
407 | #define CP0C1_IA 16 | |
408 | #define CP0C1_DS 13 | |
409 | #define CP0C1_DL 10 | |
410 | #define CP0C1_DA 7 | |
7a387fff TS |
411 | #define CP0C1_C2 6 |
412 | #define CP0C1_MD 5 | |
6af0bf9c FB |
413 | #define CP0C1_PC 4 |
414 | #define CP0C1_WR 3 | |
415 | #define CP0C1_CA 2 | |
416 | #define CP0C1_EP 1 | |
417 | #define CP0C1_FP 0 | |
9c2149c8 | 418 | int32_t CP0_Config2; |
7a387fff TS |
419 | #define CP0C2_M 31 |
420 | #define CP0C2_TU 28 | |
421 | #define CP0C2_TS 24 | |
422 | #define CP0C2_TL 20 | |
423 | #define CP0C2_TA 16 | |
424 | #define CP0C2_SU 12 | |
425 | #define CP0C2_SS 8 | |
426 | #define CP0C2_SL 4 | |
427 | #define CP0C2_SA 0 | |
9c2149c8 | 428 | int32_t CP0_Config3; |
7a387fff | 429 | #define CP0C3_M 31 |
70409e67 | 430 | #define CP0C3_BPG 30 |
c870e3f5 | 431 | #define CP0C3_CMGCR 29 |
e97a391d | 432 | #define CP0C3_MSAP 28 |
aea14095 LA |
433 | #define CP0C3_BP 27 |
434 | #define CP0C3_BI 26 | |
74dbf824 | 435 | #define CP0C3_SC 25 |
70409e67 MR |
436 | #define CP0C3_IPLW 21 |
437 | #define CP0C3_MMAR 18 | |
438 | #define CP0C3_MCU 17 | |
bbfa8f72 | 439 | #define CP0C3_ISA_ON_EXC 16 |
70409e67 | 440 | #define CP0C3_ISA 14 |
d279279e | 441 | #define CP0C3_ULRI 13 |
7207c7f9 | 442 | #define CP0C3_RXI 12 |
70409e67 | 443 | #define CP0C3_DSP2P 11 |
7a387fff TS |
444 | #define CP0C3_DSPP 10 |
445 | #define CP0C3_LPA 7 | |
446 | #define CP0C3_VEIC 6 | |
447 | #define CP0C3_VInt 5 | |
448 | #define CP0C3_SP 4 | |
70409e67 | 449 | #define CP0C3_CDMM 3 |
7a387fff TS |
450 | #define CP0C3_MT 2 |
451 | #define CP0C3_SM 1 | |
452 | #define CP0C3_TL 0 | |
8280b12c MR |
453 | int32_t CP0_Config4; |
454 | int32_t CP0_Config4_rw_bitmask; | |
b4160af1 | 455 | #define CP0C4_M 31 |
9456c2fb | 456 | #define CP0C4_IE 29 |
a0c80608 | 457 | #define CP0C4_AE 28 |
e98c0d17 | 458 | #define CP0C4_KScrExist 16 |
70409e67 MR |
459 | #define CP0C4_MMUExtDef 14 |
460 | #define CP0C4_FTLBPageSize 8 | |
461 | #define CP0C4_FTLBWays 4 | |
462 | #define CP0C4_FTLBSets 0 | |
463 | #define CP0C4_MMUSizeExt 0 | |
8280b12c MR |
464 | int32_t CP0_Config5; |
465 | int32_t CP0_Config5_rw_bitmask; | |
b4dd99a3 PJ |
466 | #define CP0C5_M 31 |
467 | #define CP0C5_K 30 | |
468 | #define CP0C5_CV 29 | |
469 | #define CP0C5_EVA 28 | |
470 | #define CP0C5_MSAEn 27 | |
b00c7218 | 471 | #define CP0C5_XNP 13 |
7c979afd LA |
472 | #define CP0C5_UFE 9 |
473 | #define CP0C5_FRE 8 | |
01bc435b | 474 | #define CP0C5_VP 7 |
faf1f68b | 475 | #define CP0C5_SBRI 6 |
5204ea79 | 476 | #define CP0C5_MVH 5 |
ce9782f4 | 477 | #define CP0C5_LLB 4 |
f6d4dd81 | 478 | #define CP0C5_MRP 3 |
b4dd99a3 PJ |
479 | #define CP0C5_UFR 2 |
480 | #define CP0C5_NFExists 0 | |
e397ee33 TS |
481 | int32_t CP0_Config6; |
482 | int32_t CP0_Config7; | |
f6d4dd81 YK |
483 | uint64_t CP0_MAAR[MIPS_MAAR_MAX]; |
484 | int32_t CP0_MAARI; | |
ead9360e | 485 | /* XXX: Maybe make LLAddr per-TC? */ |
284b731a | 486 | uint64_t lladdr; |
590bc601 PB |
487 | target_ulong llval; |
488 | target_ulong llnewval; | |
489 | target_ulong llreg; | |
284b731a | 490 | uint64_t CP0_LLAddr_rw_bitmask; |
2a6e32dd | 491 | int CP0_LLAddr_shift; |
fd88b6ab TS |
492 | target_ulong CP0_WatchLo[8]; |
493 | int32_t CP0_WatchHi[8]; | |
6ec98bd7 | 494 | #define CP0WH_ASID 16 |
9c2149c8 TS |
495 | target_ulong CP0_XContext; |
496 | int32_t CP0_Framemask; | |
497 | int32_t CP0_Debug; | |
ead9360e | 498 | #define CP0DB_DBD 31 |
6af0bf9c FB |
499 | #define CP0DB_DM 30 |
500 | #define CP0DB_LSNM 28 | |
501 | #define CP0DB_Doze 27 | |
502 | #define CP0DB_Halt 26 | |
503 | #define CP0DB_CNT 25 | |
504 | #define CP0DB_IBEP 24 | |
505 | #define CP0DB_DBEP 21 | |
506 | #define CP0DB_IEXI 20 | |
507 | #define CP0DB_VER 15 | |
508 | #define CP0DB_DEC 10 | |
509 | #define CP0DB_SSt 8 | |
510 | #define CP0DB_DINT 5 | |
511 | #define CP0DB_DIB 4 | |
512 | #define CP0DB_DDBS 3 | |
513 | #define CP0DB_DDBL 2 | |
514 | #define CP0DB_DBp 1 | |
515 | #define CP0DB_DSS 0 | |
c570fd16 | 516 | target_ulong CP0_DEPC; |
9c2149c8 | 517 | int32_t CP0_Performance0; |
0d74a222 LA |
518 | int32_t CP0_ErrCtl; |
519 | #define CP0EC_WST 29 | |
520 | #define CP0EC_SPR 28 | |
521 | #define CP0EC_ITC 26 | |
284b731a | 522 | uint64_t CP0_TagLo; |
9c2149c8 TS |
523 | int32_t CP0_DataLo; |
524 | int32_t CP0_TagHi; | |
525 | int32_t CP0_DataHi; | |
c570fd16 | 526 | target_ulong CP0_ErrorEPC; |
9c2149c8 | 527 | int32_t CP0_DESAVE; |
b5dc7732 TS |
528 | /* We waste some space so we can handle shadow registers like TCs. */ |
529 | TCState tcs[MIPS_SHADOW_SET_MAX]; | |
f01be154 | 530 | CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; |
5cbdb3a3 | 531 | /* QEMU */ |
6af0bf9c | 532 | int error_code; |
aea14095 LA |
533 | #define EXCP_TLB_NOMATCH 0x1 |
534 | #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ | |
6af0bf9c FB |
535 | uint32_t hflags; /* CPU State */ |
536 | /* TMASK defines different execution modes */ | |
42c86612 | 537 | #define MIPS_HFLAG_TMASK 0x1F5807FF |
79ef2c4c | 538 | #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ |
623a930e TS |
539 | /* The KSU flags must be the lowest bits in hflags. The flag order |
540 | must be the same as defined for CP0 Status. This allows to use | |
541 | the bits as the value of mmu_idx. */ | |
79ef2c4c NF |
542 | #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ |
543 | #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ | |
544 | #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ | |
545 | #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ | |
546 | #define MIPS_HFLAG_DM 0x00004 /* Debug mode */ | |
547 | #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ | |
548 | #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ | |
549 | #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ | |
550 | #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ | |
b8aa4598 TS |
551 | /* True if the MIPS IV COP1X instructions can be used. This also |
552 | controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S | |
553 | and RSQRT.D. */ | |
79ef2c4c NF |
554 | #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ |
555 | #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ | |
01f72885 | 556 | #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */ |
79ef2c4c NF |
557 | #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ |
558 | #define MIPS_HFLAG_M16_SHIFT 10 | |
4ad40f36 FB |
559 | /* If translation is interrupted between the branch instruction and |
560 | * the delay slot, record what type of branch it is so that we can | |
561 | * resume translation properly. It might be possible to reduce | |
562 | * this from three bits to two. */ | |
339cd2a8 | 563 | #define MIPS_HFLAG_BMASK_BASE 0x803800 |
79ef2c4c NF |
564 | #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ |
565 | #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ | |
566 | #define MIPS_HFLAG_BL 0x01800 /* Likely branch */ | |
567 | #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ | |
568 | /* Extra flags about the current pending branch. */ | |
b231c103 | 569 | #define MIPS_HFLAG_BMASK_EXT 0x7C000 |
79ef2c4c NF |
570 | #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ |
571 | #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ | |
572 | #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ | |
b231c103 YK |
573 | #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */ |
574 | #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */ | |
79ef2c4c | 575 | #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) |
853c3240 | 576 | /* MIPS DSP resources access. */ |
b231c103 YK |
577 | #define MIPS_HFLAG_DSP 0x080000 /* Enable access to MIPS DSP resources. */ |
578 | #define MIPS_HFLAG_DSPR2 0x100000 /* Enable access to MIPS DSPR2 resources. */ | |
d279279e | 579 | /* Extra flag about HWREna register. */ |
b231c103 | 580 | #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */ |
faf1f68b | 581 | #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */ |
339cd2a8 | 582 | #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */ |
e97a391d | 583 | #define MIPS_HFLAG_MSA 0x1000000 |
7c979afd | 584 | #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */ |
e117f526 | 585 | #define MIPS_HFLAG_ELPA 0x4000000 |
0d74a222 | 586 | #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */ |
42c86612 | 587 | #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */ |
6af0bf9c | 588 | target_ulong btarget; /* Jump / branch target */ |
1ba74fb8 | 589 | target_ulong bcond; /* Branch condition (if needed) */ |
a316d335 | 590 | |
7a387fff TS |
591 | int SYNCI_Step; /* Address step size for SYNCI */ |
592 | int CCRes; /* Cycle count resolution/divisor */ | |
ead9360e TS |
593 | uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ |
594 | uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ | |
e189e748 | 595 | int insn_flags; /* Supported instruction set */ |
7a387fff | 596 | |
1f5c00cf AB |
597 | /* Fields up to this point are cleared by a CPU reset */ |
598 | struct {} end_reset_fields; | |
599 | ||
a316d335 | 600 | CPU_COMMON |
6ae81775 | 601 | |
f0c3c505 | 602 | /* Fields from here on are preserved across CPU reset. */ |
51cc2e78 | 603 | CPUMIPSMVPContext *mvp; |
3c7b48b7 | 604 | #if !defined(CONFIG_USER_ONLY) |
51cc2e78 | 605 | CPUMIPSTLBContext *tlb; |
3c7b48b7 | 606 | #endif |
51cc2e78 | 607 | |
c227f099 | 608 | const mips_def_t *cpu_model; |
33ac7f16 | 609 | void *irq[8]; |
1246b259 | 610 | QEMUTimer *timer; /* Internal timer */ |
34fa7e83 | 611 | MemoryRegion *itc_tag; /* ITC Configuration Tags */ |
89777fd1 | 612 | target_ulong exception_base; /* ExceptionBase input to the core */ |
6af0bf9c FB |
613 | }; |
614 | ||
416bf936 PB |
615 | /** |
616 | * MIPSCPU: | |
617 | * @env: #CPUMIPSState | |
618 | * | |
619 | * A MIPS CPU. | |
620 | */ | |
621 | struct MIPSCPU { | |
622 | /*< private >*/ | |
623 | CPUState parent_obj; | |
624 | /*< public >*/ | |
625 | ||
626 | CPUMIPSState env; | |
627 | }; | |
628 | ||
629 | static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) | |
630 | { | |
631 | return container_of(env, MIPSCPU, env); | |
632 | } | |
633 | ||
634 | #define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e)) | |
635 | ||
636 | #define ENV_OFFSET offsetof(MIPSCPU, env) | |
637 | ||
9a78eead | 638 | void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); |
647de6ca | 639 | |
9467d44c | 640 | #define cpu_signal_handler cpu_mips_signal_handler |
c732abe2 | 641 | #define cpu_list mips_cpu_list |
9467d44c | 642 | |
084d0497 RH |
643 | extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); |
644 | extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); | |
645 | ||
623a930e TS |
646 | /* MMU modes definitions. We carefully match the indices with our |
647 | hflags layout. */ | |
6ebbf390 | 648 | #define MMU_MODE0_SUFFIX _kernel |
623a930e TS |
649 | #define MMU_MODE1_SUFFIX _super |
650 | #define MMU_MODE2_SUFFIX _user | |
42c86612 | 651 | #define MMU_MODE3_SUFFIX _error |
623a930e | 652 | #define MMU_USER_IDX 2 |
b0fc6003 JH |
653 | |
654 | static inline int hflags_mmu_index(uint32_t hflags) | |
655 | { | |
42c86612 JH |
656 | if (hflags & MIPS_HFLAG_ERL) { |
657 | return 3; /* ERL */ | |
658 | } else { | |
659 | return hflags & MIPS_HFLAG_KSU; | |
660 | } | |
b0fc6003 JH |
661 | } |
662 | ||
97ed5ccd | 663 | static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch) |
6ebbf390 | 664 | { |
b0fc6003 | 665 | return hflags_mmu_index(env->hflags); |
6ebbf390 JM |
666 | } |
667 | ||
022c62cb | 668 | #include "exec/cpu-all.h" |
6af0bf9c FB |
669 | |
670 | /* Memory access type : | |
671 | * may be needed for precise access rights control and precise exceptions. | |
672 | */ | |
673 | enum { | |
674 | /* 1 bit to define user level / supervisor access */ | |
675 | ACCESS_USER = 0x00, | |
676 | ACCESS_SUPER = 0x01, | |
677 | /* 1 bit to indicate direction */ | |
678 | ACCESS_STORE = 0x02, | |
679 | /* Type of instruction that generated the access */ | |
680 | ACCESS_CODE = 0x10, /* Code fetch access */ | |
681 | ACCESS_INT = 0x20, /* Integer load/store access */ | |
682 | ACCESS_FLOAT = 0x30, /* floating point load/store access */ | |
683 | }; | |
684 | ||
685 | /* Exceptions */ | |
686 | enum { | |
687 | EXCP_NONE = -1, | |
688 | EXCP_RESET = 0, | |
689 | EXCP_SRESET, | |
690 | EXCP_DSS, | |
691 | EXCP_DINT, | |
14e51cc7 TS |
692 | EXCP_DDBL, |
693 | EXCP_DDBS, | |
6af0bf9c FB |
694 | EXCP_NMI, |
695 | EXCP_MCHECK, | |
14e51cc7 | 696 | EXCP_EXT_INTERRUPT, /* 8 */ |
6af0bf9c | 697 | EXCP_DFWATCH, |
14e51cc7 | 698 | EXCP_DIB, |
6af0bf9c FB |
699 | EXCP_IWATCH, |
700 | EXCP_AdEL, | |
701 | EXCP_AdES, | |
702 | EXCP_TLBF, | |
703 | EXCP_IBE, | |
14e51cc7 | 704 | EXCP_DBp, /* 16 */ |
6af0bf9c | 705 | EXCP_SYSCALL, |
14e51cc7 | 706 | EXCP_BREAK, |
4ad40f36 | 707 | EXCP_CpU, |
6af0bf9c FB |
708 | EXCP_RI, |
709 | EXCP_OVERFLOW, | |
710 | EXCP_TRAP, | |
5a5012ec | 711 | EXCP_FPE, |
14e51cc7 | 712 | EXCP_DWATCH, /* 24 */ |
6af0bf9c FB |
713 | EXCP_LTLBL, |
714 | EXCP_TLBL, | |
715 | EXCP_TLBS, | |
716 | EXCP_DBE, | |
ead9360e | 717 | EXCP_THREAD, |
14e51cc7 TS |
718 | EXCP_MDMX, |
719 | EXCP_C2E, | |
720 | EXCP_CACHE, /* 32 */ | |
853c3240 | 721 | EXCP_DSPDIS, |
e97a391d YK |
722 | EXCP_MSADIS, |
723 | EXCP_MSAFPE, | |
92ceb440 LA |
724 | EXCP_TLBXI, |
725 | EXCP_TLBRI, | |
14e51cc7 | 726 | |
92ceb440 | 727 | EXCP_LAST = EXCP_TLBRI, |
6af0bf9c | 728 | }; |
590bc601 PB |
729 | /* Dummy exception for conditional stores. */ |
730 | #define EXCP_SC 0x100 | |
6af0bf9c | 731 | |
f249412c | 732 | /* |
26aa3d9a | 733 | * This is an internally generated WAKE request line. |
f249412c EI |
734 | * It is driven by the CPU itself. Raised when the MT |
735 | * block wants to wake a VPE from an inactive state and | |
736 | * cleared when VPE goes from active to inactive. | |
737 | */ | |
738 | #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 | |
739 | ||
388bb21a | 740 | int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); |
6af0bf9c | 741 | |
c4c8146c | 742 | #define cpu_init(cpu_model) cpu_generic_init(TYPE_MIPS_CPU, cpu_model) |
a7519f2b IM |
743 | |
744 | #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU | |
745 | #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX | |
0dacec87 | 746 | #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU |
a7519f2b IM |
747 | |
748 | bool cpu_supports_cps_smp(const char *cpu_type); | |
749 | bool cpu_supports_isa(const char *cpu_type, unsigned int isa); | |
89777fd1 | 750 | void cpu_set_exception_base(int vp_index, target_ulong address); |
30bf942d | 751 | |
5dc5d9f0 | 752 | /* mips_int.c */ |
7db13fae | 753 | void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); |
5dc5d9f0 | 754 | |
f9480ffc | 755 | /* helper.c */ |
1239b472 | 756 | target_ulong exception_resume_pc (CPUMIPSState *env); |
f9480ffc | 757 | |
599bc5e8 AM |
758 | static inline void restore_snan_bit_mode(CPUMIPSState *env) |
759 | { | |
760 | set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, | |
761 | &env->active_fpu.fp_status); | |
762 | } | |
763 | ||
7db13fae | 764 | static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, |
89fee74a | 765 | target_ulong *cs_base, uint32_t *flags) |
6b917547 AL |
766 | { |
767 | *pc = env->active_tc.PC; | |
768 | *cs_base = 0; | |
d279279e PJ |
769 | *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | |
770 | MIPS_HFLAG_HWRENA_ULR); | |
6b917547 AL |
771 | } |
772 | ||
07f5a258 | 773 | #endif /* MIPS_CPU_H */ |