[mirror_qemu.git] / target / mips / machine.c

#include "qemu/osdep.h"
#include "cpu.h"
#include "internal.h"
#include "hw/hw.h"
#include "migration/cpu.h"

static int cpu_post_load(void *opaque, int version_id)
{
    MIPSCPU *cpu = opaque;
    CPUMIPSState *env = &cpu->env;

    restore_fp_status(env);
    restore_msa_fp_status(env);
    compute_hflags(env);
    restore_pamask(env);

    return 0;
}

/* FPU state */

static int get_fpr(QEMUFile *f, void *pv, size_t size,
                   const VMStateField *field)
{
    int i;
    fpr_t *v = pv;
    /* Restore entire MSA vector register */
    for (i = 0; i < MSA_WRLEN/64; i++) {
        qemu_get_sbe64s(f, &v->wr.d[i]);
    }
    return 0;
}

static int put_fpr(QEMUFile *f, void *pv, size_t size,
                   const VMStateField *field, QJSON *vmdesc)
{
    int i;
    fpr_t *v = pv;
    /* Save entire MSA vector register */
    for (i = 0; i < MSA_WRLEN/64; i++) {
        qemu_put_sbe64s(f, &v->wr.d[i]);
    }

    return 0;
}

const VMStateInfo vmstate_info_fpr = {
    .name = "fpr",
    .get  = get_fpr,
    .put  = put_fpr,
};

#define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v)                     \
    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t)

#define VMSTATE_FPR_ARRAY(_f, _s, _n)                           \
    VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)

static VMStateField vmstate_fpu_fields[] = {
    VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
    VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
    VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
    VMSTATE_END_OF_LIST()
};

const VMStateDescription vmstate_fpu = {
    .name = "cpu/fpu",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = vmstate_fpu_fields
};

const VMStateDescription vmstate_inactive_fpu = {
    .name = "cpu/inactive_fpu",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = vmstate_fpu_fields
};

/* TC state */

static VMStateField vmstate_tc_fields[] = {
    VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
    VMSTATE_UINTTL(PC, TCState),
    VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
    VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
    VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
    VMSTATE_UINTTL(DSPControl, TCState),
    VMSTATE_INT32(CP0_TCStatus, TCState),
    VMSTATE_INT32(CP0_TCBind, TCState),
    VMSTATE_UINTTL(CP0_TCHalt, TCState),
    VMSTATE_UINTTL(CP0_TCContext, TCState),
    VMSTATE_UINTTL(CP0_TCSchedule, TCState),
    VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
    VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
    VMSTATE_UINTTL(CP0_UserLocal, TCState),
    VMSTATE_INT32(msacsr, TCState),
    VMSTATE_END_OF_LIST()
};

const VMStateDescription vmstate_tc = {
    .name = "cpu/tc",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = vmstate_tc_fields
};

const VMStateDescription vmstate_inactive_tc = {
    .name = "cpu/inactive_tc",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = vmstate_tc_fields
};

/* MVP state */

const VMStateDescription vmstate_mvp = {
    .name = "cpu/mvp",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),
        VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
        VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext),
        VMSTATE_END_OF_LIST()
    }
};

/* TLB state */

static int get_tlb(QEMUFile *f, void *pv, size_t size,
                   const VMStateField *field)
{
    r4k_tlb_t *v = pv;
    uint16_t flags;

    qemu_get_betls(f, &v->VPN);
    qemu_get_be32s(f, &v->PageMask);
    qemu_get_be16s(f, &v->ASID);
    qemu_get_be16s(f, &flags);
    v->G = (flags >> 10) & 1;
    v->C0 = (flags >> 7) & 3;
    v->C1 = (flags >> 4) & 3;
    v->V0 = (flags >> 3) & 1;
    v->V1 = (flags >> 2) & 1;
    v->D0 = (flags >> 1) & 1;
    v->D1 = (flags >> 0) & 1;
    v->EHINV = (flags >> 15) & 1;
    v->RI1 = (flags >> 14) & 1;
    v->RI0 = (flags >> 13) & 1;
    v->XI1 = (flags >> 12) & 1;
    v->XI0 = (flags >> 11) & 1;
    qemu_get_be64s(f, &v->PFN[0]);
    qemu_get_be64s(f, &v->PFN[1]);

    return 0;
}

static int put_tlb(QEMUFile *f, void *pv, size_t size,
                   const VMStateField *field, QJSON *vmdesc)
{
    r4k_tlb_t *v = pv;

    uint16_t asid = v->ASID;
    uint16_t flags = ((v->EHINV << 15) |
                      (v->RI1 << 14) |
                      (v->RI0 << 13) |
                      (v->XI1 << 12) |
                      (v->XI0 << 11) |
                      (v->G << 10) |
                      (v->C0 << 7) |
                      (v->C1 << 4) |
                      (v->V0 << 3) |
                      (v->V1 << 2) |
                      (v->D0 << 1) |
                      (v->D1 << 0));

    qemu_put_betls(f, &v->VPN);
    qemu_put_be32s(f, &v->PageMask);
    qemu_put_be16s(f, &asid);
    qemu_put_be16s(f, &flags);
    qemu_put_be64s(f, &v->PFN[0]);
    qemu_put_be64s(f, &v->PFN[1]);

    return 0;
}

const VMStateInfo vmstate_info_tlb = {
    .name = "tlb_entry",
    .get  = get_tlb,
    .put  = put_tlb,
};

#define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v)                     \
    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t)

#define VMSTATE_TLB_ARRAY(_f, _s, _n)                           \
    VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0)

const VMStateDescription vmstate_tlb = {
    .name = "cpu/tlb",
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
        VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
        VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX),
        VMSTATE_END_OF_LIST()
    }
};

/* MIPS CPU state */

const VMStateDescription vmstate_mips_cpu = {
    .name = "cpu",
    .version_id = 18,
    .minimum_version_id = 18,
    .post_load = cpu_post_load,
    .fields = (VMStateField[]) {
        /* Active TC */
        VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),

        /* Active FPU */
        VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,
                       CPUMIPSFPUContext),

        /* MVP */
        VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp,
                               CPUMIPSMVPContext),

        /* TLB */
        VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb,
                               CPUMIPSTLBContext),

        /* CPU metastate */
        VMSTATE_UINT32(env.current_tc, MIPSCPU),
        VMSTATE_UINT32(env.current_fpu, MIPSCPU),
        VMSTATE_INT32(env.error_code, MIPSCPU),
        VMSTATE_UINTTL(env.btarget, MIPSCPU),
        VMSTATE_UINTTL(env.bcond, MIPSCPU),

        /* Remaining CP0 registers */
        VMSTATE_INT32(env.CP0_Index, MIPSCPU),
        VMSTATE_INT32(env.CP0_Random, MIPSCPU),
        VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
        VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
        VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU),
        VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
        VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
        VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
        VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU),
        VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
        VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU),
        VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
        VMSTATE_INT32(env.CP0_PWCtl, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
        VMSTATE_INT32(env.CP0_HWREna, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
        VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
        VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
        VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
        VMSTATE_INT32(env.CP0_Count, MIPSCPU),
        VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU),
        VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2),
        VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
        VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
        VMSTATE_INT32(env.CP0_Status, MIPSCPU),
        VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU),
        VMSTATE_INT32(env.CP0_Cause, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
        VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_EBase, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
        VMSTATE_UINT64(env.CP0_LLAddr, MIPSCPU),
        VMSTATE_UINT64_ARRAY(env.CP0_MAAR, MIPSCPU, MIPS_MAAR_MAX),
        VMSTATE_INT32(env.CP0_MAARI, MIPSCPU),
        VMSTATE_UINTTL(env.lladdr, MIPSCPU),
        VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
        VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
        VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
        VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
        VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
        VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
        VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU),
        VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
        VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
        VMSTATE_INT32(env.CP0_DataHi, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU),
        VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),
        VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM),

        /* Inactive TC */
        VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
                             vmstate_inactive_tc, TCState),
        VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1,
                             vmstate_inactive_fpu, CPUMIPSFPUContext),

        VMSTATE_END_OF_LIST()
    },
};
Commit	Line	Data
c684822a	1	#include "qemu/osdep.h"
33c11879	2	#include "cpu.h"
26aa3d9a	3	#include "internal.h"
8dd3dca3	4	#include "hw/hw.h"
1e00b8d5	5	#include "migration/cpu.h"
33a84765	6
64451111 LA	7	static int cpu_post_load(void *opaque, int version_id)
	8	{
	9	MIPSCPU *cpu = opaque;
	10	CPUMIPSState *env = &cpu->env;
	11
	12	restore_fp_status(env);
	13	restore_msa_fp_status(env);
	14	compute_hflags(env);
e117f526	15	restore_pamask(env);
64451111 LA	16
	17	return 0;
	18	}
	19
04cd7962 LA	20	/* FPU state */
04cd7962 LA	21
03fee66f MAL	22	static int get_fpr(QEMUFile f, void pv, size_t size,
03fee66f MAL	23	const VMStateField *field)
33a84765	24	{
64451111	25	int i;
04cd7962	26	fpr_t *v = pv;
64451111 LA	27	/* Restore entire MSA vector register */
	28	for (i = 0; i < MSA_WRLEN/64; i++) {
	29	qemu_get_sbe64s(f, &v->wr.d[i]);
	30	}
04cd7962	31	return 0;
33a84765 TS	32	}
33a84765 TS	33
03fee66f MAL	34	static int put_fpr(QEMUFile f, void pv, size_t size,
03fee66f MAL	35	const VMStateField field, QJSON vmdesc)
33a84765	36	{
64451111	37	int i;
04cd7962	38	fpr_t *v = pv;
64451111 LA	39	/* Save entire MSA vector register */
	40	for (i = 0; i < MSA_WRLEN/64; i++) {
	41	qemu_put_sbe64s(f, &v->wr.d[i]);
	42	}
2c21ee76 JD	43
2c21ee76 JD	44	return 0;
33a84765 TS	45	}
33a84765 TS	46
04cd7962 LA	47	const VMStateInfo vmstate_info_fpr = {
	48	.name = "fpr",
	49	.get = get_fpr,
	50	.put = put_fpr,
	51	};
	52
	53	#define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \
	54	VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t)
	55
	56	#define VMSTATE_FPR_ARRAY(_f, _s, _n) \
	57	VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
	58
	59	static VMStateField vmstate_fpu_fields[] = {
	60	VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
04cd7962 LA	61	VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
	62	VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
	63	VMSTATE_END_OF_LIST()
	64	};
	65
	66	const VMStateDescription vmstate_fpu = {
	67	.name = "cpu/fpu",
	68	.version_id = 1,
	69	.minimum_version_id = 1,
	70	.fields = vmstate_fpu_fields
	71	};
	72
	73	const VMStateDescription vmstate_inactive_fpu = {
	74	.name = "cpu/inactive_fpu",
	75	.version_id = 1,
	76	.minimum_version_id = 1,
	77	.fields = vmstate_fpu_fields
	78	};
33a84765	79
04cd7962 LA	80	/* TC state */
	81
	82	static VMStateField vmstate_tc_fields[] = {
	83	VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
	84	VMSTATE_UINTTL(PC, TCState),
	85	VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
	86	VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
	87	VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
	88	VMSTATE_UINTTL(DSPControl, TCState),
	89	VMSTATE_INT32(CP0_TCStatus, TCState),
	90	VMSTATE_INT32(CP0_TCBind, TCState),
	91	VMSTATE_UINTTL(CP0_TCHalt, TCState),
	92	VMSTATE_UINTTL(CP0_TCContext, TCState),
	93	VMSTATE_UINTTL(CP0_TCSchedule, TCState),
	94	VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
	95	VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
	96	VMSTATE_UINTTL(CP0_UserLocal, TCState),
64451111	97	VMSTATE_INT32(msacsr, TCState),
04cd7962 LA	98	VMSTATE_END_OF_LIST()
	99	};
	100
	101	const VMStateDescription vmstate_tc = {
	102	.name = "cpu/tc",
	103	.version_id = 1,
	104	.minimum_version_id = 1,
	105	.fields = vmstate_tc_fields
	106	};
	107
	108	const VMStateDescription vmstate_inactive_tc = {
	109	.name = "cpu/inactive_tc",
	110	.version_id = 1,
	111	.minimum_version_id = 1,
	112	.fields = vmstate_tc_fields
	113	};
	114
	115	/* MVP state */
	116
	117	const VMStateDescription vmstate_mvp = {
	118	.name = "cpu/mvp",
	119	.version_id = 1,
	120	.minimum_version_id = 1,
	121	.fields = (VMStateField[]) {
	122	VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),
	123	VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
	124	VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext),
	125	VMSTATE_END_OF_LIST()
460c81f1	126	}
04cd7962	127	};
33a84765	128
04cd7962	129	/* TLB state */
33a84765	130
03fee66f MAL	131	static int get_tlb(QEMUFile f, void pv, size_t size,
03fee66f MAL	132	const VMStateField *field)
33a84765	133	{
04cd7962 LA	134	r4k_tlb_t *v = pv;
	135	uint16_t flags;
	136
	137	qemu_get_betls(f, &v->VPN);
	138	qemu_get_be32s(f, &v->PageMask);
2d72e7b0	139	qemu_get_be16s(f, &v->ASID);
04cd7962 LA	140	qemu_get_be16s(f, &flags);
	141	v->G = (flags >> 10) & 1;
	142	v->C0 = (flags >> 7) & 3;
	143	v->C1 = (flags >> 4) & 3;
	144	v->V0 = (flags >> 3) & 1;
	145	v->V1 = (flags >> 2) & 1;
	146	v->D0 = (flags >> 1) & 1;
	147	v->D1 = (flags >> 0) & 1;
	148	v->EHINV = (flags >> 15) & 1;
	149	v->RI1 = (flags >> 14) & 1;
	150	v->RI0 = (flags >> 13) & 1;
	151	v->XI1 = (flags >> 12) & 1;
	152	v->XI0 = (flags >> 11) & 1;
284b731a LA	153	qemu_get_be64s(f, &v->PFN[0]);
284b731a LA	154	qemu_get_be64s(f, &v->PFN[1]);
04cd7962 LA	155
04cd7962 LA	156	return 0;
33a84765 TS	157	}
33a84765 TS	158
03fee66f MAL	159	static int put_tlb(QEMUFile f, void pv, size_t size,
03fee66f MAL	160	const VMStateField field, QJSON vmdesc)
33a84765	161	{
04cd7962 LA	162	r4k_tlb_t *v = pv;
04cd7962 LA	163
2d72e7b0	164	uint16_t asid = v->ASID;
04cd7962 LA	165	uint16_t flags = ((v->EHINV << 15) \|
	166	(v->RI1 << 14) \|
	167	(v->RI0 << 13) \|
	168	(v->XI1 << 12) \|
	169	(v->XI0 << 11) \|
	170	(v->G << 10) \|
	171	(v->C0 << 7) \|
	172	(v->C1 << 4) \|
	173	(v->V0 << 3) \|
	174	(v->V1 << 2) \|
	175	(v->D0 << 1) \|
	176	(v->D1 << 0));
	177
	178	qemu_put_betls(f, &v->VPN);
	179	qemu_put_be32s(f, &v->PageMask);
2d72e7b0	180	qemu_put_be16s(f, &asid);
04cd7962	181	qemu_put_be16s(f, &flags);
284b731a LA	182	qemu_put_be64s(f, &v->PFN[0]);
284b731a LA	183	qemu_put_be64s(f, &v->PFN[1]);
2c21ee76 JD	184
2c21ee76 JD	185	return 0;
8dd3dca3 AJ	186	}
8dd3dca3 AJ	187
04cd7962 LA	188	const VMStateInfo vmstate_info_tlb = {
	189	.name = "tlb_entry",
	190	.get = get_tlb,
	191	.put = put_tlb,
	192	};
33a84765	193
04cd7962 LA	194	#define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v) \
04cd7962 LA	195	VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t)
33a84765	196
04cd7962 LA	197	#define VMSTATE_TLB_ARRAY(_f, _s, _n) \
04cd7962 LA	198	VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0)
33a84765	199
04cd7962 LA	200	const VMStateDescription vmstate_tlb = {
04cd7962 LA	201	.name = "cpu/tlb",
2d72e7b0 PB	202	.version_id = 2,
2d72e7b0 PB	203	.minimum_version_id = 2,
04cd7962 LA	204	.fields = (VMStateField[]) {
	205	VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
	206	VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
	207	VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX),
	208	VMSTATE_END_OF_LIST()
460c81f1	209	}
04cd7962	210	};
33a84765	211
04cd7962	212	/* MIPS CPU state */
33a84765	213
04cd7962 LA	214	const VMStateDescription vmstate_mips_cpu = {
04cd7962 LA	215	.name = "cpu",
c7c7e1e9 LA	216	.version_id = 18,
c7c7e1e9 LA	217	.minimum_version_id = 18,
64451111	218	.post_load = cpu_post_load,
04cd7962 LA	219	.fields = (VMStateField[]) {
	220	/* Active TC */
	221	VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),
	222
	223	/* Active FPU */
	224	VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,
	225	CPUMIPSFPUContext),
	226
	227	/* MVP */
	228	VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp,
	229	CPUMIPSMVPContext),
	230
	231	/* TLB */
	232	VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb,
	233	CPUMIPSTLBContext),
	234
	235	/* CPU metastate */
	236	VMSTATE_UINT32(env.current_tc, MIPSCPU),
	237	VMSTATE_UINT32(env.current_fpu, MIPSCPU),
	238	VMSTATE_INT32(env.error_code, MIPSCPU),
04cd7962 LA	239	VMSTATE_UINTTL(env.btarget, MIPSCPU),
	240	VMSTATE_UINTTL(env.bcond, MIPSCPU),
	241
	242	/* Remaining CP0 registers */
	243	VMSTATE_INT32(env.CP0_Index, MIPSCPU),
	244	VMSTATE_INT32(env.CP0_Random, MIPSCPU),
	245	VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
	246	VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
	247	VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU),
	248	VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU),
	249	VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU),
	250	VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU),
	251	VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
284b731a LA	252	VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
284b731a LA	253	VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
04cd7962	254	VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
3ef521ee	255	VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU),
04cd7962 LA	256	VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
04cd7962 LA	257	VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
cec56a73 JH	258	VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU),
	259	VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU),
	260	VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU),
5e31fdd5	261	VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU),
fa75ad14	262	VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU),
20b28ebc	263	VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU),
04cd7962	264	VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
103be64c	265	VMSTATE_INT32(env.CP0_PWCtl, MIPSCPU),
04cd7962 LA	266	VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
	267	VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
	268	VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
	269	VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
	270	VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
	271	VMSTATE_INT32(env.CP0_HWREna, MIPSCPU),
	272	VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
	273	VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
	274	VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
25beba9b	275	VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
04cd7962	276	VMSTATE_INT32(env.CP0_Count, MIPSCPU),
167db30e YK	277	VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU),
167db30e YK	278	VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2),
04cd7962 LA	279	VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
	280	VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
	281	VMSTATE_INT32(env.CP0_Status, MIPSCPU),
	282	VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU),
	283	VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU),
	284	VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU),
	285	VMSTATE_INT32(env.CP0_Cause, MIPSCPU),
	286	VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
	287	VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
74dbf824	288	VMSTATE_UINTTL(env.CP0_EBase, MIPSCPU),
04cd7962 LA	289	VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
	290	VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
	291	VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
	292	VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
	293	VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
	294	VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
c7c7e1e9	295	VMSTATE_UINT64(env.CP0_LLAddr, MIPSCPU),
f6d4dd81 YK	296	VMSTATE_UINT64_ARRAY(env.CP0_MAAR, MIPSCPU, MIPS_MAAR_MAX),
f6d4dd81 YK	297	VMSTATE_INT32(env.CP0_MAARI, MIPSCPU),
c7c7e1e9	298	VMSTATE_UINTTL(env.lladdr, MIPSCPU),
04cd7962 LA	299	VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
	300	VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
	301	VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
	302	VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
	303	VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
	304	VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
	305	VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
284b731a	306	VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU),
04cd7962 LA	307	VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
	308	VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
	309	VMSTATE_INT32(env.CP0_DataHi, MIPSCPU),
	310	VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU),
	311	VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),
	312	VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM),
	313
	314	/* Inactive TC */
	315	VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
	316	vmstate_inactive_tc, TCState),
	317	VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1,
	318	vmstate_inactive_fpu, CPUMIPSFPUContext),
	319
	320	VMSTATE_END_OF_LIST()
	321	},
	322	};