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[mirror_qemu.git] / target / ppc / kvm.c
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d76d1650
AJ		 1/*
2 * PowerPC implementation of KVM hooks
3 *
4 * Copyright IBM Corp. 2007
90dc8812 5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
d76d1650
AJ		 6 *
7 * Authors:
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
14 *
15 */
16
0d75590d 17#include "qemu/osdep.h"
eadaada1 18#include <dirent.h>
d76d1650 19#include <sys/ioctl.h>
4656e1f0 20#include <sys/vfs.h>
d76d1650
AJ		 21
22#include <linux/kvm.h>
23
30f4b05b 24#include "qapi/error.h"
072ed5f2 25#include "qemu/error-report.h"
33c11879 26#include "cpu.h"
715d4b96 27#include "cpu-models.h"
1de7afc9 28#include "qemu/timer.h"
b3946626 29#include "sysemu/hw_accel.h"
d76d1650 30#include "kvm_ppc.h"
9c17d615
PB		 31#include "sysemu/cpus.h"
32#include "sysemu/device_tree.h"
d5aea6f3 33#include "mmu-hash64.h"
d76d1650 34
f61b4bed 35#include "hw/sysbus.h"
0d09e41a 36#include "hw/ppc/spapr.h"
7ebaf795 37#include "hw/ppc/spapr_cpu_core.h"
650d103d 38#include "hw/hw.h"
98a8b524 39#include "hw/ppc/ppc.h"
ca77ee28 40#include "migration/qemu-file-types.h"
31f2cb8f 41#include "sysemu/watchdog.h"
b36f100e 42#include "trace.h"
88365d17 43#include "exec/gdbstub.h"
4c663752 44#include "exec/memattrs.h"
9c607668 45#include "exec/ram_addr.h"
2d103aae 46#include "sysemu/hostmem.h"
f348b6d1 47#include "qemu/cutils.h"
db725815 48#include "qemu/main-loop.h"
9c607668 49#include "qemu/mmap-alloc.h"
f3d9f303 50#include "elf.h"
c64abd1f 51#include "sysemu/kvm_int.h"
f61b4bed 52
eadaada1
AG		 53#define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
54
6e0552a3
FR		 55#define DEBUG_RETURN_GUEST 0
56#define DEBUG_RETURN_GDB 1
57
94a8d39a
JK		 58const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
59 KVM_CAP_LAST_INFO
60};
61
c995e942 62static int cap_interrupt_unset;
90dc8812 63static int cap_segstate;
90dc8812 64static int cap_booke_sregs;
e97c3636 65static int cap_ppc_smt;
fa98fbfc 66static int cap_ppc_smt_possible;
0f5cb298 67static int cap_spapr_tce;
d6ee2a7c 68static int cap_spapr_tce_64;
da95324e 69static int cap_spapr_multitce;
9bb62a07 70static int cap_spapr_vfio;
f1af19d7 71static int cap_hior;
d67d40ea 72static int cap_one_reg;
3b961124 73static int cap_epr;
31f2cb8f 74static int cap_ppc_watchdog;
9b00ea49 75static int cap_papr;
e68cb8b4 76static int cap_htab_fd;
87a91de6 77static int cap_fixup_hcalls;
bac3bf28 78static int cap_htm; /* Hardware transactional memory support */
cf1c4cce
SB		 79static int cap_mmu_radix;
80static int cap_mmu_hash_v3;
38afd772 81static int cap_xive;
b55d295e 82static int cap_resize_hpt;
c363a37a 83static int cap_ppc_pvr_compat;
8acc2ae5
SJS		 84static int cap_ppc_safe_cache;
85static int cap_ppc_safe_bounds_check;
86static int cap_ppc_safe_indirect_branch;
8ff43ee4 87static int cap_ppc_count_cache_flush_assist;
b9a477b7 88static int cap_ppc_nested_kvm_hv;
7d050527 89static int cap_large_decr;
ec010c00 90static int cap_fwnmi;
82123b75 91static int cap_rpt_invalidate;
fc87e185 92
3c902d44
BB		 93static uint32_t debug_inst_opcode;
94
c995e942
DG		 95/*
96 * Check whether we are running with KVM-PR (instead of KVM-HV). This
96c9cff0
TH		 97 * should only be used for fallback tests - generally we should use
98 * explicit capabilities for the features we want, rather than
c995e942
DG		 99 * assuming what is/isn't available depending on the KVM variant.
100 */
96c9cff0
TH		 101static bool kvmppc_is_pr(KVMState *ks)
102{
103 /* Assume KVM-PR if the GET_PVINFO capability is available */
70a0c19e 104 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0;
96c9cff0
TH		 105}
106
165dc3ed 107static int kvm_ppc_register_host_cpu_type(void);
8acc2ae5 108static void kvmppc_get_cpu_characteristics(KVMState *s);
7d050527 109static int kvmppc_get_dec_bits(void);
5ba4576b 110
b16565b3 111int kvm_arch_init(MachineState *ms, KVMState *s)
d76d1650 112{
fc87e185 113 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
90dc8812 114 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
90dc8812 115 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
6977afda 116 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE);
0f5cb298 117 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
d6ee2a7c 118 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64);
da95324e 119 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE);
9ded780c 120 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO);
d67d40ea 121 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
f1af19d7 122 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
3b961124 123 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
31f2cb8f 124 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG);
c995e942
DG		 125 /*
126 * Note: we don't set cap_papr here, because this capability is
127 * only activated after this by kvmppc_set_papr()
128 */
6977afda 129 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD);
87a91de6 130 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL);
fa98fbfc 131 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT);
bac3bf28 132 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM);
cf1c4cce
SB		 133 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX);
134 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
38afd772 135 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE);
b55d295e 136 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT);
8acc2ae5 137 kvmppc_get_cpu_characteristics(s);
b9a477b7 138 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV);
7d050527 139 cap_large_decr = kvmppc_get_dec_bits();
ec010c00 140 cap_fwnmi = kvm_vm_check_extension(s, KVM_CAP_PPC_FWNMI);
c363a37a
DHB		 141 /*
142 * Note: setting it to false because there is not such capability
143 * in KVM at this moment.
144 *
145 * TODO: call kvm_vm_check_extension() with the right capability
c995e942
DG		 146 * after the kernel starts implementing it.
147 */
c363a37a 148 cap_ppc_pvr_compat = false;
fc87e185 149
1e8f51e8
SB		 150 if (!kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL)) {
151 error_report("KVM: Host kernel doesn't have level irq capability");
152 exit(1);
fc87e185
AG		 153 }
154
82123b75 155 cap_rpt_invalidate = kvm_vm_check_extension(s, KVM_CAP_PPC_RPT_INVALIDATE);
165dc3ed 156 kvm_ppc_register_host_cpu_type();
5ba4576b 157
d76d1650
AJ		 158 return 0;
159}
160
4376c40d 161int kvm_arch_irqchip_create(KVMState *s)
d525ffab
PB		 162{
163 return 0;
164}
165
1bc22652 166static int kvm_arch_sync_sregs(PowerPCCPU *cpu)
d76d1650 167{
1bc22652
AF		 168 CPUPPCState *cenv = &cpu->env;
169 CPUState *cs = CPU(cpu);
861bbc80 170 struct kvm_sregs sregs;
5666ca4a
SW		 171 int ret;
172
173 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
c995e942
DG		 174 /*
175 * What we're really trying to say is "if we're on BookE, we
176 * use the native PVR for now". This is the only sane way to
177 * check it though, so we potentially confuse users that they
178 * can run BookE guests on BookS. Let's hope nobody dares
179 * enough :)
180 */
5666ca4a
SW		 181 return 0;
182 } else {
90dc8812 183 if (!cap_segstate) {
64e07be5
AG		 184 fprintf(stderr, "kvm error: missing PVR setting capability\n");
185 return -ENOSYS;
5666ca4a 186 }
5666ca4a
SW		 187 }
188
1bc22652 189 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);
5666ca4a
SW		 190 if (ret) {
191 return ret;
192 }
861bbc80
AG		 193
194 sregs.pvr = cenv->spr[SPR_PVR];
1bc22652 195 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);
5666ca4a
SW		 196}
197
93dd5e85 198/* Set up a shared TLB array with KVM */
1bc22652 199static int kvm_booke206_tlb_init(PowerPCCPU *cpu)
93dd5e85 200{
1bc22652
AF		 201 CPUPPCState *env = &cpu->env;
202 CPUState *cs = CPU(cpu);
93dd5e85
SW		 203 struct kvm_book3e_206_tlb_params params = {};
204 struct kvm_config_tlb cfg = {};
93dd5e85
SW		 205 unsigned int entries = 0;
206 int ret, i;
207
208 if (!kvm_enabled() ||
a60f24b5 209 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) {
93dd5e85
SW		 210 return 0;
211 }
212
213 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);
214
215 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
216 params.tlb_sizes[i] = booke206_tlb_size(env, i);
217 params.tlb_ways[i] = booke206_tlb_ways(env, i);
218 entries += params.tlb_sizes[i];
219 }
220
221 assert(entries == env->nb_tlb);
222 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));
223
224 env->tlb_dirty = true;
225
226 cfg.array = (uintptr_t)env->tlb.tlbm;
227 cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
228 cfg.params = (uintptr_t)&params;
229 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
230
48add816 231 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg);
93dd5e85
SW		 232 if (ret < 0) {
233 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
234 __func__, strerror(-ret));
235 return ret;
236 }
237
238 env->kvm_sw_tlb = true;
239 return 0;
240}
241
4656e1f0
BH		 242
243#if defined(TARGET_PPC64)
ab256960 244static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp)
4656e1f0 245{
71d0f1ea 246 int ret;
a60f24b5 247
ab256960
GK		 248 assert(kvm_state != NULL);
249
250 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) {
71d0f1ea
GK		 251 error_setg(errp, "KVM doesn't expose the MMU features it supports");
252 error_append_hint(errp, "Consider switching to a newer KVM\n");
253 return;
4656e1f0 254 }
4656e1f0 255
ab256960 256 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info);
71d0f1ea
GK		 257 if (ret == 0) {
258 return;
4656e1f0
BH		 259 }
260
71d0f1ea
GK		 261 error_setg_errno(errp, -ret,
262 "KVM failed to provide the MMU features it supports");
4656e1f0
BH		 263}
264
c64abd1f
SB		 265struct ppc_radix_page_info *kvm_get_radix_page_info(void)
266{
4f7f5893 267 KVMState *s = KVM_STATE(current_accel());
c64abd1f
SB		 268 struct ppc_radix_page_info *radix_page_info;
269 struct kvm_ppc_rmmu_info rmmu_info;
270 int i;
271
272 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) {
273 return NULL;
274 }
275 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) {
276 return NULL;
277 }
278 radix_page_info = g_malloc0(sizeof(*radix_page_info));
279 radix_page_info->count = 0;
280 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
281 if (rmmu_info.ap_encodings[i]) {
282 radix_page_info->entries[i] = rmmu_info.ap_encodings[i];
283 radix_page_info->count++;
284 }
285 }
286 return radix_page_info;
287}
288
b4db5413
SJS		 289target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
290 bool radix, bool gtse,
291 uint64_t proc_tbl)
292{
293 CPUState *cs = CPU(cpu);
294 int ret;
295 uint64_t flags = 0;
296 struct kvm_ppc_mmuv3_cfg cfg = {
297 .process_table = proc_tbl,
298 };
299
300 if (radix) {
301 flags |= KVM_PPC_MMUV3_RADIX;
302 }
303 if (gtse) {
304 flags |= KVM_PPC_MMUV3_GTSE;
305 }
306 cfg.flags = flags;
307 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg);
308 switch (ret) {
309 case 0:
310 return H_SUCCESS;
311 case -EINVAL:
312 return H_PARAMETER;
313 case -ENODEV:
314 return H_NOT_AVAILABLE;
315 default:
316 return H_HARDWARE;
317 }
318}
319
24c6863c
DG		 320bool kvmppc_hpt_needs_host_contiguous_pages(void)
321{
24c6863c
DG		 322 static struct kvm_ppc_smmu_info smmu_info;
323
324 if (!kvm_enabled()) {
325 return false;
326 }
327
ab256960 328 kvm_get_smmu_info(&smmu_info, &error_fatal);
24c6863c
DG		 329 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL);
330}
331
e5ca28ec 332void kvm_check_mmu(PowerPCCPU *cpu, Error **errp)
4656e1f0 333{
e5ca28ec 334 struct kvm_ppc_smmu_info smmu_info;
4656e1f0 335 int iq, ik, jq, jk;
71d0f1ea 336 Error *local_err = NULL;
4656e1f0 337
e5ca28ec
DG		 338 /* For now, we only have anything to check on hash64 MMUs */
339 if (!cpu->hash64_opts || !kvm_enabled()) {
4656e1f0
BH		 340 return;
341 }
342
ab256960 343 kvm_get_smmu_info(&smmu_info, &local_err);
71d0f1ea
GK		 344 if (local_err) {
345 error_propagate(errp, local_err);
346 return;
347 }
4656e1f0 348
e5ca28ec
DG		 349 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)
350 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
351 error_setg(errp,
352 "KVM does not support 1TiB segments which guest expects");
353 return;
df587133 354 }
4656e1f0 355
e5ca28ec
DG		 356 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) {
357 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u",
358 smmu_info.slb_size, cpu->hash64_opts->slb_size);
359 return;
90da0d5a
BH		 360 }
361
08215d8f 362 /*
e5ca28ec
DG		 363 * Verify that every pagesize supported by the cpu model is
364 * supported by KVM with the same encodings
08215d8f 365 */
e5ca28ec 366 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) {
b07c59f7 367 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq];
e5ca28ec 368 struct kvm_ppc_one_seg_page_size *ksps;
4656e1f0 369
e5ca28ec
DG		 370 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) {
371 if (qsps->page_shift == smmu_info.sps[ik].page_shift) {
4656e1f0
BH		 372 break;
373 }
374 }
e5ca28ec
DG		 375 if (ik >= ARRAY_SIZE(smmu_info.sps)) {
376 error_setg(errp, "KVM doesn't support for base page shift %u",
377 qsps->page_shift);
378 return;
379 }
380
381 ksps = &smmu_info.sps[ik];
382 if (ksps->slb_enc != qsps->slb_enc) {
383 error_setg(errp,
384"KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
385 ksps->slb_enc, ksps->page_shift, qsps->slb_enc);
386 return;
387 }
388
389 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) {
390 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) {
391 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) {
392 break;
393 }
394 }
395
396 if (jk >= ARRAY_SIZE(ksps->enc)) {
397 error_setg(errp, "KVM doesn't support page shift %u/%u",
398 qsps->enc[jq].page_shift, qsps->page_shift);
399 return;
400 }
401 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) {
402 error_setg(errp,
403"KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
404 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift,
405 qsps->page_shift, qsps->enc[jq].pte_enc);
406 return;
407 }
4656e1f0
BH		 408 }
409 }
4656e1f0 410
e5ca28ec 411 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
c995e942
DG		 412 /*
413 * Mostly what guest pagesizes we can use are related to the
e5ca28ec
DG		 414 * host pages used to map guest RAM, which is handled in the
415 * platform code. Cache-Inhibited largepages (64k) however are
416 * used for I/O, so if they're mapped to the host at all it
417 * will be a normal mapping, not a special hugepage one used
c995e942
DG		 418 * for RAM.
419 */
8e3b0cbb 420 if (qemu_real_host_page_size() < 0x10000) {
e5ca28ec
DG		 421 error_setg(errp,
422 "KVM can't supply 64kiB CI pages, which guest expects");
423 }
424 }
4656e1f0 425}
4656e1f0
BH		 426#endif /* !defined (TARGET_PPC64) */
427
b164e48e
EH		 428unsigned long kvm_arch_vcpu_id(CPUState *cpu)
429{
2e886fb3 430 return POWERPC_CPU(cpu)->vcpu_id;
b164e48e
EH		 431}
432
c995e942
DG		 433/*
434 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports
435 * only 1 watchpoint, so array size of 4 is sufficient for now.
88365d17
BB		 436 */
437#define MAX_HW_BKPTS 4
438
439static struct HWBreakpoint {
440 target_ulong addr;
441 int type;
442} hw_debug_points[MAX_HW_BKPTS];
443
444static CPUWatchpoint hw_watchpoint;
445
446/* Default there is no breakpoint and watchpoint supported */
447static int max_hw_breakpoint;
448static int max_hw_watchpoint;
449static int nb_hw_breakpoint;
450static int nb_hw_watchpoint;
451
452static void kvmppc_hw_debug_points_init(CPUPPCState *cenv)
453{
454 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
455 max_hw_breakpoint = 2;
456 max_hw_watchpoint = 2;
457 }
458
459 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) {
460 fprintf(stderr, "Error initializing h/w breakpoints\n");
461 return;
462 }
463}
464
20d695a9 465int kvm_arch_init_vcpu(CPUState *cs)
5666ca4a 466{
20d695a9
AF		 467 PowerPCCPU *cpu = POWERPC_CPU(cs);
468 CPUPPCState *cenv = &cpu->env;
5666ca4a
SW		 469 int ret;
470
4656e1f0 471 /* Synchronize sregs with kvm */
1bc22652 472 ret = kvm_arch_sync_sregs(cpu);
5666ca4a 473 if (ret) {
388e47c7
TH		 474 if (ret == -EINVAL) {
475 error_report("Register sync failed... If you're using kvm-hv.ko,"
476 " only \"-cpu host\" is possible");
477 }
5666ca4a
SW		 478 return ret;
479 }
861bbc80 480
93dd5e85
SW		 481 switch (cenv->mmu_model) {
482 case POWERPC_MMU_BOOKE206:
7f516c96 483 /* This target supports access to KVM's guest TLB */
1bc22652 484 ret = kvm_booke206_tlb_init(cpu);
93dd5e85 485 break;
7f516c96
TH		 486 case POWERPC_MMU_2_07:
487 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) {
c995e942
DG		 488 /*
489 * KVM-HV has transactional memory on POWER8 also without
490 * the KVM_CAP_PPC_HTM extension, so enable it here
136fbf65 491 * instead as long as it's available to userspace on the
c995e942
DG		 492 * host.
493 */
f3d9f303
SB		 494 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
495 cap_htm = true;
496 }
7f516c96
TH		 497 }
498 break;
93dd5e85
SW		 499 default:
500 break;
501 }
502
3c902d44 503 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode);
88365d17 504 kvmppc_hw_debug_points_init(cenv);
3c902d44 505
861bbc80 506 return ret;
d76d1650
AJ		 507}
508
b1115c99
LA		 509int kvm_arch_destroy_vcpu(CPUState *cs)
510{
511 return 0;
512}
513
1bc22652 514static void kvm_sw_tlb_put(PowerPCCPU *cpu)
93dd5e85 515{
1bc22652
AF		 516 CPUPPCState *env = &cpu->env;
517 CPUState *cs = CPU(cpu);
93dd5e85
SW		 518 struct kvm_dirty_tlb dirty_tlb;
519 unsigned char *bitmap;
520 int ret;
521
522 if (!env->kvm_sw_tlb) {
523 return;
524 }
525
526 bitmap = g_malloc((env->nb_tlb + 7) / 8);
527 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
528
529 dirty_tlb.bitmap = (uintptr_t)bitmap;
530 dirty_tlb.num_dirty = env->nb_tlb;
531
1bc22652 532 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb);
93dd5e85
SW		 533 if (ret) {
534 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
535 __func__, strerror(-ret));
536 }
537
538 g_free(bitmap);
539}
540
d67d40ea
DG		 541static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
542{
543 PowerPCCPU *cpu = POWERPC_CPU(cs);
544 CPUPPCState *env = &cpu->env;
545 union {
546 uint32_t u32;
547 uint64_t u64;
548 } val;
549 struct kvm_one_reg reg = {
550 .id = id,
551 .addr = (uintptr_t) &val,
552 };
553 int ret;
554
555 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
556 if (ret != 0) {
b36f100e 557 trace_kvm_failed_spr_get(spr, strerror(errno));
d67d40ea
DG		 558 } else {
559 switch (id & KVM_REG_SIZE_MASK) {
560 case KVM_REG_SIZE_U32:
561 env->spr[spr] = val.u32;
562 break;
563
564 case KVM_REG_SIZE_U64:
565 env->spr[spr] = val.u64;
566 break;
567
568 default:
569 /* Don't handle this size yet */
570 abort();
571 }
572 }
573}
574
575static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
576{
577 PowerPCCPU *cpu = POWERPC_CPU(cs);
578 CPUPPCState *env = &cpu->env;
579 union {
580 uint32_t u32;
581 uint64_t u64;
582 } val;
583 struct kvm_one_reg reg = {
584 .id = id,
585 .addr = (uintptr_t) &val,
586 };
587 int ret;
588
589 switch (id & KVM_REG_SIZE_MASK) {
590 case KVM_REG_SIZE_U32:
591 val.u32 = env->spr[spr];
592 break;
593
594 case KVM_REG_SIZE_U64:
595 val.u64 = env->spr[spr];
596 break;
597
598 default:
599 /* Don't handle this size yet */
600 abort();
601 }
602
603 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
604 if (ret != 0) {
b36f100e 605 trace_kvm_failed_spr_set(spr, strerror(errno));
d67d40ea
DG		 606 }
607}
608
70b79849
DG		 609static int kvm_put_fp(CPUState *cs)
610{
611 PowerPCCPU *cpu = POWERPC_CPU(cs);
612 CPUPPCState *env = &cpu->env;
613 struct kvm_one_reg reg;
614 int i;
615 int ret;
616
617 if (env->insns_flags & PPC_FLOAT) {
618 uint64_t fpscr = env->fpscr;
619 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
620
621 reg.id = KVM_REG_PPC_FPSCR;
622 reg.addr = (uintptr_t)&fpscr;
623 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
624 if (ret < 0) {
8d83cbf1 625 trace_kvm_failed_fpscr_set(strerror(errno));
70b79849
DG		 626 return ret;
627 }
628
629 for (i = 0; i < 32; i++) {
630 uint64_t vsr[2];
ef96e3ae
MCA		 631 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
632 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
70b79849 633
e03b5686 634#if HOST_BIG_ENDIAN
ef96e3ae
MCA		 635 vsr[0] = float64_val(*fpr);
636 vsr[1] = *vsrl;
3a4b791b 637#else
ef96e3ae
MCA		 638 vsr[0] = *vsrl;
639 vsr[1] = float64_val(*fpr);
3a4b791b 640#endif
70b79849
DG		 641 reg.addr = (uintptr_t) &vsr;
642 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
643
644 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
645 if (ret < 0) {
8d83cbf1
GK		 646 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i,
647 strerror(errno));
70b79849
DG		 648 return ret;
649 }
650 }
651 }
652
653 if (env->insns_flags & PPC_ALTIVEC) {
654 reg.id = KVM_REG_PPC_VSCR;
655 reg.addr = (uintptr_t)&env->vscr;
656 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
657 if (ret < 0) {
8d83cbf1 658 trace_kvm_failed_vscr_set(strerror(errno));
70b79849
DG		 659 return ret;
660 }
661
662 for (i = 0; i < 32; i++) {
663 reg.id = KVM_REG_PPC_VR(i);
ef96e3ae 664 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
70b79849
DG		 665 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
666 if (ret < 0) {
8d83cbf1 667 trace_kvm_failed_vr_set(i, strerror(errno));
70b79849
DG		 668 return ret;
669 }
670 }
671 }
672
673 return 0;
674}
675
676static int kvm_get_fp(CPUState *cs)
677{
678 PowerPCCPU *cpu = POWERPC_CPU(cs);
679 CPUPPCState *env = &cpu->env;
680 struct kvm_one_reg reg;
681 int i;
682 int ret;
683
684 if (env->insns_flags & PPC_FLOAT) {
685 uint64_t fpscr;
686 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
687
688 reg.id = KVM_REG_PPC_FPSCR;
689 reg.addr = (uintptr_t)&fpscr;
690 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
691 if (ret < 0) {
8d83cbf1 692 trace_kvm_failed_fpscr_get(strerror(errno));
70b79849
DG		 693 return ret;
694 } else {
695 env->fpscr = fpscr;
696 }
697
698 for (i = 0; i < 32; i++) {
699 uint64_t vsr[2];
ef96e3ae
MCA		 700 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
701 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
70b79849
DG		 702
703 reg.addr = (uintptr_t) &vsr;
704 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
705
706 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
707 if (ret < 0) {
8d83cbf1
GK		 708 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i,
709 strerror(errno));
70b79849
DG		 710 return ret;
711 } else {
e03b5686 712#if HOST_BIG_ENDIAN
ef96e3ae 713 *fpr = vsr[0];
70b79849 714 if (vsx) {
ef96e3ae 715 *vsrl = vsr[1];
70b79849 716 }
3a4b791b 717#else
ef96e3ae 718 *fpr = vsr[1];
3a4b791b 719 if (vsx) {
ef96e3ae 720 *vsrl = vsr[0];
3a4b791b
GK		 721 }
722#endif
70b79849
DG		 723 }
724 }
725 }
726
727 if (env->insns_flags & PPC_ALTIVEC) {
728 reg.id = KVM_REG_PPC_VSCR;
729 reg.addr = (uintptr_t)&env->vscr;
730 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
731 if (ret < 0) {
8d83cbf1 732 trace_kvm_failed_vscr_get(strerror(errno));
70b79849
DG		 733 return ret;
734 }
735
736 for (i = 0; i < 32; i++) {
737 reg.id = KVM_REG_PPC_VR(i);
ef96e3ae 738 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
70b79849
DG		 739 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
740 if (ret < 0) {
8d83cbf1 741 trace_kvm_failed_vr_get(i, strerror(errno));
70b79849
DG		 742 return ret;
743 }
744 }
745 }
746
747 return 0;
748}
749
9b00ea49
DG		 750#if defined(TARGET_PPC64)
751static int kvm_get_vpa(CPUState *cs)
752{
753 PowerPCCPU *cpu = POWERPC_CPU(cs);
ce2918cb 754 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
9b00ea49
DG		 755 struct kvm_one_reg reg;
756 int ret;
757
758 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 759 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 760 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
761 if (ret < 0) {
8d83cbf1 762 trace_kvm_failed_vpa_addr_get(strerror(errno));
9b00ea49
DG		 763 return ret;
764 }
765
7388efaf
DG		 766 assert((uintptr_t)&spapr_cpu->slb_shadow_size
767 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
9b00ea49 768 reg.id = KVM_REG_PPC_VPA_SLB;
7388efaf 769 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
9b00ea49
DG		 770 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
771 if (ret < 0) {
8d83cbf1 772 trace_kvm_failed_slb_get(strerror(errno));
9b00ea49
DG		 773 return ret;
774 }
775
7388efaf
DG		 776 assert((uintptr_t)&spapr_cpu->dtl_size
777 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
9b00ea49 778 reg.id = KVM_REG_PPC_VPA_DTL;
7388efaf 779 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
9b00ea49
DG		 780 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
781 if (ret < 0) {
8d83cbf1 782 trace_kvm_failed_dtl_get(strerror(errno));
9b00ea49
DG		 783 return ret;
784 }
785
786 return 0;
787}
788
789static int kvm_put_vpa(CPUState *cs)
790{
791 PowerPCCPU *cpu = POWERPC_CPU(cs);
ce2918cb 792 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
9b00ea49
DG		 793 struct kvm_one_reg reg;
794 int ret;
795
c995e942
DG		 796 /*
797 * SLB shadow or DTL can't be registered unless a master VPA is
9b00ea49
DG		 798 * registered. That means when restoring state, if a VPA *is*
799 * registered, we need to set that up first. If not, we need to
c995e942
DG		 800 * deregister the others before deregistering the master VPA
801 */
7388efaf
DG		 802 assert(spapr_cpu->vpa_addr
803 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr));
9b00ea49 804
7388efaf 805 if (spapr_cpu->vpa_addr) {
9b00ea49 806 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 807 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 808 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
809 if (ret < 0) {
8d83cbf1 810 trace_kvm_failed_vpa_addr_set(strerror(errno));
9b00ea49
DG		 811 return ret;
812 }
813 }
814
7388efaf
DG		 815 assert((uintptr_t)&spapr_cpu->slb_shadow_size
816 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
9b00ea49 817 reg.id = KVM_REG_PPC_VPA_SLB;
7388efaf 818 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
9b00ea49
DG		 819 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
820 if (ret < 0) {
8d83cbf1 821 trace_kvm_failed_slb_set(strerror(errno));
9b00ea49
DG		 822 return ret;
823 }
824
7388efaf
DG		 825 assert((uintptr_t)&spapr_cpu->dtl_size
826 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
9b00ea49 827 reg.id = KVM_REG_PPC_VPA_DTL;
7388efaf 828 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
9b00ea49
DG		 829 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
830 if (ret < 0) {
8d83cbf1 831 trace_kvm_failed_dtl_set(strerror(errno));
9b00ea49
DG		 832 return ret;
833 }
834
7388efaf 835 if (!spapr_cpu->vpa_addr) {
9b00ea49 836 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 837 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 838 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
839 if (ret < 0) {
8d83cbf1 840 trace_kvm_failed_null_vpa_addr_set(strerror(errno));
9b00ea49
DG		 841 return ret;
842 }
843 }
844
845 return 0;
846}
847#endif /* TARGET_PPC64 */
848
e5c0d3ce 849int kvmppc_put_books_sregs(PowerPCCPU *cpu)
a7a00a72
DG		 850{
851 CPUPPCState *env = &cpu->env;
852 struct kvm_sregs sregs;
853 int i;
854
855 sregs.pvr = env->spr[SPR_PVR];
856
1ec26c75
GK		 857 if (cpu->vhyp) {
858 PPCVirtualHypervisorClass *vhc =
859 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
860 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp);
861 } else {
862 sregs.u.s.sdr1 = env->spr[SPR_SDR1];
863 }
a7a00a72
DG		 864
865 /* Sync SLB */
866#ifdef TARGET_PPC64
867 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
868 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid;
869 if (env->slb[i].esid & SLB_ESID_V) {
870 sregs.u.s.ppc64.slb[i].slbe |= i;
871 }
872 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid;
873 }
874#endif
875
876 /* Sync SRs */
877 for (i = 0; i < 16; i++) {
878 sregs.u.s.ppc32.sr[i] = env->sr[i];
879 }
880
881 /* Sync BATs */
882 for (i = 0; i < 8; i++) {
883 /* Beware. We have to swap upper and lower bits here */
884 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32)
885 | env->DBAT[1][i];
886 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32)
887 | env->IBAT[1][i];
888 }
889
890 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
891}
892
20d695a9 893int kvm_arch_put_registers(CPUState *cs, int level)
d76d1650 894{
20d695a9
AF		 895 PowerPCCPU *cpu = POWERPC_CPU(cs);
896 CPUPPCState *env = &cpu->env;
d76d1650
AJ		 897 struct kvm_regs regs;
898 int ret;
899 int i;
900
1bc22652
AF		 901 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
902 if (ret < 0) {
d76d1650 903 return ret;
1bc22652 904 }
d76d1650
AJ		 905
906 regs.ctr = env->ctr;
907 regs.lr = env->lr;
da91a00f 908 regs.xer = cpu_read_xer(env);
d76d1650
AJ		 909 regs.msr = env->msr;
910 regs.pc = env->nip;
911
912 regs.srr0 = env->spr[SPR_SRR0];
913 regs.srr1 = env->spr[SPR_SRR1];
914
915 regs.sprg0 = env->spr[SPR_SPRG0];
916 regs.sprg1 = env->spr[SPR_SPRG1];
917 regs.sprg2 = env->spr[SPR_SPRG2];
918 regs.sprg3 = env->spr[SPR_SPRG3];
919 regs.sprg4 = env->spr[SPR_SPRG4];
920 regs.sprg5 = env->spr[SPR_SPRG5];
921 regs.sprg6 = env->spr[SPR_SPRG6];
922 regs.sprg7 = env->spr[SPR_SPRG7];
923
90dc8812
SW		 924 regs.pid = env->spr[SPR_BOOKE_PID];
925
c995e942 926 for (i = 0; i < 32; i++) {
d76d1650 927 regs.gpr[i] = env->gpr[i];
c995e942 928 }
d76d1650 929
4bddaf55
AK		 930 regs.cr = 0;
931 for (i = 0; i < 8; i++) {
932 regs.cr |= (env->crf[i] & 15) << (4 * (7 - i));
933 }
934
1bc22652 935 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
c995e942 936 if (ret < 0) {
d76d1650 937 return ret;
c995e942 938 }
d76d1650 939
70b79849
DG		 940 kvm_put_fp(cs);
941
93dd5e85 942 if (env->tlb_dirty) {
1bc22652 943 kvm_sw_tlb_put(cpu);
93dd5e85
SW		 944 env->tlb_dirty = false;
945 }
946
f1af19d7 947 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) {
a7a00a72
DG		 948 ret = kvmppc_put_books_sregs(cpu);
949 if (ret < 0) {
f1af19d7
DG		 950 return ret;
951 }
952 }
953
954 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {
d67d40ea
DG		 955 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
956 }
f1af19d7 957
d67d40ea
DG		 958 if (cap_one_reg) {
959 int i;
960
c995e942
DG		 961 /*
962 * We deliberately ignore errors here, for kernels which have
d67d40ea
DG		 963 * the ONE_REG calls, but don't support the specific
964 * registers, there's a reasonable chance things will still
c995e942
DG		 965 * work, at least until we try to migrate.
966 */
d67d40ea
DG		 967 for (i = 0; i < 1024; i++) {
968 uint64_t id = env->spr_cb[i].one_reg_id;
969
970 if (id != 0) {
971 kvm_put_one_spr(cs, id, i);
972 }
f1af19d7 973 }
9b00ea49
DG		 974
975#ifdef TARGET_PPC64
80b3f79b
AK		 976 if (msr_ts) {
977 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
978 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
979 }
980 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
981 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
982 }
983 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
984 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
985 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
986 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
987 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
988 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
989 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
990 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
991 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
992 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
993 }
994
9b00ea49
DG		 995 if (cap_papr) {
996 if (kvm_put_vpa(cs) < 0) {
8d83cbf1 997 trace_kvm_failed_put_vpa();
9b00ea49
DG		 998 }
999 }
98a8b524
AK		 1000
1001 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
972bd576
AK		 1002
1003 if (level > KVM_PUT_RUNTIME_STATE) {
1004 kvm_put_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES);
1005 }
9b00ea49 1006#endif /* TARGET_PPC64 */
f1af19d7
DG		 1007 }
1008
d76d1650
AJ		 1009 return ret;
1010}
1011
c371c2e3
BB		 1012static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor)
1013{
1014 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR];
1015}
1016
a7a00a72
DG		 1017static int kvmppc_get_booke_sregs(PowerPCCPU *cpu)
1018{
1019 CPUPPCState *env = &cpu->env;
1020 struct kvm_sregs sregs;
1021 int ret;
1022
1023 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1024 if (ret < 0) {
1025 return ret;
1026 }
1027
1028 if (sregs.u.e.features & KVM_SREGS_E_BASE) {
1029 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
1030 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
1031 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
1032 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
1033 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
1034 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
1035 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
1036 env->spr[SPR_DECR] = sregs.u.e.dec;
1037 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
1038 env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
1039 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
1040 }
1041
1042 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
1043 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
1044 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
1045 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
1046 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
1047 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
1048 }
1049
1050 if (sregs.u.e.features & KVM_SREGS_E_64) {
1051 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
1052 }
1053
1054 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
1055 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
1056 }
1057
1058 if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
1059 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
1060 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0);
1061 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
1062 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1);
1063 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
1064 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2);
1065 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
1066 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3);
1067 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
1068 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4);
1069 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
1070 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5);
1071 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
1072 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6);
1073 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
1074 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7);
1075 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
1076 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8);
1077 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
1078 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9);
1079 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
1080 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10);
1081 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
1082 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11);
1083 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
1084 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12);
1085 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
1086 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13);
1087 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
1088 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14);
1089 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
1090 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15);
1091
1092 if (sregs.u.e.features & KVM_SREGS_E_SPE) {
1093 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
1094 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32);
1095 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
1096 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33);
1097 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
1098 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34);
1099 }
1100
1101 if (sregs.u.e.features & KVM_SREGS_E_PM) {
1102 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
1103 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35);
1104 }
1105
1106 if (sregs.u.e.features & KVM_SREGS_E_PC) {
1107 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
1108 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36);
1109 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
1110 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37);
1111 }
1112 }
1113
1114 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
1115 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
1116 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
1117 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
1118 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
1119 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
1120 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
1121 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
1122 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
1123 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
1124 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
1125 }
1126
1127 if (sregs.u.e.features & KVM_SREGS_EXP) {
1128 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
1129 }
1130
1131 if (sregs.u.e.features & KVM_SREGS_E_PD) {
1132 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
1133 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
1134 }
1135
1136 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
1137 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
1138 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
1139 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;
1140
1141 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
1142 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
1143 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
1144 }
1145 }
1146
1147 return 0;
1148}
1149
1150static int kvmppc_get_books_sregs(PowerPCCPU *cpu)
1151{
1152 CPUPPCState *env = &cpu->env;
1153 struct kvm_sregs sregs;
1154 int ret;
1155 int i;
1156
1157 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1158 if (ret < 0) {
1159 return ret;
1160 }
1161
e57ca75c 1162 if (!cpu->vhyp) {
a7a00a72
DG		 1163 ppc_store_sdr1(env, sregs.u.s.sdr1);
1164 }
1165
1166 /* Sync SLB */
1167#ifdef TARGET_PPC64
1168 /*
1169 * The packed SLB array we get from KVM_GET_SREGS only contains
1170 * information about valid entries. So we flush our internal copy
1171 * to get rid of stale ones, then put all valid SLB entries back
1172 * in.
1173 */
1174 memset(env->slb, 0, sizeof(env->slb));
1175 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
1176 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe;
1177 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv;
1178 /*
1179 * Only restore valid entries
1180 */
1181 if (rb & SLB_ESID_V) {
1182 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs);
1183 }
1184 }
1185#endif
1186
1187 /* Sync SRs */
1188 for (i = 0; i < 16; i++) {
1189 env->sr[i] = sregs.u.s.ppc32.sr[i];
1190 }
1191
1192 /* Sync BATs */
1193 for (i = 0; i < 8; i++) {
1194 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
1195 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
1196 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
1197 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
1198 }
1199
1200 return 0;
1201}
1202
20d695a9 1203int kvm_arch_get_registers(CPUState *cs)
d76d1650 1204{
20d695a9
AF		 1205 PowerPCCPU *cpu = POWERPC_CPU(cs);
1206 CPUPPCState *env = &cpu->env;
d76d1650 1207 struct kvm_regs regs;
90dc8812 1208 uint32_t cr;
138b38b6 1209 int i, ret;
d76d1650 1210
1bc22652 1211 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
c995e942 1212 if (ret < 0) {
d76d1650 1213 return ret;
c995e942 1214 }
d76d1650 1215
90dc8812
SW		 1216 cr = regs.cr;
1217 for (i = 7; i >= 0; i--) {
1218 env->crf[i] = cr & 15;
1219 cr >>= 4;
1220 }
ba5e5090 1221
d76d1650
AJ		 1222 env->ctr = regs.ctr;
1223 env->lr = regs.lr;
da91a00f 1224 cpu_write_xer(env, regs.xer);
d76d1650
AJ		 1225 env->msr = regs.msr;
1226 env->nip = regs.pc;
1227
1228 env->spr[SPR_SRR0] = regs.srr0;
1229 env->spr[SPR_SRR1] = regs.srr1;
1230
1231 env->spr[SPR_SPRG0] = regs.sprg0;
1232 env->spr[SPR_SPRG1] = regs.sprg1;
1233 env->spr[SPR_SPRG2] = regs.sprg2;
1234 env->spr[SPR_SPRG3] = regs.sprg3;
1235 env->spr[SPR_SPRG4] = regs.sprg4;
1236 env->spr[SPR_SPRG5] = regs.sprg5;
1237 env->spr[SPR_SPRG6] = regs.sprg6;
1238 env->spr[SPR_SPRG7] = regs.sprg7;
1239
90dc8812
SW		 1240 env->spr[SPR_BOOKE_PID] = regs.pid;
1241
c995e942 1242 for (i = 0; i < 32; i++) {
d76d1650 1243 env->gpr[i] = regs.gpr[i];
c995e942 1244 }
d76d1650 1245
70b79849
DG		 1246 kvm_get_fp(cs);
1247
90dc8812 1248 if (cap_booke_sregs) {
a7a00a72 1249 ret = kvmppc_get_booke_sregs(cpu);
90dc8812
SW		 1250 if (ret < 0) {
1251 return ret;
1252 }
fafc0b6a 1253 }
90dc8812 1254
90dc8812 1255 if (cap_segstate) {
a7a00a72 1256 ret = kvmppc_get_books_sregs(cpu);
90dc8812
SW		 1257 if (ret < 0) {
1258 return ret;
1259 }
fafc0b6a 1260 }
ba5e5090 1261
d67d40ea
DG		 1262 if (cap_hior) {
1263 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
1264 }
1265
1266 if (cap_one_reg) {
1267 int i;
1268
c995e942
DG		 1269 /*
1270 * We deliberately ignore errors here, for kernels which have
d67d40ea
DG		 1271 * the ONE_REG calls, but don't support the specific
1272 * registers, there's a reasonable chance things will still
c995e942
DG		 1273 * work, at least until we try to migrate.
1274 */
d67d40ea
DG		 1275 for (i = 0; i < 1024; i++) {
1276 uint64_t id = env->spr_cb[i].one_reg_id;
1277
1278 if (id != 0) {
1279 kvm_get_one_spr(cs, id, i);
1280 }
1281 }
9b00ea49
DG		 1282
1283#ifdef TARGET_PPC64
80b3f79b
AK		 1284 if (msr_ts) {
1285 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
1286 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
1287 }
1288 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
1289 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
1290 }
1291 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
1292 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
1293 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
1294 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
1295 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1296 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1297 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1298 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1299 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1300 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1301 }
1302
9b00ea49
DG		 1303 if (cap_papr) {
1304 if (kvm_get_vpa(cs) < 0) {
8d83cbf1 1305 trace_kvm_failed_get_vpa();
9b00ea49
DG		 1306 }
1307 }
98a8b524
AK		 1308
1309 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
972bd576 1310 kvm_get_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES);
9b00ea49 1311#endif
d67d40ea
DG		 1312 }
1313
d76d1650
AJ		 1314 return 0;
1315}
1316
1bc22652 1317int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
fc87e185
AG		 1318{
1319 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
1320
1321 if (irq != PPC_INTERRUPT_EXT) {
1322 return 0;
1323 }
1324
1e8f51e8 1325 if (!kvm_enabled() || !cap_interrupt_unset) {
fc87e185
AG		 1326 return 0;
1327 }
1328
1bc22652 1329 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
fc87e185
AG		 1330
1331 return 0;
1332}
1333
20d695a9 1334void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
d76d1650 1335{
1e8f51e8 1336 return;
d76d1650
AJ		 1337}
1338
4c663752 1339MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
d76d1650 1340{
4c663752 1341 return MEMTXATTRS_UNSPECIFIED;
d76d1650
AJ		 1342}
1343
20d695a9 1344int kvm_arch_process_async_events(CPUState *cs)
0af691d7 1345{
259186a7 1346 return cs->halted;
0af691d7
MT		 1347}
1348
259186a7 1349static int kvmppc_handle_halt(PowerPCCPU *cpu)
d76d1650 1350{
259186a7
AF		 1351 CPUState *cs = CPU(cpu);
1352 CPUPPCState *env = &cpu->env;
1353
1354 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
1355 cs->halted = 1;
27103424 1356 cs->exception_index = EXCP_HLT;
d76d1650
AJ		 1357 }
1358
bb4ea393 1359 return 0;
d76d1650
AJ		 1360}
1361
1362/* map dcr access to existing qemu dcr emulation */
c995e942
DG		 1363static int kvmppc_handle_dcr_read(CPUPPCState *env,
1364 uint32_t dcrn, uint32_t *data)
d76d1650 1365{
c995e942 1366 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) {
d76d1650 1367 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
c995e942 1368 }
d76d1650 1369
bb4ea393 1370 return 0;
d76d1650
AJ		 1371}
1372
c995e942
DG		 1373static int kvmppc_handle_dcr_write(CPUPPCState *env,
1374 uint32_t dcrn, uint32_t data)
d76d1650 1375{
c995e942 1376 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) {
d76d1650 1377 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
c995e942 1378 }
d76d1650 1379
bb4ea393 1380 return 0;
d76d1650
AJ		 1381}
1382
8a0548f9
BB		 1383int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1384{
1385 /* Mixed endian case is not handled */
1386 uint32_t sc = debug_inst_opcode;
1387
1388 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1389 sizeof(sc), 0) ||
1390 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) {
1391 return -EINVAL;
1392 }
1393
1394 return 0;
1395}
1396
1397int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1398{
1399 uint32_t sc;
1400
1401 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) ||
1402 sc != debug_inst_opcode ||
1403 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1404 sizeof(sc), 1)) {
1405 return -EINVAL;
1406 }
1407
1408 return 0;
1409}
1410
88365d17
BB		 1411static int find_hw_breakpoint(target_ulong addr, int type)
1412{
1413 int n;
1414
1415 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1416 <= ARRAY_SIZE(hw_debug_points));
1417
1418 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1419 if (hw_debug_points[n].addr == addr &&
1420 hw_debug_points[n].type == type) {
1421 return n;
1422 }
1423 }
1424
1425 return -1;
1426}
1427
1428static int find_hw_watchpoint(target_ulong addr, int *flag)
1429{
1430 int n;
1431
1432 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS);
1433 if (n >= 0) {
1434 *flag = BP_MEM_ACCESS;
1435 return n;
1436 }
1437
1438 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE);
1439 if (n >= 0) {
1440 *flag = BP_MEM_WRITE;
1441 return n;
1442 }
1443
1444 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ);
1445 if (n >= 0) {
1446 *flag = BP_MEM_READ;
1447 return n;
1448 }
1449
1450 return -1;
1451}
1452
1453int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1454 target_ulong len, int type)
1455{
1456 if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) {
1457 return -ENOBUFS;
1458 }
1459
1460 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr;
1461 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type;
1462
1463 switch (type) {
1464 case GDB_BREAKPOINT_HW:
1465 if (nb_hw_breakpoint >= max_hw_breakpoint) {
1466 return -ENOBUFS;
1467 }
1468
1469 if (find_hw_breakpoint(addr, type) >= 0) {
1470 return -EEXIST;
1471 }
1472
1473 nb_hw_breakpoint++;
1474 break;
1475
1476 case GDB_WATCHPOINT_WRITE:
1477 case GDB_WATCHPOINT_READ:
1478 case GDB_WATCHPOINT_ACCESS:
1479 if (nb_hw_watchpoint >= max_hw_watchpoint) {
1480 return -ENOBUFS;
1481 }
1482
1483 if (find_hw_breakpoint(addr, type) >= 0) {
1484 return -EEXIST;
1485 }
1486
1487 nb_hw_watchpoint++;
1488 break;
1489
1490 default:
1491 return -ENOSYS;
1492 }
1493
1494 return 0;
1495}
1496
1497int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1498 target_ulong len, int type)
1499{
1500 int n;
1501
1502 n = find_hw_breakpoint(addr, type);
1503 if (n < 0) {
1504 return -ENOENT;
1505 }
1506
1507 switch (type) {
1508 case GDB_BREAKPOINT_HW:
1509 nb_hw_breakpoint--;
1510 break;
1511
1512 case GDB_WATCHPOINT_WRITE:
1513 case GDB_WATCHPOINT_READ:
1514 case GDB_WATCHPOINT_ACCESS:
1515 nb_hw_watchpoint--;
1516 break;
1517
1518 default:
1519 return -ENOSYS;
1520 }
1521 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint];
1522
1523 return 0;
1524}
1525
1526void kvm_arch_remove_all_hw_breakpoints(void)
1527{
1528 nb_hw_breakpoint = nb_hw_watchpoint = 0;
1529}
1530
8a0548f9
BB		 1531void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
1532{
88365d17
BB		 1533 int n;
1534
8a0548f9
BB		 1535 /* Software Breakpoint updates */
1536 if (kvm_sw_breakpoints_active(cs)) {
1537 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1538 }
88365d17
BB		 1539
1540 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1541 <= ARRAY_SIZE(hw_debug_points));
1542 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp));
1543
1544 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1545 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1546 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp));
1547 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1548 switch (hw_debug_points[n].type) {
1549 case GDB_BREAKPOINT_HW:
1550 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT;
1551 break;
1552 case GDB_WATCHPOINT_WRITE:
1553 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE;
1554 break;
1555 case GDB_WATCHPOINT_READ:
1556 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ;
1557 break;
1558 case GDB_WATCHPOINT_ACCESS:
1559 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE |
1560 KVMPPC_DEBUG_WATCH_READ;
1561 break;
1562 default:
1563 cpu_abort(cs, "Unsupported breakpoint type\n");
1564 }
1565 dbg->arch.bp[n].addr = hw_debug_points[n].addr;
1566 }
1567 }
8a0548f9
BB		 1568}
1569
2cbd1581
FR		 1570static int kvm_handle_hw_breakpoint(CPUState *cs,
1571 struct kvm_debug_exit_arch *arch_info)
1572{
6e0552a3 1573 int handle = DEBUG_RETURN_GUEST;
2cbd1581
FR		 1574 int n;
1575 int flag = 0;
1576
1577 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1578 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) {
1579 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW);
1580 if (n >= 0) {
6e0552a3 1581 handle = DEBUG_RETURN_GDB;
2cbd1581
FR		 1582 }
1583 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ |
1584 KVMPPC_DEBUG_WATCH_WRITE)) {
1585 n = find_hw_watchpoint(arch_info->address, &flag);
1586 if (n >= 0) {
6e0552a3 1587 handle = DEBUG_RETURN_GDB;
2cbd1581
FR		 1588 cs->watchpoint_hit = &hw_watchpoint;
1589 hw_watchpoint.vaddr = hw_debug_points[n].addr;
1590 hw_watchpoint.flags = flag;
1591 }
1592 }
1593 }
1594 return handle;
1595}
1596
468e3a1a
FR		 1597static int kvm_handle_singlestep(void)
1598{
6e0552a3 1599 return DEBUG_RETURN_GDB;
468e3a1a
FR		 1600}
1601
1602static int kvm_handle_sw_breakpoint(void)
1603{
6e0552a3 1604 return DEBUG_RETURN_GDB;
468e3a1a
FR		 1605}
1606
8a0548f9
BB		 1607static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run)
1608{
1609 CPUState *cs = CPU(cpu);
1610 CPUPPCState *env = &cpu->env;
1611 struct kvm_debug_exit_arch *arch_info = &run->debug.arch;
8a0548f9 1612
88365d17 1613 if (cs->singlestep_enabled) {
468e3a1a
FR		 1614 return kvm_handle_singlestep();
1615 }
8a0548f9 1616
468e3a1a
FR		 1617 if (arch_info->status) {
1618 return kvm_handle_hw_breakpoint(cs, arch_info);
8a0548f9
BB		 1619 }
1620
468e3a1a
FR		 1621 if (kvm_find_sw_breakpoint(cs, arch_info->address)) {
1622 return kvm_handle_sw_breakpoint();
1623 }
1624
1625 /*
1626 * QEMU is not able to handle debug exception, so inject
1627 * program exception to guest;
1628 * Yes program exception NOT debug exception !!
1629 * When QEMU is using debug resources then debug exception must
1630 * be always set. To achieve this we set MSR_DE and also set
1631 * MSRP_DEP so guest cannot change MSR_DE.
1632 * When emulating debug resource for guest we want guest
1633 * to control MSR_DE (enable/disable debug interrupt on need).
1634 * Supporting both configurations are NOT possible.
1635 * So the result is that we cannot share debug resources
1636 * between QEMU and Guest on BOOKE architecture.
1637 * In the current design QEMU gets the priority over guest,
1638 * this means that if QEMU is using debug resources then guest
1639 * cannot use them;
1640 * For software breakpoint QEMU uses a privileged instruction;
1641 * So there cannot be any reason that we are here for guest
1642 * set debug exception, only possibility is guest executed a
1643 * privileged / illegal instruction and that's why we are
1644 * injecting a program interrupt.
1645 */
1646 cpu_synchronize_state(cs);
1647 /*
1648 * env->nip is PC, so increment this by 4 to use
1649 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1650 */
1651 env->nip += 4;
1652 cs->exception_index = POWERPC_EXCP_PROGRAM;
1653 env->error_code = POWERPC_EXCP_INVAL;
1654 ppc_cpu_do_interrupt(cs);
1655
6e0552a3 1656 return DEBUG_RETURN_GUEST;
8a0548f9
BB		 1657}
1658
20d695a9 1659int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
d76d1650 1660{
20d695a9
AF		 1661 PowerPCCPU *cpu = POWERPC_CPU(cs);
1662 CPUPPCState *env = &cpu->env;
bb4ea393 1663 int ret;
d76d1650 1664
4b8523ee
JK		 1665 qemu_mutex_lock_iothread();
1666
d76d1650
AJ		 1667 switch (run->exit_reason) {
1668 case KVM_EXIT_DCR:
1669 if (run->dcr.is_write) {
8d83cbf1 1670 trace_kvm_handle_dcr_write();
d76d1650
AJ		 1671 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
1672 } else {
228152c2 1673 trace_kvm_handle_dcr_read();
d76d1650
AJ		 1674 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
1675 }
1676 break;
1677 case KVM_EXIT_HLT:
8d83cbf1 1678 trace_kvm_handle_halt();
259186a7 1679 ret = kvmppc_handle_halt(cpu);
d76d1650 1680 break;
c6304a4a 1681#if defined(TARGET_PPC64)
f61b4bed 1682 case KVM_EXIT_PAPR_HCALL:
8d83cbf1 1683 trace_kvm_handle_papr_hcall();
20d695a9 1684 run->papr_hcall.ret = spapr_hypercall(cpu,
aa100fa4 1685 run->papr_hcall.nr,
f61b4bed 1686 run->papr_hcall.args);
78e8fde2 1687 ret = 0;
f61b4bed
AG		 1688 break;
1689#endif
5b95b8b9 1690 case KVM_EXIT_EPR:
8d83cbf1 1691 trace_kvm_handle_epr();
933b19ea 1692 run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
5b95b8b9
AG		 1693 ret = 0;
1694 break;
31f2cb8f 1695 case KVM_EXIT_WATCHDOG:
8d83cbf1 1696 trace_kvm_handle_watchdog_expiry();
31f2cb8f
BB		 1697 watchdog_perform_action();
1698 ret = 0;
1699 break;
1700
8a0548f9 1701 case KVM_EXIT_DEBUG:
8d83cbf1 1702 trace_kvm_handle_debug_exception();
8a0548f9
BB		 1703 if (kvm_handle_debug(cpu, run)) {
1704 ret = EXCP_DEBUG;
1705 break;
1706 }
1707 /* re-enter, this exception was guest-internal */
1708 ret = 0;
1709 break;
1710
9ac703ac
AP		 1711#if defined(TARGET_PPC64)
1712 case KVM_EXIT_NMI:
1713 trace_kvm_handle_nmi_exception();
1714 ret = kvm_handle_nmi(cpu, run);
1715 break;
1716#endif
1717
73aaec4a
JK		 1718 default:
1719 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1720 ret = -1;
1721 break;
d76d1650
AJ		 1722 }
1723
4b8523ee 1724 qemu_mutex_unlock_iothread();
d76d1650
AJ		 1725 return ret;
1726}
1727
31f2cb8f
BB		 1728int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1729{
1730 CPUState *cs = CPU(cpu);
1731 uint32_t bits = tsr_bits;
1732 struct kvm_one_reg reg = {
1733 .id = KVM_REG_PPC_OR_TSR,
1734 .addr = (uintptr_t) &bits,
1735 };
1736
1737 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1738}
1739
1740int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1741{
1742
1743 CPUState *cs = CPU(cpu);
1744 uint32_t bits = tsr_bits;
1745 struct kvm_one_reg reg = {
1746 .id = KVM_REG_PPC_CLEAR_TSR,
1747 .addr = (uintptr_t) &bits,
1748 };
1749
1750 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1751}
1752
1753int kvmppc_set_tcr(PowerPCCPU *cpu)
1754{
1755 CPUState *cs = CPU(cpu);
1756 CPUPPCState *env = &cpu->env;
1757 uint32_t tcr = env->spr[SPR_BOOKE_TCR];
1758
1759 struct kvm_one_reg reg = {
1760 .id = KVM_REG_PPC_TCR,
1761 .addr = (uintptr_t) &tcr,
1762 };
1763
1764 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1765}
1766
1767int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
1768{
1769 CPUState *cs = CPU(cpu);
31f2cb8f
BB		 1770 int ret;
1771
1772 if (!kvm_enabled()) {
1773 return -1;
1774 }
1775
1776 if (!cap_ppc_watchdog) {
1777 printf("warning: KVM does not support watchdog");
1778 return -1;
1779 }
1780
48add816 1781 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0);
31f2cb8f
BB		 1782 if (ret < 0) {
1783 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1784 __func__, strerror(-ret));
1785 return ret;
1786 }
1787
1788 return ret;
1789}
1790
dc333cd6
AG		 1791static int read_cpuinfo(const char *field, char *value, int len)
1792{
1793 FILE *f;
1794 int ret = -1;
1795 int field_len = strlen(field);
1796 char line[512];
1797
1798 f = fopen("/proc/cpuinfo", "r");
1799 if (!f) {
1800 return -1;
1801 }
1802
1803 do {
ef951443 1804 if (!fgets(line, sizeof(line), f)) {
dc333cd6
AG		 1805 break;
1806 }
1807 if (!strncmp(line, field, field_len)) {
ae215068 1808 pstrcpy(value, len, line);
dc333cd6
AG		 1809 ret = 0;
1810 break;
1811 }
c995e942 1812 } while (*line);
dc333cd6
AG		 1813
1814 fclose(f);
1815
1816 return ret;
1817}
1818
9cbcfb59 1819static uint32_t kvmppc_get_tbfreq_procfs(void)
dc333cd6
AG		 1820{
1821 char line[512];
1822 char *ns;
9cbcfb59
GK		 1823 uint32_t tbfreq_fallback = NANOSECONDS_PER_SECOND;
1824 uint32_t tbfreq_procfs;
dc333cd6
AG		 1825
1826 if (read_cpuinfo("timebase", line, sizeof(line))) {
9cbcfb59 1827 return tbfreq_fallback;
dc333cd6
AG		 1828 }
1829
c995e942
DG		 1830 ns = strchr(line, ':');
1831 if (!ns) {
9cbcfb59 1832 return tbfreq_fallback;
dc333cd6
AG		 1833 }
1834
9cbcfb59
GK		 1835 tbfreq_procfs = atoi(++ns);
1836
1837 /* 0 is certainly not acceptable by the guest, return fallback value */
1838 return tbfreq_procfs ? tbfreq_procfs : tbfreq_fallback;
1839}
1840
1841uint32_t kvmppc_get_tbfreq(void)
1842{
1843 static uint32_t cached_tbfreq;
1844
1845 if (!cached_tbfreq) {
1846 cached_tbfreq = kvmppc_get_tbfreq_procfs();
1847 }
dc333cd6 1848
9cbcfb59 1849 return cached_tbfreq;
dc333cd6 1850}
4513d923 1851
ef951443
ND		 1852bool kvmppc_get_host_serial(char **value)
1853{
1854 return g_file_get_contents("/proc/device-tree/system-id", value, NULL,
1855 NULL);
1856}
1857
1858bool kvmppc_get_host_model(char **value)
1859{
1860 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL);
1861}
1862
eadaada1
AG		 1863/* Try to find a device tree node for a CPU with clock-frequency property */
1864static int kvmppc_find_cpu_dt(char *buf, int buf_len)
1865{
1866 struct dirent *dirp;
1867 DIR *dp;
1868
c995e942
DG		 1869 dp = opendir(PROC_DEVTREE_CPU);
1870 if (!dp) {
eadaada1
AG		 1871 printf("Can't open directory " PROC_DEVTREE_CPU "\n");
1872 return -1;
1873 }
1874
1875 buf[0] = '\0';
1876 while ((dirp = readdir(dp)) != NULL) {
1877 FILE *f;
1878 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
1879 dirp->d_name);
1880 f = fopen(buf, "r");
1881 if (f) {
1882 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name);
1883 fclose(f);
1884 break;
1885 }
1886 buf[0] = '\0';
1887 }
1888 closedir(dp);
1889 if (buf[0] == '\0') {
1890 printf("Unknown host!\n");
1891 return -1;
1892 }
1893
1894 return 0;
1895}
1896
7d94a30b 1897static uint64_t kvmppc_read_int_dt(const char *filename)
eadaada1 1898{
9bc884b7
DG		 1899 union {
1900 uint32_t v32;
1901 uint64_t v64;
1902 } u;
eadaada1
AG		 1903 FILE *f;
1904 int len;
1905
7d94a30b 1906 f = fopen(filename, "rb");
eadaada1
AG		 1907 if (!f) {
1908 return -1;
1909 }
1910
9bc884b7 1911 len = fread(&u, 1, sizeof(u), f);
eadaada1
AG		 1912 fclose(f);
1913 switch (len) {
9bc884b7
DG		 1914 case 4:
1915 /* property is a 32-bit quantity */
1916 return be32_to_cpu(u.v32);
1917 case 8:
1918 return be64_to_cpu(u.v64);
eadaada1
AG		 1919 }
1920
1921 return 0;
1922}
1923
c995e942
DG		 1924/*
1925 * Read a CPU node property from the host device tree that's a single
7d94a30b 1926 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
c995e942
DG		 1927 * (can't find or open the property, or doesn't understand the format)
1928 */
7d94a30b
SB		 1929static uint64_t kvmppc_read_int_cpu_dt(const char *propname)
1930{
1931 char buf[PATH_MAX], *tmp;
1932 uint64_t val;
1933
1934 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
1935 return -1;
1936 }
1937
1938 tmp = g_strdup_printf("%s/%s", buf, propname);
1939 val = kvmppc_read_int_dt(tmp);
1940 g_free(tmp);
1941
1942 return val;
1943}
1944
9bc884b7
DG		 1945uint64_t kvmppc_get_clockfreq(void)
1946{
1947 return kvmppc_read_int_cpu_dt("clock-frequency");
1948}
1949
7d050527
SJS		 1950static int kvmppc_get_dec_bits(void)
1951{
1952 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits");
1953
1954 if (nr_bits > 0) {
1955 return nr_bits;
1956 }
1957 return 0;
1958}
1959
1a61a9ae 1960static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
db70b311
RH		 1961{
1962 CPUState *cs = env_cpu(env);
1a61a9ae 1963
6fd33a75 1964 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
1a61a9ae
SY		 1965 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
1966 return 0;
1967 }
1968
1969 return 1;
1970}
1971
1972int kvmppc_get_hasidle(CPUPPCState *env)
1973{
1974 struct kvm_ppc_pvinfo pvinfo;
1975
1976 if (!kvmppc_get_pvinfo(env, &pvinfo) &&
1977 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) {
1978 return 1;
1979 }
1980
1981 return 0;
1982}
1983
1328c2bf 1984int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len)
45024f09 1985{
c995e942 1986 uint32_t *hc = (uint32_t *)buf;
45024f09
AG		 1987 struct kvm_ppc_pvinfo pvinfo;
1988
1a61a9ae 1989 if (!kvmppc_get_pvinfo(env, &pvinfo)) {
45024f09 1990 memcpy(buf, pvinfo.hcall, buf_len);
45024f09
AG		 1991 return 0;
1992 }
45024f09
AG		 1993
1994 /*
d13fc32e 1995 * Fallback to always fail hypercalls regardless of endianness:
45024f09 1996 *
d13fc32e 1997 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
45024f09 1998 * li r3, -1
d13fc32e
AG		 1999 * b .+8 (becomes nop in wrong endian)
2000 * bswap32(li r3, -1)
45024f09
AG		 2001 */
2002
d13fc32e
AG		 2003 hc[0] = cpu_to_be32(0x08000048);
2004 hc[1] = cpu_to_be32(0x3860ffff);
2005 hc[2] = cpu_to_be32(0x48000008);
2006 hc[3] = cpu_to_be32(bswap32(0x3860ffff));
45024f09 2007
0ddbd053 2008 return 1;
45024f09
AG		 2009}
2010
026bfd89
DG		 2011static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall)
2012{
2013 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1);
2014}
2015
2016void kvmppc_enable_logical_ci_hcalls(void)
2017{
2018 /*
2019 * FIXME: it would be nice if we could detect the cases where
2020 * we're using a device which requires the in kernel
2021 * implementation of these hcalls, but the kernel lacks them and
2022 * produce a warning.
2023 */
2024 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD);
2025 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE);
2026}
2027
ef9971dd
AK		 2028void kvmppc_enable_set_mode_hcall(void)
2029{
2030 kvmppc_enable_hcall(kvm_state, H_SET_MODE);
2031}
2032
5145ad4f
NW		 2033void kvmppc_enable_clear_ref_mod_hcalls(void)
2034{
2035 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF);
2036 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD);
2037}
2038
68f9f708
SJS		 2039void kvmppc_enable_h_page_init(void)
2040{
2041 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT);
2042}
2043
82123b75
BR		 2044void kvmppc_enable_h_rpt_invalidate(void)
2045{
2046 kvmppc_enable_hcall(kvm_state, H_RPT_INVALIDATE);
2047}
2048
1bc22652 2049void kvmppc_set_papr(PowerPCCPU *cpu)
f61b4bed 2050{
1bc22652 2051 CPUState *cs = CPU(cpu);
f61b4bed
AG		 2052 int ret;
2053
da20aed1
DG		 2054 if (!kvm_enabled()) {
2055 return;
2056 }
2057
48add816 2058 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0);
f61b4bed 2059 if (ret) {
072ed5f2
TH		 2060 error_report("This vCPU type or KVM version does not support PAPR");
2061 exit(1);
94135e81 2062 }
9b00ea49 2063
c995e942
DG		 2064 /*
2065 * Update the capability flag so we sync the right information
2066 * with kvm
2067 */
9b00ea49 2068 cap_papr = 1;
f61b4bed
AG		 2069}
2070
d6e166c0 2071int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr)
6db5bb0f 2072{
d6e166c0 2073 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr);
6db5bb0f
AK		 2074}
2075
5b95b8b9
AG		 2076void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy)
2077{
5b95b8b9 2078 CPUState *cs = CPU(cpu);
5b95b8b9
AG		 2079 int ret;
2080
48add816 2081 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy);
5b95b8b9 2082 if (ret && mpic_proxy) {
072ed5f2
TH		 2083 error_report("This KVM version does not support EPR");
2084 exit(1);
5b95b8b9
AG		 2085 }
2086}
2087
ec010c00
NP		 2088bool kvmppc_get_fwnmi(void)
2089{
2090 return cap_fwnmi;
2091}
2092
aef92d87 2093int kvmppc_set_fwnmi(PowerPCCPU *cpu)
9d953ce4 2094{
9d953ce4
AP		 2095 CPUState *cs = CPU(cpu);
2096
2097 return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0);
2098}
2099
e97c3636
DG		 2100int kvmppc_smt_threads(void)
2101{
2102 return cap_ppc_smt ? cap_ppc_smt : 1;
2103}
2104
fa98fbfc
SB		 2105int kvmppc_set_smt_threads(int smt)
2106{
2107 int ret;
2108
2109 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0);
2110 if (!ret) {
2111 cap_ppc_smt = smt;
2112 }
2113 return ret;
2114}
2115
0c115681 2116void kvmppc_error_append_smt_possible_hint(Error *const *errp)
fa98fbfc
SB		 2117{
2118 int i;
2119 GString *g;
2120 char *s;
2121
2122 assert(kvm_enabled());
2123 if (cap_ppc_smt_possible) {
2124 g = g_string_new("Available VSMT modes:");
2125 for (i = 63; i >= 0; i--) {
2126 if ((1UL << i) & cap_ppc_smt_possible) {
2127 g_string_append_printf(g, " %lu", (1UL << i));
2128 }
2129 }
2130 s = g_string_free(g, false);
1a639fdf 2131 error_append_hint(errp, "%s.\n", s);
fa98fbfc
SB		 2132 g_free(s);
2133 } else {
1a639fdf 2134 error_append_hint(errp,
fa98fbfc
SB		 2135 "This KVM seems to be too old to support VSMT.\n");
2136 }
2137}
2138
2139
7f763a5d 2140#ifdef TARGET_PPC64
6a84737c 2141uint64_t kvmppc_vrma_limit(unsigned int hash_shift)
7f763a5d 2142{
f36951c1
DG		 2143 struct kvm_ppc_smmu_info info;
2144 long rampagesize, best_page_shift;
2145 int i;
2146
c995e942
DG		 2147 /*
2148 * Find the largest hardware supported page size that's less than
2149 * or equal to the (logical) backing page size of guest RAM
2150 */
ab256960 2151 kvm_get_smmu_info(&info, &error_fatal);
905b7ee4 2152 rampagesize = qemu_minrampagesize();
f36951c1
DG		 2153 best_page_shift = 0;
2154
2155 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) {
2156 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i];
2157
2158 if (!sps->page_shift) {
2159 continue;
2160 }
2161
2162 if ((sps->page_shift > best_page_shift)
2163 && ((1UL << sps->page_shift) <= rampagesize)) {
2164 best_page_shift = sps->page_shift;
2165 }
2166 }
2167
6a84737c 2168 return 1ULL << (best_page_shift + hash_shift - 7);
7f763a5d
DG		 2169}
2170#endif
2171
da95324e
AK		 2172bool kvmppc_spapr_use_multitce(void)
2173{
2174 return cap_spapr_multitce;
2175}
2176
3dc410ae
AK		 2177int kvmppc_spapr_enable_inkernel_multitce(void)
2178{
2179 int ret;
2180
2181 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2182 H_PUT_TCE_INDIRECT, 1);
2183 if (!ret) {
2184 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2185 H_STUFF_TCE, 1);
2186 }
2187
2188 return ret;
2189}
2190
d6ee2a7c
AK		 2191void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift,
2192 uint64_t bus_offset, uint32_t nb_table,
2193 int *pfd, bool need_vfio)
0f5cb298 2194{
0f5cb298
DG		 2195 long len;
2196 int fd;
2197 void *table;
2198
c995e942
DG		 2199 /*
2200 * Must set fd to -1 so we don't try to munmap when called for
b5aec396
DG		 2201 * destroying the table, which the upper layers -will- do
2202 */
2203 *pfd = -1;
6a81dd17 2204 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) {
0f5cb298
DG		 2205 return NULL;
2206 }
2207
d6ee2a7c
AK		 2208 if (cap_spapr_tce_64) {
2209 struct kvm_create_spapr_tce_64 args = {
2210 .liobn = liobn,
2211 .page_shift = page_shift,
2212 .offset = bus_offset >> page_shift,
2213 .size = nb_table,
2214 .flags = 0
2215 };
2216 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args);
2217 if (fd < 0) {
2218 fprintf(stderr,
2219 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2220 liobn);
2221 return NULL;
2222 }
2223 } else if (cap_spapr_tce) {
2224 uint64_t window_size = (uint64_t) nb_table << page_shift;
2225 struct kvm_create_spapr_tce args = {
2226 .liobn = liobn,
2227 .window_size = window_size,
2228 };
2229 if ((window_size != args.window_size) || bus_offset) {
2230 return NULL;
2231 }
2232 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args);
2233 if (fd < 0) {
2234 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n",
2235 liobn);
2236 return NULL;
2237 }
2238 } else {
0f5cb298
DG		 2239 return NULL;
2240 }
2241
d6ee2a7c 2242 len = nb_table * sizeof(uint64_t);
0f5cb298
DG		 2243 /* FIXME: round this up to page size */
2244
c995e942 2245 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
0f5cb298 2246 if (table == MAP_FAILED) {
b5aec396
DG		 2247 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n",
2248 liobn);
0f5cb298
DG		 2249 close(fd);
2250 return NULL;
2251 }
2252
2253 *pfd = fd;
2254 return table;
2255}
2256
523e7b8a 2257int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table)
0f5cb298
DG		 2258{
2259 long len;
2260
2261 if (fd < 0) {
2262 return -1;
2263 }
2264
523e7b8a 2265 len = nb_table * sizeof(uint64_t);
0f5cb298
DG		 2266 if ((munmap(table, len) < 0) ||
2267 (close(fd) < 0)) {
b5aec396
DG		 2268 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s",
2269 strerror(errno));
0f5cb298
DG		 2270 /* Leak the table */
2271 }
2272
2273 return 0;
2274}
2275
7f763a5d
DG		 2276int kvmppc_reset_htab(int shift_hint)
2277{
2278 uint32_t shift = shift_hint;
2279
ace9a2cb
DG		 2280 if (!kvm_enabled()) {
2281 /* Full emulation, tell caller to allocate htab itself */
2282 return 0;
2283 }
6977afda 2284 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) {
7f763a5d
DG		 2285 int ret;
2286 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift);
ace9a2cb 2287 if (ret == -ENOTTY) {
c995e942
DG		 2288 /*
2289 * At least some versions of PR KVM advertise the
ace9a2cb
DG		 2290 * capability, but don't implement the ioctl(). Oops.
2291 * Return 0 so that we allocate the htab in qemu, as is
c995e942
DG		 2292 * correct for PR.
2293 */
ace9a2cb
DG		 2294 return 0;
2295 } else if (ret < 0) {
7f763a5d
DG		 2296 return ret;
2297 }
2298 return shift;
2299 }
2300
c995e942
DG		 2301 /*
2302 * We have a kernel that predates the htab reset calls. For PR
ace9a2cb 2303 * KVM, we need to allocate the htab ourselves, for an HV KVM of
c995e942
DG		 2304 * this era, it has allocated a 16MB fixed size hash table
2305 * already.
2306 */
96c9cff0 2307 if (kvmppc_is_pr(kvm_state)) {
ace9a2cb
DG		 2308 /* PR - tell caller to allocate htab */
2309 return 0;
2310 } else {
2311 /* HV - assume 16MB kernel allocated htab */
2312 return 24;
2313 }
7f763a5d
DG		 2314}
2315
a1e98583
DG		 2316static inline uint32_t mfpvr(void)
2317{
2318 uint32_t pvr;
2319
2320 asm ("mfpvr %0"
2321 : "=r"(pvr));
2322 return pvr;
2323}
2324
a7342588
DG		 2325static void alter_insns(uint64_t *word, uint64_t flags, bool on)
2326{
2327 if (on) {
2328 *word |= flags;
2329 } else {
2330 *word &= ~flags;
2331 }
2332}
2333
2985b86b
AF		 2334static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
2335{
2336 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
0cbad81f
DG		 2337 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
2338 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
a1e98583 2339
cfe34f44 2340 /* Now fix up the class with information we can query from the host */
3bc9ccc0 2341 pcc->pvr = mfpvr();
a7342588 2342
3f2ca480
DG		 2343 alter_insns(&pcc->insns_flags, PPC_ALTIVEC,
2344 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC);
2345 alter_insns(&pcc->insns_flags2, PPC2_VSX,
2346 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX);
2347 alter_insns(&pcc->insns_flags2, PPC2_DFP,
2348 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP);
0cbad81f
DG		 2349
2350 if (dcache_size != -1) {
2351 pcc->l1_dcache_size = dcache_size;
2352 }
2353
2354 if (icache_size != -1) {
2355 pcc->l1_icache_size = icache_size;
2356 }
c64abd1f
SB		 2357
2358#if defined(TARGET_PPC64)
2359 pcc->radix_page_info = kvm_get_radix_page_info();
5f3066d8
DG		 2360
2361 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
2362 /*
2363 * POWER9 DD1 has some bugs which make it not really ISA 3.00
2364 * compliant. More importantly, advertising ISA 3.00
2365 * architected mode may prevent guests from activating
2366 * necessary DD1 workarounds.
2367 */
2368 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07
2369 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05);
2370 }
c64abd1f 2371#endif /* defined(TARGET_PPC64) */
a1e98583
DG		 2372}
2373
3b961124
SY		 2374bool kvmppc_has_cap_epr(void)
2375{
2376 return cap_epr;
2377}
2378
87a91de6
AG		 2379bool kvmppc_has_cap_fixup_hcalls(void)
2380{
2381 return cap_fixup_hcalls;
2382}
2383
bac3bf28
TH		 2384bool kvmppc_has_cap_htm(void)
2385{
2386 return cap_htm;
2387}
2388
cf1c4cce
SB		 2389bool kvmppc_has_cap_mmu_radix(void)
2390{
2391 return cap_mmu_radix;
2392}
2393
2394bool kvmppc_has_cap_mmu_hash_v3(void)
2395{
2396 return cap_mmu_hash_v3;
2397}
2398
072f416a
SJS		 2399static bool kvmppc_power8_host(void)
2400{
2401 bool ret = false;
2402#ifdef TARGET_PPC64
2403 {
2404 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
2405 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
2406 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
2407 (base_pvr == CPU_POWERPC_POWER8_BASE);
2408 }
2409#endif /* TARGET_PPC64 */
2410 return ret;
2411}
2412
8fea7044
SJS		 2413static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
2414{
072f416a
SJS		 2415 bool l1d_thread_priv_req = !kvmppc_power8_host();
2416
8fea7044
SJS		 2417 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
2418 return 2;
072f416a
SJS		 2419 } else if ((!l1d_thread_priv_req ||
2420 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
8fea7044
SJS		 2421 (c.character & c.character_mask
2422 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
2423 return 1;
2424 }
2425
2426 return 0;
2427}
2428
2429static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)
2430{
2431 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) {
2432 return 2;
2433 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) {
2434 return 1;
2435 }
2436
2437 return 0;
2438}
2439
2440static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
2441{
399b2896
SJS		 2442 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) &&
2443 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) &&
2444 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) {
2445 return SPAPR_CAP_FIXED_NA;
2446 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) {
2447 return SPAPR_CAP_WORKAROUND;
2448 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
8fea7044
SJS		 2449 return SPAPR_CAP_FIXED_CCD;
2450 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) {
2451 return SPAPR_CAP_FIXED_IBS;
2452 }
2453
2454 return 0;
2455}
2456
8ff43ee4
SJS		 2457static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c)
2458{
2459 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) {
2460 return 1;
2461 }
2462 return 0;
2463}
2464
38afd772
CLG		 2465bool kvmppc_has_cap_xive(void)
2466{
2467 return cap_xive;
2468}
2469
8acc2ae5
SJS		 2470static void kvmppc_get_cpu_characteristics(KVMState *s)
2471{
2472 struct kvm_ppc_cpu_char c;
2473 int ret;
2474
2475 /* Assume broken */
2476 cap_ppc_safe_cache = 0;
2477 cap_ppc_safe_bounds_check = 0;
2478 cap_ppc_safe_indirect_branch = 0;
2479
2480 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR);
2481 if (!ret) {
2482 return;
2483 }
2484 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c);
2485 if (ret < 0) {
2486 return;
2487 }
8fea7044
SJS		 2488
2489 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c);
2490 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c);
2491 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c);
8ff43ee4
SJS		 2492 cap_ppc_count_cache_flush_assist =
2493 parse_cap_ppc_count_cache_flush_assist(c);
8acc2ae5
SJS		 2494}
2495
2496int kvmppc_get_cap_safe_cache(void)
2497{
2498 return cap_ppc_safe_cache;
2499}
2500
2501int kvmppc_get_cap_safe_bounds_check(void)
2502{
2503 return cap_ppc_safe_bounds_check;
2504}
2505
2506int kvmppc_get_cap_safe_indirect_branch(void)
2507{
2508 return cap_ppc_safe_indirect_branch;
2509}
2510
8ff43ee4
SJS		 2511int kvmppc_get_cap_count_cache_flush_assist(void)
2512{
2513 return cap_ppc_count_cache_flush_assist;
2514}
2515
b9a477b7
SJS		 2516bool kvmppc_has_cap_nested_kvm_hv(void)
2517{
2518 return !!cap_ppc_nested_kvm_hv;
2519}
2520
2521int kvmppc_set_cap_nested_kvm_hv(int enable)
2522{
2523 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable);
2524}
2525
9ded780c
AK		 2526bool kvmppc_has_cap_spapr_vfio(void)
2527{
2528 return cap_spapr_vfio;
2529}
2530
7d050527
SJS		 2531int kvmppc_get_cap_large_decr(void)
2532{
2533 return cap_large_decr;
2534}
2535
2536int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable)
2537{
2538 CPUState *cs = CPU(cpu);
2539 uint64_t lpcr;
2540
2541 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2542 /* Do we need to modify the LPCR? */
2543 if (!!(lpcr & LPCR_LD) != !!enable) {
2544 if (enable) {
2545 lpcr |= LPCR_LD;
2546 } else {
2547 lpcr &= ~LPCR_LD;
2548 }
2549 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2550 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2551
2552 if (!!(lpcr & LPCR_LD) != !!enable) {
2553 return -1;
2554 }
2555 }
2556
2557 return 0;
2558}
2559
82123b75
BR		 2560int kvmppc_has_cap_rpt_invalidate(void)
2561{
2562 return cap_rpt_invalidate;
2563}
2564
52b2519c
TH		 2565PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void)
2566{
2567 uint32_t host_pvr = mfpvr();
2568 PowerPCCPUClass *pvr_pcc;
2569
2570 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
2571 if (pvr_pcc == NULL) {
2572 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr);
2573 }
2574
2575 return pvr_pcc;
2576}
2577
165dc3ed
DG		 2578static void pseries_machine_class_fixup(ObjectClass *oc, void *opaque)
2579{
2580 MachineClass *mc = MACHINE_CLASS(oc);
2581
2582 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU;
2583}
2584
2585static int kvm_ppc_register_host_cpu_type(void)
5ba4576b
AF		 2586{
2587 TypeInfo type_info = {
2588 .name = TYPE_HOST_POWERPC_CPU,
5ba4576b
AF		 2589 .class_init = kvmppc_host_cpu_class_init,
2590 };
5ba4576b 2591 PowerPCCPUClass *pvr_pcc;
92e926e1 2592 ObjectClass *oc;
5b79b1ca 2593 DeviceClass *dc;
715d4b96 2594 int i;
5ba4576b 2595
52b2519c 2596 pvr_pcc = kvm_ppc_get_host_cpu_class();
5ba4576b
AF		 2597 if (pvr_pcc == NULL) {
2598 return -1;
2599 }
2600 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc));
2601 type_register(&type_info);
165dc3ed
DG		 2602 /* override TCG default cpu type with 'host' cpu model */
2603 object_class_foreach(pseries_machine_class_fixup, TYPE_SPAPR_MACHINE,
2604 false, NULL);
5b79b1ca 2605
92e926e1
GK		 2606 oc = object_class_by_name(type_info.name);
2607 g_assert(oc);
2608
715d4b96
TH		 2609 /*
2610 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2611 * we want "POWER8" to be a "family" alias that points to the current
2612 * host CPU type, too)
2613 */
2614 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc));
2615 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
c5354f54 2616 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) {
715d4b96
TH		 2617 char *suffix;
2618
2619 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc));
c9137065 2620 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX);
715d4b96
TH		 2621 if (suffix) {
2622 *suffix = 0;
2623 }
715d4b96
TH		 2624 break;
2625 }
2626 }
2627
5ba4576b
AF		 2628 return 0;
2629}
2630
feaa64c4
DG		 2631int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function)
2632{
2633 struct kvm_rtas_token_args args = {
2634 .token = token,
2635 };
2636
2637 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) {
2638 return -ENOENT;
2639 }
2640
7701aeed 2641 strncpy(args.name, function, sizeof(args.name) - 1);
feaa64c4
DG		 2642
2643 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args);
2644}
12b1143b 2645
14b0d748 2646int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp)
e68cb8b4
AK		 2647{
2648 struct kvm_get_htab_fd s = {
2649 .flags = write ? KVM_GET_HTAB_WRITE : 0,
14b0d748 2650 .start_index = index,
e68cb8b4 2651 };
82be8e73 2652 int ret;
e68cb8b4
AK		 2653
2654 if (!cap_htab_fd) {
14b0d748
GK		 2655 error_setg(errp, "KVM version doesn't support %s the HPT",
2656 write ? "writing" : "reading");
82be8e73
GK		 2657 return -ENOTSUP;
2658 }
2659
2660 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s);
2661 if (ret < 0) {
14b0d748
GK		 2662 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s",
2663 write ? "writing" : "reading", write ? "to" : "from",
2664 strerror(errno));
82be8e73 2665 return -errno;
e68cb8b4
AK		 2666 }
2667
82be8e73 2668 return ret;
e68cb8b4
AK		 2669}
2670
2671int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns)
2672{
bc72ad67 2673 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
e68cb8b4
AK		 2674 uint8_t buf[bufsize];
2675 ssize_t rc;
2676
2677 do {
2678 rc = read(fd, buf, bufsize);
2679 if (rc < 0) {
2680 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n",
2681 strerror(errno));
2682 return rc;
2683 } else if (rc) {
e094c4c1
CLG		 2684 uint8_t *buffer = buf;
2685 ssize_t n = rc;
2686 while (n) {
2687 struct kvm_get_htab_header *head =
2688 (struct kvm_get_htab_header *) buffer;
2689 size_t chunksize = sizeof(*head) +
2690 HASH_PTE_SIZE_64 * head->n_valid;
2691
2692 qemu_put_be32(f, head->index);
2693 qemu_put_be16(f, head->n_valid);
2694 qemu_put_be16(f, head->n_invalid);
2695 qemu_put_buffer(f, (void *)(head + 1),
2696 HASH_PTE_SIZE_64 * head->n_valid);
2697
2698 buffer += chunksize;
2699 n -= chunksize;
2700 }
e68cb8b4
AK		 2701 }
2702 } while ((rc != 0)
c995e942
DG		 2703 && ((max_ns < 0) ||
2704 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns)));
e68cb8b4
AK		 2705
2706 return (rc == 0) ? 1 : 0;
2707}
2708
2709int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
0a06e4d6 2710 uint16_t n_valid, uint16_t n_invalid, Error **errp)
e68cb8b4
AK		 2711{
2712 struct kvm_get_htab_header *buf;
c995e942 2713 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64;
e68cb8b4
AK		 2714 ssize_t rc;
2715
2716 buf = alloca(chunksize);
e68cb8b4
AK		 2717 buf->index = index;
2718 buf->n_valid = n_valid;
2719 buf->n_invalid = n_invalid;
2720
c995e942 2721 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid);
e68cb8b4
AK		 2722
2723 rc = write(fd, buf, chunksize);
2724 if (rc < 0) {
0a06e4d6
GK		 2725 error_setg_errno(errp, errno, "Error writing the KVM hash table");
2726 return -errno;
e68cb8b4
AK		 2727 }
2728 if (rc != chunksize) {
2729 /* We should never get a short write on a single chunk */
0a06e4d6
GK		 2730 error_setg(errp, "Short write while restoring the KVM hash table");
2731 return -ENOSPC;
e68cb8b4
AK		 2732 }
2733 return 0;
2734}
2735
20d695a9 2736bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
4513d923
GN		 2737{
2738 return true;
2739}
a1b87fe0 2740
82169660
SW		 2741void kvm_arch_init_irq_routing(KVMState *s)
2742{
2743}
c65f9a07 2744
1ad9f0a4 2745void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n)
7c43bca0 2746{
1ad9f0a4
DG		 2747 int fd, rc;
2748 int i;
7c43bca0 2749
14b0d748 2750 fd = kvmppc_get_htab_fd(false, ptex, &error_abort);
7c43bca0 2751
1ad9f0a4
DG		 2752 i = 0;
2753 while (i < n) {
2754 struct kvm_get_htab_header *hdr;
2755 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP;
2756 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64];
7c43bca0 2757
1ad9f0a4
DG		 2758 rc = read(fd, buf, sizeof(buf));
2759 if (rc < 0) {
2760 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2761 }
7c43bca0 2762
1ad9f0a4
DG		 2763 hdr = (struct kvm_get_htab_header *)buf;
2764 while ((i < n) && ((char *)hdr < (buf + rc))) {
a36593e1 2765 int invalid = hdr->n_invalid, valid = hdr->n_valid;
7c43bca0 2766
1ad9f0a4
DG		 2767 if (hdr->index != (ptex + i)) {
2768 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2769 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i);
2770 }
2771
a36593e1
AK		 2772 if (n - i < valid) {
2773 valid = n - i;
2774 }
2775 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid);
2776 i += valid;
7c43bca0 2777
1ad9f0a4
DG		 2778 if ((n - i) < invalid) {
2779 invalid = n - i;
2780 }
2781 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64);
a36593e1 2782 i += invalid;
1ad9f0a4
DG		 2783
2784 hdr = (struct kvm_get_htab_header *)
2785 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid);
2786 }
2787 }
2788
2789 close(fd);
7c43bca0 2790}
c1385933 2791
1ad9f0a4 2792void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1)
c1385933 2793{
1ad9f0a4 2794 int fd, rc;
1ad9f0a4
DG		 2795 struct {
2796 struct kvm_get_htab_header hdr;
2797 uint64_t pte0;
2798 uint64_t pte1;
2799 } buf;
c1385933 2800
14b0d748 2801 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort);
c1385933 2802
1ad9f0a4
DG		 2803 buf.hdr.n_valid = 1;
2804 buf.hdr.n_invalid = 0;
2805 buf.hdr.index = ptex;
2806 buf.pte0 = cpu_to_be64(pte0);
2807 buf.pte1 = cpu_to_be64(pte1);
c1385933 2808
1ad9f0a4
DG		 2809 rc = write(fd, &buf, sizeof(buf));
2810 if (rc != sizeof(buf)) {
2811 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2812 }
2813 close(fd);
c1385933 2814}
9e03a040
FB		 2815
2816int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 2817 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040
FB		 2818{
2819 return 0;
2820}
1850b6b7 2821
38d87493
PX		 2822int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
2823 int vector, PCIDevice *dev)
2824{
2825 return 0;
2826}
2827
2828int kvm_arch_release_virq_post(int virq)
2829{
2830 return 0;
2831}
2832
1850b6b7
EA		 2833int kvm_arch_msi_data_to_gsi(uint32_t data)
2834{
2835 return data & 0xffff;
2836}
4d9392be 2837
9ac703ac
AP		 2838#if defined(TARGET_PPC64)
2839int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run)
2840{
211a7784 2841 uint16_t flags = run->flags & KVM_RUN_PPC_NMI_DISP_MASK;
81fe70e4 2842
9ac703ac
AP		 2843 cpu_synchronize_state(CPU(cpu));
2844
211a7784 2845 spapr_mce_req_event(cpu, flags == KVM_RUN_PPC_NMI_DISP_FULLY_RECOV);
9ac703ac
AP		 2846
2847 return 0;
2848}
2849#endif
2850
4d9392be
TH		 2851int kvmppc_enable_hwrng(void)
2852{
2853 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) {
2854 return -1;
2855 }
2856
2857 return kvmppc_enable_hcall(kvm_state, H_RANDOM);
2858}
30f4b05b
DG		 2859
2860void kvmppc_check_papr_resize_hpt(Error **errp)
2861{
2862 if (!kvm_enabled()) {
b55d295e
DG		 2863 return; /* No KVM, we're good */
2864 }
2865
2866 if (cap_resize_hpt) {
2867 return; /* Kernel has explicit support, we're good */
30f4b05b
DG		 2868 }
2869
b55d295e
DG		 2870 /* Otherwise fallback on looking for PR KVM */
2871 if (kvmppc_is_pr(kvm_state)) {
2872 return;
2873 }
30f4b05b
DG		 2874
2875 error_setg(errp,
2876 "Hash page table resizing not available with this KVM version");
2877}
b55d295e
DG		 2878
2879int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift)
2880{
2881 CPUState *cs = CPU(cpu);
2882 struct kvm_ppc_resize_hpt rhpt = {
2883 .flags = flags,
2884 .shift = shift,
2885 };
2886
2887 if (!cap_resize_hpt) {
2888 return -ENOSYS;
2889 }
2890
2891 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt);
2892}
2893
2894int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift)
2895{
2896 CPUState *cs = CPU(cpu);
2897 struct kvm_ppc_resize_hpt rhpt = {
2898 .flags = flags,
2899 .shift = shift,
2900 };
2901
2902 if (!cap_resize_hpt) {
2903 return -ENOSYS;
2904 }
2905
2906 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt);
2907}
2908
c363a37a
DHB		 2909/*
2910 * This is a helper function to detect a post migration scenario
2911 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2912 * the guest kernel can't handle a PVR value other than the actual host
2913 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2914 *
2915 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2916 * (so, we're HV), return true. The workaround itself is done in
2917 * cpu_post_load.
2918 *
2919 * The order here is important: we'll only check for KVM PR as a
2920 * fallback if the guest kernel can't handle the situation itself.
2921 * We need to avoid as much as possible querying the running KVM type
2922 * in QEMU level.
2923 */
2924bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu)
2925{
2926 CPUState *cs = CPU(cpu);
2927
2928 if (!kvm_enabled()) {
2929 return false;
2930 }
2931
2932 if (cap_ppc_pvr_compat) {
2933 return false;
2934 }
2935
2936 return !kvmppc_is_pr(cs->kvm_state);
2937}
a84f7179
ND		 2938
2939void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online)
2940{
2941 CPUState *cs = CPU(cpu);
2942
2943 if (kvm_enabled()) {
2944 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online);
2945 }
2946}
9723295a
GK		 2947
2948void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset)
2949{
2950 CPUState *cs = CPU(cpu);
2951
2952 if (kvm_enabled()) {
2953 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset);
2954 }
2955}
92a5199b
TL		 2956
2957bool kvm_arch_cpu_check_are_resettable(void)
2958{
2959 return true;
2960}
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