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Clean up inclusion of sysemu/sysemu.h
[mirror_qemu.git] / target / ppc / kvm.c
CommitLineData
d76d1650
AJ		 1/*
2 * PowerPC implementation of KVM hooks
3 *
4 * Copyright IBM Corp. 2007
90dc8812 5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
d76d1650
AJ		 6 *
7 * Authors:
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
14 *
15 */
16
0d75590d 17#include "qemu/osdep.h"
eadaada1 18#include <dirent.h>
d76d1650 19#include <sys/ioctl.h>
4656e1f0 20#include <sys/vfs.h>
d76d1650
AJ		 21
22#include <linux/kvm.h>
23
24#include "qemu-common.h"
30f4b05b 25#include "qapi/error.h"
072ed5f2 26#include "qemu/error-report.h"
33c11879 27#include "cpu.h"
715d4b96 28#include "cpu-models.h"
1de7afc9 29#include "qemu/timer.h"
b3946626 30#include "sysemu/hw_accel.h"
d76d1650 31#include "kvm_ppc.h"
9c17d615
PB		 32#include "sysemu/cpus.h"
33#include "sysemu/device_tree.h"
d5aea6f3 34#include "mmu-hash64.h"
d76d1650 35
f61b4bed 36#include "hw/sysbus.h"
0d09e41a 37#include "hw/ppc/spapr.h"
7ebaf795 38#include "hw/ppc/spapr_cpu_core.h"
650d103d 39#include "hw/hw.h"
98a8b524 40#include "hw/ppc/ppc.h"
ca77ee28 41#include "migration/qemu-file-types.h"
31f2cb8f 42#include "sysemu/watchdog.h"
b36f100e 43#include "trace.h"
88365d17 44#include "exec/gdbstub.h"
4c663752 45#include "exec/memattrs.h"
9c607668 46#include "exec/ram_addr.h"
2d103aae 47#include "sysemu/hostmem.h"
f348b6d1 48#include "qemu/cutils.h"
db725815 49#include "qemu/main-loop.h"
9c607668 50#include "qemu/mmap-alloc.h"
f3d9f303 51#include "elf.h"
c64abd1f 52#include "sysemu/kvm_int.h"
f61b4bed 53
eadaada1
AG		 54#define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
55
94a8d39a
JK		 56const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
57 KVM_CAP_LAST_INFO
58};
59
c995e942
DG		 60static int cap_interrupt_unset;
61static int cap_interrupt_level;
90dc8812 62static int cap_segstate;
90dc8812 63static int cap_booke_sregs;
e97c3636 64static int cap_ppc_smt;
fa98fbfc 65static int cap_ppc_smt_possible;
0f5cb298 66static int cap_spapr_tce;
d6ee2a7c 67static int cap_spapr_tce_64;
da95324e 68static int cap_spapr_multitce;
9bb62a07 69static int cap_spapr_vfio;
f1af19d7 70static int cap_hior;
d67d40ea 71static int cap_one_reg;
3b961124 72static int cap_epr;
31f2cb8f 73static int cap_ppc_watchdog;
9b00ea49 74static int cap_papr;
e68cb8b4 75static int cap_htab_fd;
87a91de6 76static int cap_fixup_hcalls;
bac3bf28 77static int cap_htm; /* Hardware transactional memory support */
cf1c4cce
SB		 78static int cap_mmu_radix;
79static int cap_mmu_hash_v3;
38afd772 80static int cap_xive;
b55d295e 81static int cap_resize_hpt;
c363a37a 82static int cap_ppc_pvr_compat;
8acc2ae5
SJS		 83static int cap_ppc_safe_cache;
84static int cap_ppc_safe_bounds_check;
85static int cap_ppc_safe_indirect_branch;
8ff43ee4 86static int cap_ppc_count_cache_flush_assist;
b9a477b7 87static int cap_ppc_nested_kvm_hv;
7d050527 88static int cap_large_decr;
fc87e185 89
3c902d44
BB		 90static uint32_t debug_inst_opcode;
91
c995e942
DG		 92/*
93 * XXX We have a race condition where we actually have a level triggered
c821c2bd
AG		 94 * interrupt, but the infrastructure can't expose that yet, so the guest
95 * takes but ignores it, goes to sleep and never gets notified that there's
96 * still an interrupt pending.
c6a94ba5 97 *
c821c2bd
AG		 98 * As a quick workaround, let's just wake up again 20 ms after we injected
99 * an interrupt. That way we can assure that we're always reinjecting
100 * interrupts in case the guest swallowed them.
c6a94ba5
AG		 101 */
102static QEMUTimer *idle_timer;
103
d5a68146 104static void kvm_kick_cpu(void *opaque)
c6a94ba5 105{
d5a68146 106 PowerPCCPU *cpu = opaque;
d5a68146 107
c08d7424 108 qemu_cpu_kick(CPU(cpu));
c6a94ba5
AG		 109}
110
c995e942
DG		 111/*
112 * Check whether we are running with KVM-PR (instead of KVM-HV). This
96c9cff0
TH		 113 * should only be used for fallback tests - generally we should use
114 * explicit capabilities for the features we want, rather than
c995e942
DG		 115 * assuming what is/isn't available depending on the KVM variant.
116 */
96c9cff0
TH		 117static bool kvmppc_is_pr(KVMState *ks)
118{
119 /* Assume KVM-PR if the GET_PVINFO capability is available */
70a0c19e 120 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0;
96c9cff0
TH		 121}
122
2e9c10eb 123static int kvm_ppc_register_host_cpu_type(MachineState *ms);
8acc2ae5 124static void kvmppc_get_cpu_characteristics(KVMState *s);
7d050527 125static int kvmppc_get_dec_bits(void);
5ba4576b 126
b16565b3 127int kvm_arch_init(MachineState *ms, KVMState *s)
d76d1650 128{
fc87e185 129 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
fc87e185 130 cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL);
90dc8812 131 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
90dc8812 132 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
6977afda 133 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE);
0f5cb298 134 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
d6ee2a7c 135 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64);
da95324e 136 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE);
9ded780c 137 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO);
d67d40ea 138 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
f1af19d7 139 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
3b961124 140 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
31f2cb8f 141 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG);
c995e942
DG		 142 /*
143 * Note: we don't set cap_papr here, because this capability is
144 * only activated after this by kvmppc_set_papr()
145 */
6977afda 146 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD);
87a91de6 147 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL);
fa98fbfc 148 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT);
bac3bf28 149 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM);
cf1c4cce
SB		 150 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX);
151 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
38afd772 152 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE);
b55d295e 153 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT);
8acc2ae5 154 kvmppc_get_cpu_characteristics(s);
b9a477b7 155 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV);
7d050527 156 cap_large_decr = kvmppc_get_dec_bits();
c363a37a
DHB		 157 /*
158 * Note: setting it to false because there is not such capability
159 * in KVM at this moment.
160 *
161 * TODO: call kvm_vm_check_extension() with the right capability
c995e942
DG		 162 * after the kernel starts implementing it.
163 */
c363a37a 164 cap_ppc_pvr_compat = false;
fc87e185
AG		 165
166 if (!cap_interrupt_level) {
167 fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the "
168 "VM to stall at times!\n");
169 }
170
2e9c10eb 171 kvm_ppc_register_host_cpu_type(ms);
5ba4576b 172
d76d1650
AJ		 173 return 0;
174}
175
d525ffab
PB		 176int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
177{
178 return 0;
179}
180
1bc22652 181static int kvm_arch_sync_sregs(PowerPCCPU *cpu)
d76d1650 182{
1bc22652
AF		 183 CPUPPCState *cenv = &cpu->env;
184 CPUState *cs = CPU(cpu);
861bbc80 185 struct kvm_sregs sregs;
5666ca4a
SW		 186 int ret;
187
188 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
c995e942
DG		 189 /*
190 * What we're really trying to say is "if we're on BookE, we
191 * use the native PVR for now". This is the only sane way to
192 * check it though, so we potentially confuse users that they
193 * can run BookE guests on BookS. Let's hope nobody dares
194 * enough :)
195 */
5666ca4a
SW		 196 return 0;
197 } else {
90dc8812 198 if (!cap_segstate) {
64e07be5
AG		 199 fprintf(stderr, "kvm error: missing PVR setting capability\n");
200 return -ENOSYS;
5666ca4a 201 }
5666ca4a
SW		 202 }
203
1bc22652 204 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);
5666ca4a
SW		 205 if (ret) {
206 return ret;
207 }
861bbc80
AG		 208
209 sregs.pvr = cenv->spr[SPR_PVR];
1bc22652 210 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);
5666ca4a
SW		 211}
212
93dd5e85 213/* Set up a shared TLB array with KVM */
1bc22652 214static int kvm_booke206_tlb_init(PowerPCCPU *cpu)
93dd5e85 215{
1bc22652
AF		 216 CPUPPCState *env = &cpu->env;
217 CPUState *cs = CPU(cpu);
93dd5e85
SW		 218 struct kvm_book3e_206_tlb_params params = {};
219 struct kvm_config_tlb cfg = {};
93dd5e85
SW		 220 unsigned int entries = 0;
221 int ret, i;
222
223 if (!kvm_enabled() ||
a60f24b5 224 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) {
93dd5e85
SW		 225 return 0;
226 }
227
228 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);
229
230 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
231 params.tlb_sizes[i] = booke206_tlb_size(env, i);
232 params.tlb_ways[i] = booke206_tlb_ways(env, i);
233 entries += params.tlb_sizes[i];
234 }
235
236 assert(entries == env->nb_tlb);
237 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));
238
239 env->tlb_dirty = true;
240
241 cfg.array = (uintptr_t)env->tlb.tlbm;
242 cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
243 cfg.params = (uintptr_t)&params;
244 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
245
48add816 246 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg);
93dd5e85
SW		 247 if (ret < 0) {
248 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
249 __func__, strerror(-ret));
250 return ret;
251 }
252
253 env->kvm_sw_tlb = true;
254 return 0;
255}
256
4656e1f0
BH		 257
258#if defined(TARGET_PPC64)
ab256960 259static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp)
4656e1f0 260{
71d0f1ea 261 int ret;
a60f24b5 262
ab256960
GK		 263 assert(kvm_state != NULL);
264
265 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) {
71d0f1ea
GK		 266 error_setg(errp, "KVM doesn't expose the MMU features it supports");
267 error_append_hint(errp, "Consider switching to a newer KVM\n");
268 return;
4656e1f0 269 }
4656e1f0 270
ab256960 271 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info);
71d0f1ea
GK		 272 if (ret == 0) {
273 return;
4656e1f0
BH		 274 }
275
71d0f1ea
GK		 276 error_setg_errno(errp, -ret,
277 "KVM failed to provide the MMU features it supports");
4656e1f0
BH		 278}
279
c64abd1f
SB		 280struct ppc_radix_page_info *kvm_get_radix_page_info(void)
281{
282 KVMState *s = KVM_STATE(current_machine->accelerator);
283 struct ppc_radix_page_info *radix_page_info;
284 struct kvm_ppc_rmmu_info rmmu_info;
285 int i;
286
287 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) {
288 return NULL;
289 }
290 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) {
291 return NULL;
292 }
293 radix_page_info = g_malloc0(sizeof(*radix_page_info));
294 radix_page_info->count = 0;
295 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
296 if (rmmu_info.ap_encodings[i]) {
297 radix_page_info->entries[i] = rmmu_info.ap_encodings[i];
298 radix_page_info->count++;
299 }
300 }
301 return radix_page_info;
302}
303
b4db5413
SJS		 304target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
305 bool radix, bool gtse,
306 uint64_t proc_tbl)
307{
308 CPUState *cs = CPU(cpu);
309 int ret;
310 uint64_t flags = 0;
311 struct kvm_ppc_mmuv3_cfg cfg = {
312 .process_table = proc_tbl,
313 };
314
315 if (radix) {
316 flags |= KVM_PPC_MMUV3_RADIX;
317 }
318 if (gtse) {
319 flags |= KVM_PPC_MMUV3_GTSE;
320 }
321 cfg.flags = flags;
322 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg);
323 switch (ret) {
324 case 0:
325 return H_SUCCESS;
326 case -EINVAL:
327 return H_PARAMETER;
328 case -ENODEV:
329 return H_NOT_AVAILABLE;
330 default:
331 return H_HARDWARE;
332 }
333}
334
24c6863c
DG		 335bool kvmppc_hpt_needs_host_contiguous_pages(void)
336{
24c6863c
DG		 337 static struct kvm_ppc_smmu_info smmu_info;
338
339 if (!kvm_enabled()) {
340 return false;
341 }
342
ab256960 343 kvm_get_smmu_info(&smmu_info, &error_fatal);
24c6863c
DG		 344 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL);
345}
346
e5ca28ec 347void kvm_check_mmu(PowerPCCPU *cpu, Error **errp)
4656e1f0 348{
e5ca28ec 349 struct kvm_ppc_smmu_info smmu_info;
4656e1f0 350 int iq, ik, jq, jk;
71d0f1ea 351 Error *local_err = NULL;
4656e1f0 352
e5ca28ec
DG		 353 /* For now, we only have anything to check on hash64 MMUs */
354 if (!cpu->hash64_opts || !kvm_enabled()) {
4656e1f0
BH		 355 return;
356 }
357
ab256960 358 kvm_get_smmu_info(&smmu_info, &local_err);
71d0f1ea
GK		 359 if (local_err) {
360 error_propagate(errp, local_err);
361 return;
362 }
4656e1f0 363
e5ca28ec
DG		 364 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)
365 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
366 error_setg(errp,
367 "KVM does not support 1TiB segments which guest expects");
368 return;
df587133 369 }
4656e1f0 370
e5ca28ec
DG		 371 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) {
372 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u",
373 smmu_info.slb_size, cpu->hash64_opts->slb_size);
374 return;
90da0d5a
BH		 375 }
376
08215d8f 377 /*
e5ca28ec
DG		 378 * Verify that every pagesize supported by the cpu model is
379 * supported by KVM with the same encodings
08215d8f 380 */
e5ca28ec 381 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) {
b07c59f7 382 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq];
e5ca28ec 383 struct kvm_ppc_one_seg_page_size *ksps;
4656e1f0 384
e5ca28ec
DG		 385 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) {
386 if (qsps->page_shift == smmu_info.sps[ik].page_shift) {
4656e1f0
BH		 387 break;
388 }
389 }
e5ca28ec
DG		 390 if (ik >= ARRAY_SIZE(smmu_info.sps)) {
391 error_setg(errp, "KVM doesn't support for base page shift %u",
392 qsps->page_shift);
393 return;
394 }
395
396 ksps = &smmu_info.sps[ik];
397 if (ksps->slb_enc != qsps->slb_enc) {
398 error_setg(errp,
399"KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
400 ksps->slb_enc, ksps->page_shift, qsps->slb_enc);
401 return;
402 }
403
404 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) {
405 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) {
406 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) {
407 break;
408 }
409 }
410
411 if (jk >= ARRAY_SIZE(ksps->enc)) {
412 error_setg(errp, "KVM doesn't support page shift %u/%u",
413 qsps->enc[jq].page_shift, qsps->page_shift);
414 return;
415 }
416 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) {
417 error_setg(errp,
418"KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
419 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift,
420 qsps->page_shift, qsps->enc[jq].pte_enc);
421 return;
422 }
4656e1f0
BH		 423 }
424 }
4656e1f0 425
e5ca28ec 426 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
c995e942
DG		 427 /*
428 * Mostly what guest pagesizes we can use are related to the
e5ca28ec
DG		 429 * host pages used to map guest RAM, which is handled in the
430 * platform code. Cache-Inhibited largepages (64k) however are
431 * used for I/O, so if they're mapped to the host at all it
432 * will be a normal mapping, not a special hugepage one used
c995e942
DG		 433 * for RAM.
434 */
e5ca28ec
DG		 435 if (getpagesize() < 0x10000) {
436 error_setg(errp,
437 "KVM can't supply 64kiB CI pages, which guest expects");
438 }
439 }
4656e1f0 440}
4656e1f0
BH		 441#endif /* !defined (TARGET_PPC64) */
442
b164e48e
EH		 443unsigned long kvm_arch_vcpu_id(CPUState *cpu)
444{
2e886fb3 445 return POWERPC_CPU(cpu)->vcpu_id;
b164e48e
EH		 446}
447
c995e942
DG		 448/*
449 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports
450 * only 1 watchpoint, so array size of 4 is sufficient for now.
88365d17
BB		 451 */
452#define MAX_HW_BKPTS 4
453
454static struct HWBreakpoint {
455 target_ulong addr;
456 int type;
457} hw_debug_points[MAX_HW_BKPTS];
458
459static CPUWatchpoint hw_watchpoint;
460
461/* Default there is no breakpoint and watchpoint supported */
462static int max_hw_breakpoint;
463static int max_hw_watchpoint;
464static int nb_hw_breakpoint;
465static int nb_hw_watchpoint;
466
467static void kvmppc_hw_debug_points_init(CPUPPCState *cenv)
468{
469 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
470 max_hw_breakpoint = 2;
471 max_hw_watchpoint = 2;
472 }
473
474 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) {
475 fprintf(stderr, "Error initializing h/w breakpoints\n");
476 return;
477 }
478}
479
20d695a9 480int kvm_arch_init_vcpu(CPUState *cs)
5666ca4a 481{
20d695a9
AF		 482 PowerPCCPU *cpu = POWERPC_CPU(cs);
483 CPUPPCState *cenv = &cpu->env;
5666ca4a
SW		 484 int ret;
485
4656e1f0 486 /* Synchronize sregs with kvm */
1bc22652 487 ret = kvm_arch_sync_sregs(cpu);
5666ca4a 488 if (ret) {
388e47c7
TH		 489 if (ret == -EINVAL) {
490 error_report("Register sync failed... If you're using kvm-hv.ko,"
491 " only \"-cpu host\" is possible");
492 }
5666ca4a
SW		 493 return ret;
494 }
861bbc80 495
bc72ad67 496 idle_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, kvm_kick_cpu, cpu);
c821c2bd 497
93dd5e85
SW		 498 switch (cenv->mmu_model) {
499 case POWERPC_MMU_BOOKE206:
7f516c96 500 /* This target supports access to KVM's guest TLB */
1bc22652 501 ret = kvm_booke206_tlb_init(cpu);
93dd5e85 502 break;
7f516c96
TH		 503 case POWERPC_MMU_2_07:
504 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) {
c995e942
DG		 505 /*
506 * KVM-HV has transactional memory on POWER8 also without
507 * the KVM_CAP_PPC_HTM extension, so enable it here
508 * instead as long as it's availble to userspace on the
509 * host.
510 */
f3d9f303
SB		 511 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
512 cap_htm = true;
513 }
7f516c96
TH		 514 }
515 break;
93dd5e85
SW		 516 default:
517 break;
518 }
519
3c902d44 520 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode);
88365d17 521 kvmppc_hw_debug_points_init(cenv);
3c902d44 522
861bbc80 523 return ret;
d76d1650
AJ		 524}
525
b1115c99
LA		 526int kvm_arch_destroy_vcpu(CPUState *cs)
527{
528 return 0;
529}
530
1bc22652 531static void kvm_sw_tlb_put(PowerPCCPU *cpu)
93dd5e85 532{
1bc22652
AF		 533 CPUPPCState *env = &cpu->env;
534 CPUState *cs = CPU(cpu);
93dd5e85
SW		 535 struct kvm_dirty_tlb dirty_tlb;
536 unsigned char *bitmap;
537 int ret;
538
539 if (!env->kvm_sw_tlb) {
540 return;
541 }
542
543 bitmap = g_malloc((env->nb_tlb + 7) / 8);
544 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
545
546 dirty_tlb.bitmap = (uintptr_t)bitmap;
547 dirty_tlb.num_dirty = env->nb_tlb;
548
1bc22652 549 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb);
93dd5e85
SW		 550 if (ret) {
551 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
552 __func__, strerror(-ret));
553 }
554
555 g_free(bitmap);
556}
557
d67d40ea
DG		 558static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
559{
560 PowerPCCPU *cpu = POWERPC_CPU(cs);
561 CPUPPCState *env = &cpu->env;
562 union {
563 uint32_t u32;
564 uint64_t u64;
565 } val;
566 struct kvm_one_reg reg = {
567 .id = id,
568 .addr = (uintptr_t) &val,
569 };
570 int ret;
571
572 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
573 if (ret != 0) {
b36f100e 574 trace_kvm_failed_spr_get(spr, strerror(errno));
d67d40ea
DG		 575 } else {
576 switch (id & KVM_REG_SIZE_MASK) {
577 case KVM_REG_SIZE_U32:
578 env->spr[spr] = val.u32;
579 break;
580
581 case KVM_REG_SIZE_U64:
582 env->spr[spr] = val.u64;
583 break;
584
585 default:
586 /* Don't handle this size yet */
587 abort();
588 }
589 }
590}
591
592static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
593{
594 PowerPCCPU *cpu = POWERPC_CPU(cs);
595 CPUPPCState *env = &cpu->env;
596 union {
597 uint32_t u32;
598 uint64_t u64;
599 } val;
600 struct kvm_one_reg reg = {
601 .id = id,
602 .addr = (uintptr_t) &val,
603 };
604 int ret;
605
606 switch (id & KVM_REG_SIZE_MASK) {
607 case KVM_REG_SIZE_U32:
608 val.u32 = env->spr[spr];
609 break;
610
611 case KVM_REG_SIZE_U64:
612 val.u64 = env->spr[spr];
613 break;
614
615 default:
616 /* Don't handle this size yet */
617 abort();
618 }
619
620 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
621 if (ret != 0) {
b36f100e 622 trace_kvm_failed_spr_set(spr, strerror(errno));
d67d40ea
DG		 623 }
624}
625
70b79849
DG		 626static int kvm_put_fp(CPUState *cs)
627{
628 PowerPCCPU *cpu = POWERPC_CPU(cs);
629 CPUPPCState *env = &cpu->env;
630 struct kvm_one_reg reg;
631 int i;
632 int ret;
633
634 if (env->insns_flags & PPC_FLOAT) {
635 uint64_t fpscr = env->fpscr;
636 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
637
638 reg.id = KVM_REG_PPC_FPSCR;
639 reg.addr = (uintptr_t)&fpscr;
640 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
641 if (ret < 0) {
8d83cbf1 642 trace_kvm_failed_fpscr_set(strerror(errno));
70b79849
DG		 643 return ret;
644 }
645
646 for (i = 0; i < 32; i++) {
647 uint64_t vsr[2];
ef96e3ae
MCA		 648 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
649 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
70b79849 650
3a4b791b 651#ifdef HOST_WORDS_BIGENDIAN
ef96e3ae
MCA		 652 vsr[0] = float64_val(*fpr);
653 vsr[1] = *vsrl;
3a4b791b 654#else
ef96e3ae
MCA		 655 vsr[0] = *vsrl;
656 vsr[1] = float64_val(*fpr);
3a4b791b 657#endif
70b79849
DG		 658 reg.addr = (uintptr_t) &vsr;
659 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
660
661 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
662 if (ret < 0) {
8d83cbf1
GK		 663 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i,
664 strerror(errno));
70b79849
DG		 665 return ret;
666 }
667 }
668 }
669
670 if (env->insns_flags & PPC_ALTIVEC) {
671 reg.id = KVM_REG_PPC_VSCR;
672 reg.addr = (uintptr_t)&env->vscr;
673 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
674 if (ret < 0) {
8d83cbf1 675 trace_kvm_failed_vscr_set(strerror(errno));
70b79849
DG		 676 return ret;
677 }
678
679 for (i = 0; i < 32; i++) {
680 reg.id = KVM_REG_PPC_VR(i);
ef96e3ae 681 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
70b79849
DG		 682 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
683 if (ret < 0) {
8d83cbf1 684 trace_kvm_failed_vr_set(i, strerror(errno));
70b79849
DG		 685 return ret;
686 }
687 }
688 }
689
690 return 0;
691}
692
693static int kvm_get_fp(CPUState *cs)
694{
695 PowerPCCPU *cpu = POWERPC_CPU(cs);
696 CPUPPCState *env = &cpu->env;
697 struct kvm_one_reg reg;
698 int i;
699 int ret;
700
701 if (env->insns_flags & PPC_FLOAT) {
702 uint64_t fpscr;
703 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
704
705 reg.id = KVM_REG_PPC_FPSCR;
706 reg.addr = (uintptr_t)&fpscr;
707 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
708 if (ret < 0) {
8d83cbf1 709 trace_kvm_failed_fpscr_get(strerror(errno));
70b79849
DG		 710 return ret;
711 } else {
712 env->fpscr = fpscr;
713 }
714
715 for (i = 0; i < 32; i++) {
716 uint64_t vsr[2];
ef96e3ae
MCA		 717 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
718 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
70b79849
DG		 719
720 reg.addr = (uintptr_t) &vsr;
721 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
722
723 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
724 if (ret < 0) {
8d83cbf1
GK		 725 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i,
726 strerror(errno));
70b79849
DG		 727 return ret;
728 } else {
3a4b791b 729#ifdef HOST_WORDS_BIGENDIAN
ef96e3ae 730 *fpr = vsr[0];
70b79849 731 if (vsx) {
ef96e3ae 732 *vsrl = vsr[1];
70b79849 733 }
3a4b791b 734#else
ef96e3ae 735 *fpr = vsr[1];
3a4b791b 736 if (vsx) {
ef96e3ae 737 *vsrl = vsr[0];
3a4b791b
GK		 738 }
739#endif
70b79849
DG		 740 }
741 }
742 }
743
744 if (env->insns_flags & PPC_ALTIVEC) {
745 reg.id = KVM_REG_PPC_VSCR;
746 reg.addr = (uintptr_t)&env->vscr;
747 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
748 if (ret < 0) {
8d83cbf1 749 trace_kvm_failed_vscr_get(strerror(errno));
70b79849
DG		 750 return ret;
751 }
752
753 for (i = 0; i < 32; i++) {
754 reg.id = KVM_REG_PPC_VR(i);
ef96e3ae 755 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
70b79849
DG		 756 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
757 if (ret < 0) {
8d83cbf1 758 trace_kvm_failed_vr_get(i, strerror(errno));
70b79849
DG		 759 return ret;
760 }
761 }
762 }
763
764 return 0;
765}
766
9b00ea49
DG		 767#if defined(TARGET_PPC64)
768static int kvm_get_vpa(CPUState *cs)
769{
770 PowerPCCPU *cpu = POWERPC_CPU(cs);
ce2918cb 771 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
9b00ea49
DG		 772 struct kvm_one_reg reg;
773 int ret;
774
775 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 776 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 777 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
778 if (ret < 0) {
8d83cbf1 779 trace_kvm_failed_vpa_addr_get(strerror(errno));
9b00ea49
DG		 780 return ret;
781 }
782
7388efaf
DG		 783 assert((uintptr_t)&spapr_cpu->slb_shadow_size
784 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
9b00ea49 785 reg.id = KVM_REG_PPC_VPA_SLB;
7388efaf 786 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
9b00ea49
DG		 787 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
788 if (ret < 0) {
8d83cbf1 789 trace_kvm_failed_slb_get(strerror(errno));
9b00ea49
DG		 790 return ret;
791 }
792
7388efaf
DG		 793 assert((uintptr_t)&spapr_cpu->dtl_size
794 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
9b00ea49 795 reg.id = KVM_REG_PPC_VPA_DTL;
7388efaf 796 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
9b00ea49
DG		 797 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
798 if (ret < 0) {
8d83cbf1 799 trace_kvm_failed_dtl_get(strerror(errno));
9b00ea49
DG		 800 return ret;
801 }
802
803 return 0;
804}
805
806static int kvm_put_vpa(CPUState *cs)
807{
808 PowerPCCPU *cpu = POWERPC_CPU(cs);
ce2918cb 809 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
9b00ea49
DG		 810 struct kvm_one_reg reg;
811 int ret;
812
c995e942
DG		 813 /*
814 * SLB shadow or DTL can't be registered unless a master VPA is
9b00ea49
DG		 815 * registered. That means when restoring state, if a VPA *is*
816 * registered, we need to set that up first. If not, we need to
c995e942
DG		 817 * deregister the others before deregistering the master VPA
818 */
7388efaf
DG		 819 assert(spapr_cpu->vpa_addr
820 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr));
9b00ea49 821
7388efaf 822 if (spapr_cpu->vpa_addr) {
9b00ea49 823 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 824 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 825 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
826 if (ret < 0) {
8d83cbf1 827 trace_kvm_failed_vpa_addr_set(strerror(errno));
9b00ea49
DG		 828 return ret;
829 }
830 }
831
7388efaf
DG		 832 assert((uintptr_t)&spapr_cpu->slb_shadow_size
833 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
9b00ea49 834 reg.id = KVM_REG_PPC_VPA_SLB;
7388efaf 835 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
9b00ea49
DG		 836 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
837 if (ret < 0) {
8d83cbf1 838 trace_kvm_failed_slb_set(strerror(errno));
9b00ea49
DG		 839 return ret;
840 }
841
7388efaf
DG		 842 assert((uintptr_t)&spapr_cpu->dtl_size
843 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
9b00ea49 844 reg.id = KVM_REG_PPC_VPA_DTL;
7388efaf 845 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
9b00ea49
DG		 846 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
847 if (ret < 0) {
8d83cbf1 848 trace_kvm_failed_dtl_set(strerror(errno));
9b00ea49
DG		 849 return ret;
850 }
851
7388efaf 852 if (!spapr_cpu->vpa_addr) {
9b00ea49 853 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 854 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 855 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
856 if (ret < 0) {
8d83cbf1 857 trace_kvm_failed_null_vpa_addr_set(strerror(errno));
9b00ea49
DG		 858 return ret;
859 }
860 }
861
862 return 0;
863}
864#endif /* TARGET_PPC64 */
865
e5c0d3ce 866int kvmppc_put_books_sregs(PowerPCCPU *cpu)
a7a00a72
DG		 867{
868 CPUPPCState *env = &cpu->env;
869 struct kvm_sregs sregs;
870 int i;
871
872 sregs.pvr = env->spr[SPR_PVR];
873
1ec26c75
GK		 874 if (cpu->vhyp) {
875 PPCVirtualHypervisorClass *vhc =
876 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
877 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp);
878 } else {
879 sregs.u.s.sdr1 = env->spr[SPR_SDR1];
880 }
a7a00a72
DG		 881
882 /* Sync SLB */
883#ifdef TARGET_PPC64
884 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
885 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid;
886 if (env->slb[i].esid & SLB_ESID_V) {
887 sregs.u.s.ppc64.slb[i].slbe |= i;
888 }
889 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid;
890 }
891#endif
892
893 /* Sync SRs */
894 for (i = 0; i < 16; i++) {
895 sregs.u.s.ppc32.sr[i] = env->sr[i];
896 }
897
898 /* Sync BATs */
899 for (i = 0; i < 8; i++) {
900 /* Beware. We have to swap upper and lower bits here */
901 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32)
902 | env->DBAT[1][i];
903 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32)
904 | env->IBAT[1][i];
905 }
906
907 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
908}
909
20d695a9 910int kvm_arch_put_registers(CPUState *cs, int level)
d76d1650 911{
20d695a9
AF		 912 PowerPCCPU *cpu = POWERPC_CPU(cs);
913 CPUPPCState *env = &cpu->env;
d76d1650
AJ		 914 struct kvm_regs regs;
915 int ret;
916 int i;
917
1bc22652
AF		 918 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
919 if (ret < 0) {
d76d1650 920 return ret;
1bc22652 921 }
d76d1650
AJ		 922
923 regs.ctr = env->ctr;
924 regs.lr = env->lr;
da91a00f 925 regs.xer = cpu_read_xer(env);
d76d1650
AJ		 926 regs.msr = env->msr;
927 regs.pc = env->nip;
928
929 regs.srr0 = env->spr[SPR_SRR0];
930 regs.srr1 = env->spr[SPR_SRR1];
931
932 regs.sprg0 = env->spr[SPR_SPRG0];
933 regs.sprg1 = env->spr[SPR_SPRG1];
934 regs.sprg2 = env->spr[SPR_SPRG2];
935 regs.sprg3 = env->spr[SPR_SPRG3];
936 regs.sprg4 = env->spr[SPR_SPRG4];
937 regs.sprg5 = env->spr[SPR_SPRG5];
938 regs.sprg6 = env->spr[SPR_SPRG6];
939 regs.sprg7 = env->spr[SPR_SPRG7];
940
90dc8812
SW		 941 regs.pid = env->spr[SPR_BOOKE_PID];
942
c995e942 943 for (i = 0; i < 32; i++) {
d76d1650 944 regs.gpr[i] = env->gpr[i];
c995e942 945 }
d76d1650 946
4bddaf55
AK		 947 regs.cr = 0;
948 for (i = 0; i < 8; i++) {
949 regs.cr |= (env->crf[i] & 15) << (4 * (7 - i));
950 }
951
1bc22652 952 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
c995e942 953 if (ret < 0) {
d76d1650 954 return ret;
c995e942 955 }
d76d1650 956
70b79849
DG		 957 kvm_put_fp(cs);
958
93dd5e85 959 if (env->tlb_dirty) {
1bc22652 960 kvm_sw_tlb_put(cpu);
93dd5e85
SW		 961 env->tlb_dirty = false;
962 }
963
f1af19d7 964 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) {
a7a00a72
DG		 965 ret = kvmppc_put_books_sregs(cpu);
966 if (ret < 0) {
f1af19d7
DG		 967 return ret;
968 }
969 }
970
971 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {
d67d40ea
DG		 972 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
973 }
f1af19d7 974
d67d40ea
DG		 975 if (cap_one_reg) {
976 int i;
977
c995e942
DG		 978 /*
979 * We deliberately ignore errors here, for kernels which have
d67d40ea
DG		 980 * the ONE_REG calls, but don't support the specific
981 * registers, there's a reasonable chance things will still
c995e942
DG		 982 * work, at least until we try to migrate.
983 */
d67d40ea
DG		 984 for (i = 0; i < 1024; i++) {
985 uint64_t id = env->spr_cb[i].one_reg_id;
986
987 if (id != 0) {
988 kvm_put_one_spr(cs, id, i);
989 }
f1af19d7 990 }
9b00ea49
DG		 991
992#ifdef TARGET_PPC64
80b3f79b
AK		 993 if (msr_ts) {
994 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
995 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
996 }
997 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
998 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
999 }
1000 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
1001 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
1002 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
1003 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
1004 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1005 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1006 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1007 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1008 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1009 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1010 }
1011
9b00ea49
DG		 1012 if (cap_papr) {
1013 if (kvm_put_vpa(cs) < 0) {
8d83cbf1 1014 trace_kvm_failed_put_vpa();
9b00ea49
DG		 1015 }
1016 }
98a8b524
AK		 1017
1018 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
9b00ea49 1019#endif /* TARGET_PPC64 */
f1af19d7
DG		 1020 }
1021
d76d1650
AJ		 1022 return ret;
1023}
1024
c371c2e3
BB		 1025static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor)
1026{
1027 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR];
1028}
1029
a7a00a72
DG		 1030static int kvmppc_get_booke_sregs(PowerPCCPU *cpu)
1031{
1032 CPUPPCState *env = &cpu->env;
1033 struct kvm_sregs sregs;
1034 int ret;
1035
1036 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1037 if (ret < 0) {
1038 return ret;
1039 }
1040
1041 if (sregs.u.e.features & KVM_SREGS_E_BASE) {
1042 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
1043 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
1044 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
1045 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
1046 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
1047 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
1048 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
1049 env->spr[SPR_DECR] = sregs.u.e.dec;
1050 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
1051 env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
1052 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
1053 }
1054
1055 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
1056 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
1057 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
1058 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
1059 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
1060 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
1061 }
1062
1063 if (sregs.u.e.features & KVM_SREGS_E_64) {
1064 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
1065 }
1066
1067 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
1068 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
1069 }
1070
1071 if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
1072 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
1073 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0);
1074 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
1075 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1);
1076 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
1077 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2);
1078 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
1079 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3);
1080 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
1081 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4);
1082 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
1083 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5);
1084 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
1085 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6);
1086 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
1087 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7);
1088 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
1089 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8);
1090 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
1091 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9);
1092 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
1093 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10);
1094 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
1095 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11);
1096 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
1097 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12);
1098 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
1099 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13);
1100 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
1101 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14);
1102 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
1103 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15);
1104
1105 if (sregs.u.e.features & KVM_SREGS_E_SPE) {
1106 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
1107 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32);
1108 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
1109 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33);
1110 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
1111 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34);
1112 }
1113
1114 if (sregs.u.e.features & KVM_SREGS_E_PM) {
1115 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
1116 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35);
1117 }
1118
1119 if (sregs.u.e.features & KVM_SREGS_E_PC) {
1120 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
1121 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36);
1122 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
1123 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37);
1124 }
1125 }
1126
1127 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
1128 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
1129 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
1130 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
1131 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
1132 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
1133 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
1134 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
1135 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
1136 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
1137 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
1138 }
1139
1140 if (sregs.u.e.features & KVM_SREGS_EXP) {
1141 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
1142 }
1143
1144 if (sregs.u.e.features & KVM_SREGS_E_PD) {
1145 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
1146 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
1147 }
1148
1149 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
1150 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
1151 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
1152 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;
1153
1154 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
1155 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
1156 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
1157 }
1158 }
1159
1160 return 0;
1161}
1162
1163static int kvmppc_get_books_sregs(PowerPCCPU *cpu)
1164{
1165 CPUPPCState *env = &cpu->env;
1166 struct kvm_sregs sregs;
1167 int ret;
1168 int i;
1169
1170 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1171 if (ret < 0) {
1172 return ret;
1173 }
1174
e57ca75c 1175 if (!cpu->vhyp) {
a7a00a72
DG		 1176 ppc_store_sdr1(env, sregs.u.s.sdr1);
1177 }
1178
1179 /* Sync SLB */
1180#ifdef TARGET_PPC64
1181 /*
1182 * The packed SLB array we get from KVM_GET_SREGS only contains
1183 * information about valid entries. So we flush our internal copy
1184 * to get rid of stale ones, then put all valid SLB entries back
1185 * in.
1186 */
1187 memset(env->slb, 0, sizeof(env->slb));
1188 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
1189 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe;
1190 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv;
1191 /*
1192 * Only restore valid entries
1193 */
1194 if (rb & SLB_ESID_V) {
1195 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs);
1196 }
1197 }
1198#endif
1199
1200 /* Sync SRs */
1201 for (i = 0; i < 16; i++) {
1202 env->sr[i] = sregs.u.s.ppc32.sr[i];
1203 }
1204
1205 /* Sync BATs */
1206 for (i = 0; i < 8; i++) {
1207 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
1208 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
1209 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
1210 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
1211 }
1212
1213 return 0;
1214}
1215
20d695a9 1216int kvm_arch_get_registers(CPUState *cs)
d76d1650 1217{
20d695a9
AF		 1218 PowerPCCPU *cpu = POWERPC_CPU(cs);
1219 CPUPPCState *env = &cpu->env;
d76d1650 1220 struct kvm_regs regs;
90dc8812 1221 uint32_t cr;
138b38b6 1222 int i, ret;
d76d1650 1223
1bc22652 1224 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
c995e942 1225 if (ret < 0) {
d76d1650 1226 return ret;
c995e942 1227 }
d76d1650 1228
90dc8812
SW		 1229 cr = regs.cr;
1230 for (i = 7; i >= 0; i--) {
1231 env->crf[i] = cr & 15;
1232 cr >>= 4;
1233 }
ba5e5090 1234
d76d1650
AJ		 1235 env->ctr = regs.ctr;
1236 env->lr = regs.lr;
da91a00f 1237 cpu_write_xer(env, regs.xer);
d76d1650
AJ		 1238 env->msr = regs.msr;
1239 env->nip = regs.pc;
1240
1241 env->spr[SPR_SRR0] = regs.srr0;
1242 env->spr[SPR_SRR1] = regs.srr1;
1243
1244 env->spr[SPR_SPRG0] = regs.sprg0;
1245 env->spr[SPR_SPRG1] = regs.sprg1;
1246 env->spr[SPR_SPRG2] = regs.sprg2;
1247 env->spr[SPR_SPRG3] = regs.sprg3;
1248 env->spr[SPR_SPRG4] = regs.sprg4;
1249 env->spr[SPR_SPRG5] = regs.sprg5;
1250 env->spr[SPR_SPRG6] = regs.sprg6;
1251 env->spr[SPR_SPRG7] = regs.sprg7;
1252
90dc8812
SW		 1253 env->spr[SPR_BOOKE_PID] = regs.pid;
1254
c995e942 1255 for (i = 0; i < 32; i++) {
d76d1650 1256 env->gpr[i] = regs.gpr[i];
c995e942 1257 }
d76d1650 1258
70b79849
DG		 1259 kvm_get_fp(cs);
1260
90dc8812 1261 if (cap_booke_sregs) {
a7a00a72 1262 ret = kvmppc_get_booke_sregs(cpu);
90dc8812
SW		 1263 if (ret < 0) {
1264 return ret;
1265 }
fafc0b6a 1266 }
90dc8812 1267
90dc8812 1268 if (cap_segstate) {
a7a00a72 1269 ret = kvmppc_get_books_sregs(cpu);
90dc8812
SW		 1270 if (ret < 0) {
1271 return ret;
1272 }
fafc0b6a 1273 }
ba5e5090 1274
d67d40ea
DG		 1275 if (cap_hior) {
1276 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
1277 }
1278
1279 if (cap_one_reg) {
1280 int i;
1281
c995e942
DG		 1282 /*
1283 * We deliberately ignore errors here, for kernels which have
d67d40ea
DG		 1284 * the ONE_REG calls, but don't support the specific
1285 * registers, there's a reasonable chance things will still
c995e942
DG		 1286 * work, at least until we try to migrate.
1287 */
d67d40ea
DG		 1288 for (i = 0; i < 1024; i++) {
1289 uint64_t id = env->spr_cb[i].one_reg_id;
1290
1291 if (id != 0) {
1292 kvm_get_one_spr(cs, id, i);
1293 }
1294 }
9b00ea49
DG		 1295
1296#ifdef TARGET_PPC64
80b3f79b
AK		 1297 if (msr_ts) {
1298 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
1299 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
1300 }
1301 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
1302 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
1303 }
1304 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
1305 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
1306 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
1307 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
1308 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1309 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1310 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1311 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1312 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1313 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1314 }
1315
9b00ea49
DG		 1316 if (cap_papr) {
1317 if (kvm_get_vpa(cs) < 0) {
8d83cbf1 1318 trace_kvm_failed_get_vpa();
9b00ea49
DG		 1319 }
1320 }
98a8b524
AK		 1321
1322 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
9b00ea49 1323#endif
d67d40ea
DG		 1324 }
1325
d76d1650
AJ		 1326 return 0;
1327}
1328
1bc22652 1329int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
fc87e185
AG		 1330{
1331 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
1332
1333 if (irq != PPC_INTERRUPT_EXT) {
1334 return 0;
1335 }
1336
1337 if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) {
1338 return 0;
1339 }
1340
1bc22652 1341 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
fc87e185
AG		 1342
1343 return 0;
1344}
1345
a69dc537 1346#if defined(TARGET_PPC64)
16415335
AG		 1347#define PPC_INPUT_INT PPC970_INPUT_INT
1348#else
1349#define PPC_INPUT_INT PPC6xx_INPUT_INT
1350#endif
1351
20d695a9 1352void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
d76d1650 1353{
20d695a9
AF		 1354 PowerPCCPU *cpu = POWERPC_CPU(cs);
1355 CPUPPCState *env = &cpu->env;
d76d1650
AJ		 1356 int r;
1357 unsigned irq;
1358
4b8523ee
JK		 1359 qemu_mutex_lock_iothread();
1360
c995e942
DG		 1361 /*
1362 * PowerPC QEMU tracks the various core input pins (interrupt,
1363 * critical interrupt, reset, etc) in PPC-specific
1364 * env->irq_input_state.
1365 */
fc87e185
AG		 1366 if (!cap_interrupt_level &&
1367 run->ready_for_interrupt_injection &&
259186a7 1368 (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
c995e942 1369 (env->irq_input_state & (1 << PPC_INPUT_INT)))
d76d1650 1370 {
c995e942
DG		 1371 /*
1372 * For now KVM disregards the 'irq' argument. However, in the
1373 * future KVM could cache it in-kernel to avoid a heavyweight
1374 * exit when reading the UIC.
d76d1650 1375 */
fc87e185 1376 irq = KVM_INTERRUPT_SET;
d76d1650 1377
8d83cbf1 1378 trace_kvm_injected_interrupt(irq);
1bc22652 1379 r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &irq);
55e5c285
AF		 1380 if (r < 0) {
1381 printf("cpu %d fail inject %x\n", cs->cpu_index, irq);
1382 }
c821c2bd
AG		 1383
1384 /* Always wake up soon in case the interrupt was level based */
bc72ad67 1385 timer_mod(idle_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
73bcb24d 1386 (NANOSECONDS_PER_SECOND / 50));
d76d1650
AJ		 1387 }
1388
c995e942
DG		 1389 /*
1390 * We don't know if there are more interrupts pending after
1391 * this. However, the guest will return to userspace in the course
1392 * of handling this one anyways, so we will get a chance to
1393 * deliver the rest.
1394 */
4b8523ee
JK		 1395
1396 qemu_mutex_unlock_iothread();
d76d1650
AJ		 1397}
1398
4c663752 1399MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
d76d1650 1400{
4c663752 1401 return MEMTXATTRS_UNSPECIFIED;
d76d1650
AJ		 1402}
1403
20d695a9 1404int kvm_arch_process_async_events(CPUState *cs)
0af691d7 1405{
259186a7 1406 return cs->halted;
0af691d7
MT		 1407}
1408
259186a7 1409static int kvmppc_handle_halt(PowerPCCPU *cpu)
d76d1650 1410{
259186a7
AF		 1411 CPUState *cs = CPU(cpu);
1412 CPUPPCState *env = &cpu->env;
1413
1414 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
1415 cs->halted = 1;
27103424 1416 cs->exception_index = EXCP_HLT;
d76d1650
AJ		 1417 }
1418
bb4ea393 1419 return 0;
d76d1650
AJ		 1420}
1421
1422/* map dcr access to existing qemu dcr emulation */
c995e942
DG		 1423static int kvmppc_handle_dcr_read(CPUPPCState *env,
1424 uint32_t dcrn, uint32_t *data)
d76d1650 1425{
c995e942 1426 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) {
d76d1650 1427 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
c995e942 1428 }
d76d1650 1429
bb4ea393 1430 return 0;
d76d1650
AJ		 1431}
1432
c995e942
DG		 1433static int kvmppc_handle_dcr_write(CPUPPCState *env,
1434 uint32_t dcrn, uint32_t data)
d76d1650 1435{
c995e942 1436 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) {
d76d1650 1437 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
c995e942 1438 }
d76d1650 1439
bb4ea393 1440 return 0;
d76d1650
AJ		 1441}
1442
8a0548f9
BB		 1443int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1444{
1445 /* Mixed endian case is not handled */
1446 uint32_t sc = debug_inst_opcode;
1447
1448 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1449 sizeof(sc), 0) ||
1450 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) {
1451 return -EINVAL;
1452 }
1453
1454 return 0;
1455}
1456
1457int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1458{
1459 uint32_t sc;
1460
1461 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) ||
1462 sc != debug_inst_opcode ||
1463 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1464 sizeof(sc), 1)) {
1465 return -EINVAL;
1466 }
1467
1468 return 0;
1469}
1470
88365d17
BB		 1471static int find_hw_breakpoint(target_ulong addr, int type)
1472{
1473 int n;
1474
1475 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1476 <= ARRAY_SIZE(hw_debug_points));
1477
1478 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1479 if (hw_debug_points[n].addr == addr &&
1480 hw_debug_points[n].type == type) {
1481 return n;
1482 }
1483 }
1484
1485 return -1;
1486}
1487
1488static int find_hw_watchpoint(target_ulong addr, int *flag)
1489{
1490 int n;
1491
1492 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS);
1493 if (n >= 0) {
1494 *flag = BP_MEM_ACCESS;
1495 return n;
1496 }
1497
1498 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE);
1499 if (n >= 0) {
1500 *flag = BP_MEM_WRITE;
1501 return n;
1502 }
1503
1504 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ);
1505 if (n >= 0) {
1506 *flag = BP_MEM_READ;
1507 return n;
1508 }
1509
1510 return -1;
1511}
1512
1513int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1514 target_ulong len, int type)
1515{
1516 if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) {
1517 return -ENOBUFS;
1518 }
1519
1520 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr;
1521 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type;
1522
1523 switch (type) {
1524 case GDB_BREAKPOINT_HW:
1525 if (nb_hw_breakpoint >= max_hw_breakpoint) {
1526 return -ENOBUFS;
1527 }
1528
1529 if (find_hw_breakpoint(addr, type) >= 0) {
1530 return -EEXIST;
1531 }
1532
1533 nb_hw_breakpoint++;
1534 break;
1535
1536 case GDB_WATCHPOINT_WRITE:
1537 case GDB_WATCHPOINT_READ:
1538 case GDB_WATCHPOINT_ACCESS:
1539 if (nb_hw_watchpoint >= max_hw_watchpoint) {
1540 return -ENOBUFS;
1541 }
1542
1543 if (find_hw_breakpoint(addr, type) >= 0) {
1544 return -EEXIST;
1545 }
1546
1547 nb_hw_watchpoint++;
1548 break;
1549
1550 default:
1551 return -ENOSYS;
1552 }
1553
1554 return 0;
1555}
1556
1557int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1558 target_ulong len, int type)
1559{
1560 int n;
1561
1562 n = find_hw_breakpoint(addr, type);
1563 if (n < 0) {
1564 return -ENOENT;
1565 }
1566
1567 switch (type) {
1568 case GDB_BREAKPOINT_HW:
1569 nb_hw_breakpoint--;
1570 break;
1571
1572 case GDB_WATCHPOINT_WRITE:
1573 case GDB_WATCHPOINT_READ:
1574 case GDB_WATCHPOINT_ACCESS:
1575 nb_hw_watchpoint--;
1576 break;
1577
1578 default:
1579 return -ENOSYS;
1580 }
1581 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint];
1582
1583 return 0;
1584}
1585
1586void kvm_arch_remove_all_hw_breakpoints(void)
1587{
1588 nb_hw_breakpoint = nb_hw_watchpoint = 0;
1589}
1590
8a0548f9
BB		 1591void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
1592{
88365d17
BB		 1593 int n;
1594
8a0548f9
BB		 1595 /* Software Breakpoint updates */
1596 if (kvm_sw_breakpoints_active(cs)) {
1597 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1598 }
88365d17
BB		 1599
1600 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1601 <= ARRAY_SIZE(hw_debug_points));
1602 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp));
1603
1604 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1605 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1606 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp));
1607 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1608 switch (hw_debug_points[n].type) {
1609 case GDB_BREAKPOINT_HW:
1610 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT;
1611 break;
1612 case GDB_WATCHPOINT_WRITE:
1613 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE;
1614 break;
1615 case GDB_WATCHPOINT_READ:
1616 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ;
1617 break;
1618 case GDB_WATCHPOINT_ACCESS:
1619 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE |
1620 KVMPPC_DEBUG_WATCH_READ;
1621 break;
1622 default:
1623 cpu_abort(cs, "Unsupported breakpoint type\n");
1624 }
1625 dbg->arch.bp[n].addr = hw_debug_points[n].addr;
1626 }
1627 }
8a0548f9
BB		 1628}
1629
2cbd1581
FR		 1630static int kvm_handle_hw_breakpoint(CPUState *cs,
1631 struct kvm_debug_exit_arch *arch_info)
1632{
1633 int handle = 0;
1634 int n;
1635 int flag = 0;
1636
1637 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1638 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) {
1639 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW);
1640 if (n >= 0) {
1641 handle = 1;
1642 }
1643 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ |
1644 KVMPPC_DEBUG_WATCH_WRITE)) {
1645 n = find_hw_watchpoint(arch_info->address, &flag);
1646 if (n >= 0) {
1647 handle = 1;
1648 cs->watchpoint_hit = &hw_watchpoint;
1649 hw_watchpoint.vaddr = hw_debug_points[n].addr;
1650 hw_watchpoint.flags = flag;
1651 }
1652 }
1653 }
1654 return handle;
1655}
1656
468e3a1a
FR		 1657static int kvm_handle_singlestep(void)
1658{
1659 return 1;
1660}
1661
1662static int kvm_handle_sw_breakpoint(void)
1663{
1664 return 1;
1665}
1666
8a0548f9
BB		 1667static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run)
1668{
1669 CPUState *cs = CPU(cpu);
1670 CPUPPCState *env = &cpu->env;
1671 struct kvm_debug_exit_arch *arch_info = &run->debug.arch;
8a0548f9 1672
88365d17 1673 if (cs->singlestep_enabled) {
468e3a1a
FR		 1674 return kvm_handle_singlestep();
1675 }
8a0548f9 1676
468e3a1a
FR		 1677 if (arch_info->status) {
1678 return kvm_handle_hw_breakpoint(cs, arch_info);
8a0548f9
BB		 1679 }
1680
468e3a1a
FR		 1681 if (kvm_find_sw_breakpoint(cs, arch_info->address)) {
1682 return kvm_handle_sw_breakpoint();
1683 }
1684
1685 /*
1686 * QEMU is not able to handle debug exception, so inject
1687 * program exception to guest;
1688 * Yes program exception NOT debug exception !!
1689 * When QEMU is using debug resources then debug exception must
1690 * be always set. To achieve this we set MSR_DE and also set
1691 * MSRP_DEP so guest cannot change MSR_DE.
1692 * When emulating debug resource for guest we want guest
1693 * to control MSR_DE (enable/disable debug interrupt on need).
1694 * Supporting both configurations are NOT possible.
1695 * So the result is that we cannot share debug resources
1696 * between QEMU and Guest on BOOKE architecture.
1697 * In the current design QEMU gets the priority over guest,
1698 * this means that if QEMU is using debug resources then guest
1699 * cannot use them;
1700 * For software breakpoint QEMU uses a privileged instruction;
1701 * So there cannot be any reason that we are here for guest
1702 * set debug exception, only possibility is guest executed a
1703 * privileged / illegal instruction and that's why we are
1704 * injecting a program interrupt.
1705 */
1706 cpu_synchronize_state(cs);
1707 /*
1708 * env->nip is PC, so increment this by 4 to use
1709 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1710 */
1711 env->nip += 4;
1712 cs->exception_index = POWERPC_EXCP_PROGRAM;
1713 env->error_code = POWERPC_EXCP_INVAL;
1714 ppc_cpu_do_interrupt(cs);
1715
1716 return 0;
8a0548f9
BB		 1717}
1718
20d695a9 1719int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
d76d1650 1720{
20d695a9
AF		 1721 PowerPCCPU *cpu = POWERPC_CPU(cs);
1722 CPUPPCState *env = &cpu->env;
bb4ea393 1723 int ret;
d76d1650 1724
4b8523ee
JK		 1725 qemu_mutex_lock_iothread();
1726
d76d1650
AJ		 1727 switch (run->exit_reason) {
1728 case KVM_EXIT_DCR:
1729 if (run->dcr.is_write) {
8d83cbf1 1730 trace_kvm_handle_dcr_write();
d76d1650
AJ		 1731 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
1732 } else {
228152c2 1733 trace_kvm_handle_dcr_read();
d76d1650
AJ		 1734 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
1735 }
1736 break;
1737 case KVM_EXIT_HLT:
8d83cbf1 1738 trace_kvm_handle_halt();
259186a7 1739 ret = kvmppc_handle_halt(cpu);
d76d1650 1740 break;
c6304a4a 1741#if defined(TARGET_PPC64)
f61b4bed 1742 case KVM_EXIT_PAPR_HCALL:
8d83cbf1 1743 trace_kvm_handle_papr_hcall();
20d695a9 1744 run->papr_hcall.ret = spapr_hypercall(cpu,
aa100fa4 1745 run->papr_hcall.nr,
f61b4bed 1746 run->papr_hcall.args);
78e8fde2 1747 ret = 0;
f61b4bed
AG		 1748 break;
1749#endif
5b95b8b9 1750 case KVM_EXIT_EPR:
8d83cbf1 1751 trace_kvm_handle_epr();
933b19ea 1752 run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
5b95b8b9
AG		 1753 ret = 0;
1754 break;
31f2cb8f 1755 case KVM_EXIT_WATCHDOG:
8d83cbf1 1756 trace_kvm_handle_watchdog_expiry();
31f2cb8f
BB		 1757 watchdog_perform_action();
1758 ret = 0;
1759 break;
1760
8a0548f9 1761 case KVM_EXIT_DEBUG:
8d83cbf1 1762 trace_kvm_handle_debug_exception();
8a0548f9
BB		 1763 if (kvm_handle_debug(cpu, run)) {
1764 ret = EXCP_DEBUG;
1765 break;
1766 }
1767 /* re-enter, this exception was guest-internal */
1768 ret = 0;
1769 break;
1770
73aaec4a
JK		 1771 default:
1772 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1773 ret = -1;
1774 break;
d76d1650
AJ		 1775 }
1776
4b8523ee 1777 qemu_mutex_unlock_iothread();
d76d1650
AJ		 1778 return ret;
1779}
1780
31f2cb8f
BB		 1781int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1782{
1783 CPUState *cs = CPU(cpu);
1784 uint32_t bits = tsr_bits;
1785 struct kvm_one_reg reg = {
1786 .id = KVM_REG_PPC_OR_TSR,
1787 .addr = (uintptr_t) &bits,
1788 };
1789
1790 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1791}
1792
1793int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1794{
1795
1796 CPUState *cs = CPU(cpu);
1797 uint32_t bits = tsr_bits;
1798 struct kvm_one_reg reg = {
1799 .id = KVM_REG_PPC_CLEAR_TSR,
1800 .addr = (uintptr_t) &bits,
1801 };
1802
1803 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1804}
1805
1806int kvmppc_set_tcr(PowerPCCPU *cpu)
1807{
1808 CPUState *cs = CPU(cpu);
1809 CPUPPCState *env = &cpu->env;
1810 uint32_t tcr = env->spr[SPR_BOOKE_TCR];
1811
1812 struct kvm_one_reg reg = {
1813 .id = KVM_REG_PPC_TCR,
1814 .addr = (uintptr_t) &tcr,
1815 };
1816
1817 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1818}
1819
1820int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
1821{
1822 CPUState *cs = CPU(cpu);
31f2cb8f
BB		 1823 int ret;
1824
1825 if (!kvm_enabled()) {
1826 return -1;
1827 }
1828
1829 if (!cap_ppc_watchdog) {
1830 printf("warning: KVM does not support watchdog");
1831 return -1;
1832 }
1833
48add816 1834 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0);
31f2cb8f
BB		 1835 if (ret < 0) {
1836 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1837 __func__, strerror(-ret));
1838 return ret;
1839 }
1840
1841 return ret;
1842}
1843
dc333cd6
AG		 1844static int read_cpuinfo(const char *field, char *value, int len)
1845{
1846 FILE *f;
1847 int ret = -1;
1848 int field_len = strlen(field);
1849 char line[512];
1850
1851 f = fopen("/proc/cpuinfo", "r");
1852 if (!f) {
1853 return -1;
1854 }
1855
1856 do {
ef951443 1857 if (!fgets(line, sizeof(line), f)) {
dc333cd6
AG		 1858 break;
1859 }
1860 if (!strncmp(line, field, field_len)) {
ae215068 1861 pstrcpy(value, len, line);
dc333cd6
AG		 1862 ret = 0;
1863 break;
1864 }
c995e942 1865 } while (*line);
dc333cd6
AG		 1866
1867 fclose(f);
1868
1869 return ret;
1870}
1871
1872uint32_t kvmppc_get_tbfreq(void)
1873{
1874 char line[512];
1875 char *ns;
73bcb24d 1876 uint32_t retval = NANOSECONDS_PER_SECOND;
dc333cd6
AG		 1877
1878 if (read_cpuinfo("timebase", line, sizeof(line))) {
1879 return retval;
1880 }
1881
c995e942
DG		 1882 ns = strchr(line, ':');
1883 if (!ns) {
dc333cd6
AG		 1884 return retval;
1885 }
1886
1887 ns++;
1888
f9b8e7f6 1889 return atoi(ns);
dc333cd6 1890}
4513d923 1891
ef951443
ND		 1892bool kvmppc_get_host_serial(char **value)
1893{
1894 return g_file_get_contents("/proc/device-tree/system-id", value, NULL,
1895 NULL);
1896}
1897
1898bool kvmppc_get_host_model(char **value)
1899{
1900 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL);
1901}
1902
eadaada1
AG		 1903/* Try to find a device tree node for a CPU with clock-frequency property */
1904static int kvmppc_find_cpu_dt(char *buf, int buf_len)
1905{
1906 struct dirent *dirp;
1907 DIR *dp;
1908
c995e942
DG		 1909 dp = opendir(PROC_DEVTREE_CPU);
1910 if (!dp) {
eadaada1
AG		 1911 printf("Can't open directory " PROC_DEVTREE_CPU "\n");
1912 return -1;
1913 }
1914
1915 buf[0] = '\0';
1916 while ((dirp = readdir(dp)) != NULL) {
1917 FILE *f;
1918 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
1919 dirp->d_name);
1920 f = fopen(buf, "r");
1921 if (f) {
1922 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name);
1923 fclose(f);
1924 break;
1925 }
1926 buf[0] = '\0';
1927 }
1928 closedir(dp);
1929 if (buf[0] == '\0') {
1930 printf("Unknown host!\n");
1931 return -1;
1932 }
1933
1934 return 0;
1935}
1936
7d94a30b 1937static uint64_t kvmppc_read_int_dt(const char *filename)
eadaada1 1938{
9bc884b7
DG		 1939 union {
1940 uint32_t v32;
1941 uint64_t v64;
1942 } u;
eadaada1
AG		 1943 FILE *f;
1944 int len;
1945
7d94a30b 1946 f = fopen(filename, "rb");
eadaada1
AG		 1947 if (!f) {
1948 return -1;
1949 }
1950
9bc884b7 1951 len = fread(&u, 1, sizeof(u), f);
eadaada1
AG		 1952 fclose(f);
1953 switch (len) {
9bc884b7
DG		 1954 case 4:
1955 /* property is a 32-bit quantity */
1956 return be32_to_cpu(u.v32);
1957 case 8:
1958 return be64_to_cpu(u.v64);
eadaada1
AG		 1959 }
1960
1961 return 0;
1962}
1963
c995e942
DG		 1964/*
1965 * Read a CPU node property from the host device tree that's a single
7d94a30b 1966 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
c995e942
DG		 1967 * (can't find or open the property, or doesn't understand the format)
1968 */
7d94a30b
SB		 1969static uint64_t kvmppc_read_int_cpu_dt(const char *propname)
1970{
1971 char buf[PATH_MAX], *tmp;
1972 uint64_t val;
1973
1974 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
1975 return -1;
1976 }
1977
1978 tmp = g_strdup_printf("%s/%s", buf, propname);
1979 val = kvmppc_read_int_dt(tmp);
1980 g_free(tmp);
1981
1982 return val;
1983}
1984
9bc884b7
DG		 1985uint64_t kvmppc_get_clockfreq(void)
1986{
1987 return kvmppc_read_int_cpu_dt("clock-frequency");
1988}
1989
7d050527
SJS		 1990static int kvmppc_get_dec_bits(void)
1991{
1992 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits");
1993
1994 if (nr_bits > 0) {
1995 return nr_bits;
1996 }
1997 return 0;
1998}
1999
1a61a9ae 2000static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
db70b311
RH		 2001{
2002 CPUState *cs = env_cpu(env);
1a61a9ae 2003
6fd33a75 2004 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
1a61a9ae
SY		 2005 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
2006 return 0;
2007 }
2008
2009 return 1;
2010}
2011
2012int kvmppc_get_hasidle(CPUPPCState *env)
2013{
2014 struct kvm_ppc_pvinfo pvinfo;
2015
2016 if (!kvmppc_get_pvinfo(env, &pvinfo) &&
2017 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) {
2018 return 1;
2019 }
2020
2021 return 0;
2022}
2023
1328c2bf 2024int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len)
45024f09 2025{
c995e942 2026 uint32_t *hc = (uint32_t *)buf;
45024f09
AG		 2027 struct kvm_ppc_pvinfo pvinfo;
2028
1a61a9ae 2029 if (!kvmppc_get_pvinfo(env, &pvinfo)) {
45024f09 2030 memcpy(buf, pvinfo.hcall, buf_len);
45024f09
AG		 2031 return 0;
2032 }
45024f09
AG		 2033
2034 /*
d13fc32e 2035 * Fallback to always fail hypercalls regardless of endianness:
45024f09 2036 *
d13fc32e 2037 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
45024f09 2038 * li r3, -1
d13fc32e
AG		 2039 * b .+8 (becomes nop in wrong endian)
2040 * bswap32(li r3, -1)
45024f09
AG		 2041 */
2042
d13fc32e
AG		 2043 hc[0] = cpu_to_be32(0x08000048);
2044 hc[1] = cpu_to_be32(0x3860ffff);
2045 hc[2] = cpu_to_be32(0x48000008);
2046 hc[3] = cpu_to_be32(bswap32(0x3860ffff));
45024f09 2047
0ddbd053 2048 return 1;
45024f09
AG		 2049}
2050
026bfd89
DG		 2051static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall)
2052{
2053 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1);
2054}
2055
2056void kvmppc_enable_logical_ci_hcalls(void)
2057{
2058 /*
2059 * FIXME: it would be nice if we could detect the cases where
2060 * we're using a device which requires the in kernel
2061 * implementation of these hcalls, but the kernel lacks them and
2062 * produce a warning.
2063 */
2064 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD);
2065 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE);
2066}
2067
ef9971dd
AK		 2068void kvmppc_enable_set_mode_hcall(void)
2069{
2070 kvmppc_enable_hcall(kvm_state, H_SET_MODE);
2071}
2072
5145ad4f
NW		 2073void kvmppc_enable_clear_ref_mod_hcalls(void)
2074{
2075 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF);
2076 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD);
2077}
2078
68f9f708
SJS		 2079void kvmppc_enable_h_page_init(void)
2080{
2081 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT);
2082}
2083
1bc22652 2084void kvmppc_set_papr(PowerPCCPU *cpu)
f61b4bed 2085{
1bc22652 2086 CPUState *cs = CPU(cpu);
f61b4bed
AG		 2087 int ret;
2088
da20aed1
DG		 2089 if (!kvm_enabled()) {
2090 return;
2091 }
2092
48add816 2093 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0);
f61b4bed 2094 if (ret) {
072ed5f2
TH		 2095 error_report("This vCPU type or KVM version does not support PAPR");
2096 exit(1);
94135e81 2097 }
9b00ea49 2098
c995e942
DG		 2099 /*
2100 * Update the capability flag so we sync the right information
2101 * with kvm
2102 */
9b00ea49 2103 cap_papr = 1;
f61b4bed
AG		 2104}
2105
d6e166c0 2106int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr)
6db5bb0f 2107{
d6e166c0 2108 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr);
6db5bb0f
AK		 2109}
2110
5b95b8b9
AG		 2111void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy)
2112{
5b95b8b9 2113 CPUState *cs = CPU(cpu);
5b95b8b9
AG		 2114 int ret;
2115
48add816 2116 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy);
5b95b8b9 2117 if (ret && mpic_proxy) {
072ed5f2
TH		 2118 error_report("This KVM version does not support EPR");
2119 exit(1);
5b95b8b9
AG		 2120 }
2121}
2122
e97c3636
DG		 2123int kvmppc_smt_threads(void)
2124{
2125 return cap_ppc_smt ? cap_ppc_smt : 1;
2126}
2127
fa98fbfc
SB		 2128int kvmppc_set_smt_threads(int smt)
2129{
2130 int ret;
2131
2132 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0);
2133 if (!ret) {
2134 cap_ppc_smt = smt;
2135 }
2136 return ret;
2137}
2138
2139void kvmppc_hint_smt_possible(Error **errp)
2140{
2141 int i;
2142 GString *g;
2143 char *s;
2144
2145 assert(kvm_enabled());
2146 if (cap_ppc_smt_possible) {
2147 g = g_string_new("Available VSMT modes:");
2148 for (i = 63; i >= 0; i--) {
2149 if ((1UL << i) & cap_ppc_smt_possible) {
2150 g_string_append_printf(g, " %lu", (1UL << i));
2151 }
2152 }
2153 s = g_string_free(g, false);
2154 error_append_hint(errp, "%s.\n", s);
2155 g_free(s);
2156 } else {
2157 error_append_hint(errp,
2158 "This KVM seems to be too old to support VSMT.\n");
2159 }
2160}
2161
2162
7f763a5d 2163#ifdef TARGET_PPC64
7f763a5d
DG		 2164uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift)
2165{
f36951c1
DG		 2166 struct kvm_ppc_smmu_info info;
2167 long rampagesize, best_page_shift;
2168 int i;
2169
c995e942
DG		 2170 /*
2171 * Find the largest hardware supported page size that's less than
2172 * or equal to the (logical) backing page size of guest RAM
2173 */
ab256960 2174 kvm_get_smmu_info(&info, &error_fatal);
905b7ee4 2175 rampagesize = qemu_minrampagesize();
f36951c1
DG		 2176 best_page_shift = 0;
2177
2178 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) {
2179 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i];
2180
2181 if (!sps->page_shift) {
2182 continue;
2183 }
2184
2185 if ((sps->page_shift > best_page_shift)
2186 && ((1UL << sps->page_shift) <= rampagesize)) {
2187 best_page_shift = sps->page_shift;
2188 }
2189 }
2190
7f763a5d 2191 return MIN(current_size,
f36951c1 2192 1ULL << (best_page_shift + hash_shift - 7));
7f763a5d
DG		 2193}
2194#endif
2195
da95324e
AK		 2196bool kvmppc_spapr_use_multitce(void)
2197{
2198 return cap_spapr_multitce;
2199}
2200
3dc410ae
AK		 2201int kvmppc_spapr_enable_inkernel_multitce(void)
2202{
2203 int ret;
2204
2205 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2206 H_PUT_TCE_INDIRECT, 1);
2207 if (!ret) {
2208 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2209 H_STUFF_TCE, 1);
2210 }
2211
2212 return ret;
2213}
2214
d6ee2a7c
AK		 2215void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift,
2216 uint64_t bus_offset, uint32_t nb_table,
2217 int *pfd, bool need_vfio)
0f5cb298 2218{
0f5cb298
DG		 2219 long len;
2220 int fd;
2221 void *table;
2222
c995e942
DG		 2223 /*
2224 * Must set fd to -1 so we don't try to munmap when called for
b5aec396
DG		 2225 * destroying the table, which the upper layers -will- do
2226 */
2227 *pfd = -1;
6a81dd17 2228 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) {
0f5cb298
DG		 2229 return NULL;
2230 }
2231
d6ee2a7c
AK		 2232 if (cap_spapr_tce_64) {
2233 struct kvm_create_spapr_tce_64 args = {
2234 .liobn = liobn,
2235 .page_shift = page_shift,
2236 .offset = bus_offset >> page_shift,
2237 .size = nb_table,
2238 .flags = 0
2239 };
2240 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args);
2241 if (fd < 0) {
2242 fprintf(stderr,
2243 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2244 liobn);
2245 return NULL;
2246 }
2247 } else if (cap_spapr_tce) {
2248 uint64_t window_size = (uint64_t) nb_table << page_shift;
2249 struct kvm_create_spapr_tce args = {
2250 .liobn = liobn,
2251 .window_size = window_size,
2252 };
2253 if ((window_size != args.window_size) || bus_offset) {
2254 return NULL;
2255 }
2256 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args);
2257 if (fd < 0) {
2258 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n",
2259 liobn);
2260 return NULL;
2261 }
2262 } else {
0f5cb298
DG		 2263 return NULL;
2264 }
2265
d6ee2a7c 2266 len = nb_table * sizeof(uint64_t);
0f5cb298
DG		 2267 /* FIXME: round this up to page size */
2268
c995e942 2269 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
0f5cb298 2270 if (table == MAP_FAILED) {
b5aec396
DG		 2271 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n",
2272 liobn);
0f5cb298
DG		 2273 close(fd);
2274 return NULL;
2275 }
2276
2277 *pfd = fd;
2278 return table;
2279}
2280
523e7b8a 2281int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table)
0f5cb298
DG		 2282{
2283 long len;
2284
2285 if (fd < 0) {
2286 return -1;
2287 }
2288
523e7b8a 2289 len = nb_table * sizeof(uint64_t);
0f5cb298
DG		 2290 if ((munmap(table, len) < 0) ||
2291 (close(fd) < 0)) {
b5aec396
DG		 2292 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s",
2293 strerror(errno));
0f5cb298
DG		 2294 /* Leak the table */
2295 }
2296
2297 return 0;
2298}
2299
7f763a5d
DG		 2300int kvmppc_reset_htab(int shift_hint)
2301{
2302 uint32_t shift = shift_hint;
2303
ace9a2cb
DG		 2304 if (!kvm_enabled()) {
2305 /* Full emulation, tell caller to allocate htab itself */
2306 return 0;
2307 }
6977afda 2308 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) {
7f763a5d
DG		 2309 int ret;
2310 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift);
ace9a2cb 2311 if (ret == -ENOTTY) {
c995e942
DG		 2312 /*
2313 * At least some versions of PR KVM advertise the
ace9a2cb
DG		 2314 * capability, but don't implement the ioctl(). Oops.
2315 * Return 0 so that we allocate the htab in qemu, as is
c995e942
DG		 2316 * correct for PR.
2317 */
ace9a2cb
DG		 2318 return 0;
2319 } else if (ret < 0) {
7f763a5d
DG		 2320 return ret;
2321 }
2322 return shift;
2323 }
2324
c995e942
DG		 2325 /*
2326 * We have a kernel that predates the htab reset calls. For PR
ace9a2cb 2327 * KVM, we need to allocate the htab ourselves, for an HV KVM of
c995e942
DG		 2328 * this era, it has allocated a 16MB fixed size hash table
2329 * already.
2330 */
96c9cff0 2331 if (kvmppc_is_pr(kvm_state)) {
ace9a2cb
DG		 2332 /* PR - tell caller to allocate htab */
2333 return 0;
2334 } else {
2335 /* HV - assume 16MB kernel allocated htab */
2336 return 24;
2337 }
7f763a5d
DG		 2338}
2339
a1e98583
DG		 2340static inline uint32_t mfpvr(void)
2341{
2342 uint32_t pvr;
2343
2344 asm ("mfpvr %0"
2345 : "=r"(pvr));
2346 return pvr;
2347}
2348
a7342588
DG		 2349static void alter_insns(uint64_t *word, uint64_t flags, bool on)
2350{
2351 if (on) {
2352 *word |= flags;
2353 } else {
2354 *word &= ~flags;
2355 }
2356}
2357
2985b86b
AF		 2358static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
2359{
2360 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
0cbad81f
DG		 2361 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
2362 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
a1e98583 2363
cfe34f44 2364 /* Now fix up the class with information we can query from the host */
3bc9ccc0 2365 pcc->pvr = mfpvr();
a7342588 2366
3f2ca480
DG		 2367 alter_insns(&pcc->insns_flags, PPC_ALTIVEC,
2368 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC);
2369 alter_insns(&pcc->insns_flags2, PPC2_VSX,
2370 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX);
2371 alter_insns(&pcc->insns_flags2, PPC2_DFP,
2372 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP);
0cbad81f
DG		 2373
2374 if (dcache_size != -1) {
2375 pcc->l1_dcache_size = dcache_size;
2376 }
2377
2378 if (icache_size != -1) {
2379 pcc->l1_icache_size = icache_size;
2380 }
c64abd1f
SB		 2381
2382#if defined(TARGET_PPC64)
2383 pcc->radix_page_info = kvm_get_radix_page_info();
5f3066d8
DG		 2384
2385 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
2386 /*
2387 * POWER9 DD1 has some bugs which make it not really ISA 3.00
2388 * compliant. More importantly, advertising ISA 3.00
2389 * architected mode may prevent guests from activating
2390 * necessary DD1 workarounds.
2391 */
2392 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07
2393 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05);
2394 }
c64abd1f 2395#endif /* defined(TARGET_PPC64) */
a1e98583
DG		 2396}
2397
3b961124
SY		 2398bool kvmppc_has_cap_epr(void)
2399{
2400 return cap_epr;
2401}
2402
87a91de6
AG		 2403bool kvmppc_has_cap_fixup_hcalls(void)
2404{
2405 return cap_fixup_hcalls;
2406}
2407
bac3bf28
TH		 2408bool kvmppc_has_cap_htm(void)
2409{
2410 return cap_htm;
2411}
2412
cf1c4cce
SB		 2413bool kvmppc_has_cap_mmu_radix(void)
2414{
2415 return cap_mmu_radix;
2416}
2417
2418bool kvmppc_has_cap_mmu_hash_v3(void)
2419{
2420 return cap_mmu_hash_v3;
2421}
2422
072f416a
SJS		 2423static bool kvmppc_power8_host(void)
2424{
2425 bool ret = false;
2426#ifdef TARGET_PPC64
2427 {
2428 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
2429 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
2430 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
2431 (base_pvr == CPU_POWERPC_POWER8_BASE);
2432 }
2433#endif /* TARGET_PPC64 */
2434 return ret;
2435}
2436
8fea7044
SJS		 2437static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
2438{
072f416a
SJS		 2439 bool l1d_thread_priv_req = !kvmppc_power8_host();
2440
8fea7044
SJS		 2441 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
2442 return 2;
072f416a
SJS		 2443 } else if ((!l1d_thread_priv_req ||
2444 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
8fea7044
SJS		 2445 (c.character & c.character_mask
2446 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
2447 return 1;
2448 }
2449
2450 return 0;
2451}
2452
2453static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)
2454{
2455 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) {
2456 return 2;
2457 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) {
2458 return 1;
2459 }
2460
2461 return 0;
2462}
2463
2464static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
2465{
399b2896
SJS		 2466 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) &&
2467 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) &&
2468 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) {
2469 return SPAPR_CAP_FIXED_NA;
2470 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) {
2471 return SPAPR_CAP_WORKAROUND;
2472 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
8fea7044
SJS		 2473 return SPAPR_CAP_FIXED_CCD;
2474 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) {
2475 return SPAPR_CAP_FIXED_IBS;
2476 }
2477
2478 return 0;
2479}
2480
8ff43ee4
SJS		 2481static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c)
2482{
2483 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) {
2484 return 1;
2485 }
2486 return 0;
2487}
2488
38afd772
CLG		 2489bool kvmppc_has_cap_xive(void)
2490{
2491 return cap_xive;
2492}
2493
8acc2ae5
SJS		 2494static void kvmppc_get_cpu_characteristics(KVMState *s)
2495{
2496 struct kvm_ppc_cpu_char c;
2497 int ret;
2498
2499 /* Assume broken */
2500 cap_ppc_safe_cache = 0;
2501 cap_ppc_safe_bounds_check = 0;
2502 cap_ppc_safe_indirect_branch = 0;
2503
2504 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR);
2505 if (!ret) {
2506 return;
2507 }
2508 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c);
2509 if (ret < 0) {
2510 return;
2511 }
8fea7044
SJS		 2512
2513 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c);
2514 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c);
2515 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c);
8ff43ee4
SJS		 2516 cap_ppc_count_cache_flush_assist =
2517 parse_cap_ppc_count_cache_flush_assist(c);
8acc2ae5
SJS		 2518}
2519
2520int kvmppc_get_cap_safe_cache(void)
2521{
2522 return cap_ppc_safe_cache;
2523}
2524
2525int kvmppc_get_cap_safe_bounds_check(void)
2526{
2527 return cap_ppc_safe_bounds_check;
2528}
2529
2530int kvmppc_get_cap_safe_indirect_branch(void)
2531{
2532 return cap_ppc_safe_indirect_branch;
2533}
2534
8ff43ee4
SJS		 2535int kvmppc_get_cap_count_cache_flush_assist(void)
2536{
2537 return cap_ppc_count_cache_flush_assist;
2538}
2539
b9a477b7
SJS		 2540bool kvmppc_has_cap_nested_kvm_hv(void)
2541{
2542 return !!cap_ppc_nested_kvm_hv;
2543}
2544
2545int kvmppc_set_cap_nested_kvm_hv(int enable)
2546{
2547 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable);
2548}
2549
9ded780c
AK		 2550bool kvmppc_has_cap_spapr_vfio(void)
2551{
2552 return cap_spapr_vfio;
2553}
2554
7d050527
SJS		 2555int kvmppc_get_cap_large_decr(void)
2556{
2557 return cap_large_decr;
2558}
2559
2560int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable)
2561{
2562 CPUState *cs = CPU(cpu);
2563 uint64_t lpcr;
2564
2565 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2566 /* Do we need to modify the LPCR? */
2567 if (!!(lpcr & LPCR_LD) != !!enable) {
2568 if (enable) {
2569 lpcr |= LPCR_LD;
2570 } else {
2571 lpcr &= ~LPCR_LD;
2572 }
2573 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2574 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2575
2576 if (!!(lpcr & LPCR_LD) != !!enable) {
2577 return -1;
2578 }
2579 }
2580
2581 return 0;
2582}
2583
52b2519c
TH		 2584PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void)
2585{
2586 uint32_t host_pvr = mfpvr();
2587 PowerPCCPUClass *pvr_pcc;
2588
2589 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
2590 if (pvr_pcc == NULL) {
2591 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr);
2592 }
2593
2594 return pvr_pcc;
2595}
2596
2e9c10eb 2597static int kvm_ppc_register_host_cpu_type(MachineState *ms)
5ba4576b
AF		 2598{
2599 TypeInfo type_info = {
2600 .name = TYPE_HOST_POWERPC_CPU,
5ba4576b
AF		 2601 .class_init = kvmppc_host_cpu_class_init,
2602 };
2e9c10eb 2603 MachineClass *mc = MACHINE_GET_CLASS(ms);
5ba4576b 2604 PowerPCCPUClass *pvr_pcc;
92e926e1 2605 ObjectClass *oc;
5b79b1ca 2606 DeviceClass *dc;
715d4b96 2607 int i;
5ba4576b 2608
52b2519c 2609 pvr_pcc = kvm_ppc_get_host_cpu_class();
5ba4576b
AF		 2610 if (pvr_pcc == NULL) {
2611 return -1;
2612 }
2613 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc));
2614 type_register(&type_info);
2e9c10eb
IM		 2615 if (object_dynamic_cast(OBJECT(ms), TYPE_SPAPR_MACHINE)) {
2616 /* override TCG default cpu type with 'host' cpu model */
2617 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU;
2618 }
5b79b1ca 2619
92e926e1
GK		 2620 oc = object_class_by_name(type_info.name);
2621 g_assert(oc);
2622
715d4b96
TH		 2623 /*
2624 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2625 * we want "POWER8" to be a "family" alias that points to the current
2626 * host CPU type, too)
2627 */
2628 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc));
2629 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
c5354f54 2630 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) {
715d4b96
TH		 2631 char *suffix;
2632
2633 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc));
c9137065 2634 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX);
715d4b96
TH		 2635 if (suffix) {
2636 *suffix = 0;
2637 }
715d4b96
TH		 2638 break;
2639 }
2640 }
2641
5ba4576b
AF		 2642 return 0;
2643}
2644
feaa64c4
DG		 2645int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function)
2646{
2647 struct kvm_rtas_token_args args = {
2648 .token = token,
2649 };
2650
2651 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) {
2652 return -ENOENT;
2653 }
2654
7701aeed 2655 strncpy(args.name, function, sizeof(args.name) - 1);
feaa64c4
DG		 2656
2657 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args);
2658}
12b1143b 2659
14b0d748 2660int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp)
e68cb8b4
AK		 2661{
2662 struct kvm_get_htab_fd s = {
2663 .flags = write ? KVM_GET_HTAB_WRITE : 0,
14b0d748 2664 .start_index = index,
e68cb8b4 2665 };
82be8e73 2666 int ret;
e68cb8b4
AK		 2667
2668 if (!cap_htab_fd) {
14b0d748
GK		 2669 error_setg(errp, "KVM version doesn't support %s the HPT",
2670 write ? "writing" : "reading");
82be8e73
GK		 2671 return -ENOTSUP;
2672 }
2673
2674 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s);
2675 if (ret < 0) {
14b0d748
GK		 2676 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s",
2677 write ? "writing" : "reading", write ? "to" : "from",
2678 strerror(errno));
82be8e73 2679 return -errno;
e68cb8b4
AK		 2680 }
2681
82be8e73 2682 return ret;
e68cb8b4
AK		 2683}
2684
2685int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns)
2686{
bc72ad67 2687 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
e68cb8b4
AK		 2688 uint8_t buf[bufsize];
2689 ssize_t rc;
2690
2691 do {
2692 rc = read(fd, buf, bufsize);
2693 if (rc < 0) {
2694 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n",
2695 strerror(errno));
2696 return rc;
2697 } else if (rc) {
e094c4c1
CLG		 2698 uint8_t *buffer = buf;
2699 ssize_t n = rc;
2700 while (n) {
2701 struct kvm_get_htab_header *head =
2702 (struct kvm_get_htab_header *) buffer;
2703 size_t chunksize = sizeof(*head) +
2704 HASH_PTE_SIZE_64 * head->n_valid;
2705
2706 qemu_put_be32(f, head->index);
2707 qemu_put_be16(f, head->n_valid);
2708 qemu_put_be16(f, head->n_invalid);
2709 qemu_put_buffer(f, (void *)(head + 1),
2710 HASH_PTE_SIZE_64 * head->n_valid);
2711
2712 buffer += chunksize;
2713 n -= chunksize;
2714 }
e68cb8b4
AK		 2715 }
2716 } while ((rc != 0)
c995e942
DG		 2717 && ((max_ns < 0) ||
2718 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns)));
e68cb8b4
AK		 2719
2720 return (rc == 0) ? 1 : 0;
2721}
2722
2723int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
2724 uint16_t n_valid, uint16_t n_invalid)
2725{
2726 struct kvm_get_htab_header *buf;
c995e942 2727 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64;
e68cb8b4
AK		 2728 ssize_t rc;
2729
2730 buf = alloca(chunksize);
e68cb8b4
AK		 2731 buf->index = index;
2732 buf->n_valid = n_valid;
2733 buf->n_invalid = n_invalid;
2734
c995e942 2735 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid);
e68cb8b4
AK		 2736
2737 rc = write(fd, buf, chunksize);
2738 if (rc < 0) {
2739 fprintf(stderr, "Error writing KVM hash table: %s\n",
2740 strerror(errno));
2741 return rc;
2742 }
2743 if (rc != chunksize) {
2744 /* We should never get a short write on a single chunk */
2745 fprintf(stderr, "Short write, restoring KVM hash table\n");
2746 return -1;
2747 }
2748 return 0;
2749}
2750
20d695a9 2751bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
4513d923
GN		 2752{
2753 return true;
2754}
a1b87fe0 2755
82169660
SW		 2756void kvm_arch_init_irq_routing(KVMState *s)
2757{
2758}
c65f9a07 2759
1ad9f0a4 2760void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n)
7c43bca0 2761{
1ad9f0a4
DG		 2762 int fd, rc;
2763 int i;
7c43bca0 2764
14b0d748 2765 fd = kvmppc_get_htab_fd(false, ptex, &error_abort);
7c43bca0 2766
1ad9f0a4
DG		 2767 i = 0;
2768 while (i < n) {
2769 struct kvm_get_htab_header *hdr;
2770 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP;
2771 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64];
7c43bca0 2772
1ad9f0a4
DG		 2773 rc = read(fd, buf, sizeof(buf));
2774 if (rc < 0) {
2775 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2776 }
7c43bca0 2777
1ad9f0a4
DG		 2778 hdr = (struct kvm_get_htab_header *)buf;
2779 while ((i < n) && ((char *)hdr < (buf + rc))) {
a36593e1 2780 int invalid = hdr->n_invalid, valid = hdr->n_valid;
7c43bca0 2781
1ad9f0a4
DG		 2782 if (hdr->index != (ptex + i)) {
2783 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2784 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i);
2785 }
2786
a36593e1
AK		 2787 if (n - i < valid) {
2788 valid = n - i;
2789 }
2790 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid);
2791 i += valid;
7c43bca0 2792
1ad9f0a4
DG		 2793 if ((n - i) < invalid) {
2794 invalid = n - i;
2795 }
2796 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64);
a36593e1 2797 i += invalid;
1ad9f0a4
DG		 2798
2799 hdr = (struct kvm_get_htab_header *)
2800 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid);
2801 }
2802 }
2803
2804 close(fd);
7c43bca0 2805}
c1385933 2806
1ad9f0a4 2807void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1)
c1385933 2808{
1ad9f0a4 2809 int fd, rc;
1ad9f0a4
DG		 2810 struct {
2811 struct kvm_get_htab_header hdr;
2812 uint64_t pte0;
2813 uint64_t pte1;
2814 } buf;
c1385933 2815
14b0d748 2816 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort);
c1385933 2817
1ad9f0a4
DG		 2818 buf.hdr.n_valid = 1;
2819 buf.hdr.n_invalid = 0;
2820 buf.hdr.index = ptex;
2821 buf.pte0 = cpu_to_be64(pte0);
2822 buf.pte1 = cpu_to_be64(pte1);
c1385933 2823
1ad9f0a4
DG		 2824 rc = write(fd, &buf, sizeof(buf));
2825 if (rc != sizeof(buf)) {
2826 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2827 }
2828 close(fd);
c1385933 2829}
9e03a040
FB		 2830
2831int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 2832 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040
FB		 2833{
2834 return 0;
2835}
1850b6b7 2836
38d87493
PX		 2837int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
2838 int vector, PCIDevice *dev)
2839{
2840 return 0;
2841}
2842
2843int kvm_arch_release_virq_post(int virq)
2844{
2845 return 0;
2846}
2847
1850b6b7
EA		 2848int kvm_arch_msi_data_to_gsi(uint32_t data)
2849{
2850 return data & 0xffff;
2851}
4d9392be
TH		 2852
2853int kvmppc_enable_hwrng(void)
2854{
2855 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) {
2856 return -1;
2857 }
2858
2859 return kvmppc_enable_hcall(kvm_state, H_RANDOM);
2860}
30f4b05b
DG		 2861
2862void kvmppc_check_papr_resize_hpt(Error **errp)
2863{
2864 if (!kvm_enabled()) {
b55d295e
DG		 2865 return; /* No KVM, we're good */
2866 }
2867
2868 if (cap_resize_hpt) {
2869 return; /* Kernel has explicit support, we're good */
30f4b05b
DG		 2870 }
2871
b55d295e
DG		 2872 /* Otherwise fallback on looking for PR KVM */
2873 if (kvmppc_is_pr(kvm_state)) {
2874 return;
2875 }
30f4b05b
DG		 2876
2877 error_setg(errp,
2878 "Hash page table resizing not available with this KVM version");
2879}
b55d295e
DG		 2880
2881int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift)
2882{
2883 CPUState *cs = CPU(cpu);
2884 struct kvm_ppc_resize_hpt rhpt = {
2885 .flags = flags,
2886 .shift = shift,
2887 };
2888
2889 if (!cap_resize_hpt) {
2890 return -ENOSYS;
2891 }
2892
2893 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt);
2894}
2895
2896int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift)
2897{
2898 CPUState *cs = CPU(cpu);
2899 struct kvm_ppc_resize_hpt rhpt = {
2900 .flags = flags,
2901 .shift = shift,
2902 };
2903
2904 if (!cap_resize_hpt) {
2905 return -ENOSYS;
2906 }
2907
2908 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt);
2909}
2910
c363a37a
DHB		 2911/*
2912 * This is a helper function to detect a post migration scenario
2913 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2914 * the guest kernel can't handle a PVR value other than the actual host
2915 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2916 *
2917 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2918 * (so, we're HV), return true. The workaround itself is done in
2919 * cpu_post_load.
2920 *
2921 * The order here is important: we'll only check for KVM PR as a
2922 * fallback if the guest kernel can't handle the situation itself.
2923 * We need to avoid as much as possible querying the running KVM type
2924 * in QEMU level.
2925 */
2926bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu)
2927{
2928 CPUState *cs = CPU(cpu);
2929
2930 if (!kvm_enabled()) {
2931 return false;
2932 }
2933
2934 if (cap_ppc_pvr_compat) {
2935 return false;
2936 }
2937
2938 return !kvmppc_is_pr(cs->kvm_state);
2939}
a84f7179
ND		 2940
2941void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online)
2942{
2943 CPUState *cs = CPU(cpu);
2944
2945 if (kvm_enabled()) {
2946 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online);
2947 }
2948}
9723295a
GK		 2949
2950void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset)
2951{
2952 CPUState *cs = CPU(cpu);
2953
2954 if (kvm_enabled()) {
2955 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset);
2956 }
2957}
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