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Commit | Line | Data |
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0d75590d | 1 | #include "qemu/osdep.h" |
33c11879 PB |
2 | #include "qemu-common.h" |
3 | #include "cpu.h" | |
63c91552 | 4 | #include "exec/exec-all.h" |
8dd3dca3 AJ |
5 | #include "hw/hw.h" |
6 | #include "hw/boards.h" | |
9c17d615 | 7 | #include "sysemu/kvm.h" |
a90db158 | 8 | #include "helper_regs.h" |
cd6a9bb6 | 9 | #include "mmu-hash64.h" |
1e00b8d5 | 10 | #include "migration/cpu.h" |
d5fc133e | 11 | #include "qapi/error.h" |
c363a37a | 12 | #include "kvm_ppc.h" |
8dd3dca3 | 13 | |
a90db158 | 14 | static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) |
8dd3dca3 | 15 | { |
a90db158 AK |
16 | PowerPCCPU *cpu = opaque; |
17 | CPUPPCState *env = &cpu->env; | |
a456d59c | 18 | unsigned int i, j; |
bb593904 | 19 | target_ulong sdr1; |
30304420 | 20 | uint32_t fpscr; |
da91a00f | 21 | target_ulong xer; |
a456d59c BS |
22 | |
23 | for (i = 0; i < 32; i++) | |
24 | qemu_get_betls(f, &env->gpr[i]); | |
25 | #if !defined(TARGET_PPC64) | |
26 | for (i = 0; i < 32; i++) | |
27 | qemu_get_betls(f, &env->gprh[i]); | |
28 | #endif | |
29 | qemu_get_betls(f, &env->lr); | |
30 | qemu_get_betls(f, &env->ctr); | |
31 | for (i = 0; i < 8; i++) | |
32 | qemu_get_be32s(f, &env->crf[i]); | |
da91a00f RH |
33 | qemu_get_betls(f, &xer); |
34 | cpu_write_xer(env, xer); | |
18b21a2f | 35 | qemu_get_betls(f, &env->reserve_addr); |
a456d59c BS |
36 | qemu_get_betls(f, &env->msr); |
37 | for (i = 0; i < 4; i++) | |
38 | qemu_get_betls(f, &env->tgpr[i]); | |
39 | for (i = 0; i < 32; i++) { | |
40 | union { | |
41 | float64 d; | |
42 | uint64_t l; | |
43 | } u; | |
44 | u.l = qemu_get_be64(f); | |
45 | env->fpr[i] = u.d; | |
46 | } | |
30304420 DG |
47 | qemu_get_be32s(f, &fpscr); |
48 | env->fpscr = fpscr; | |
a456d59c | 49 | qemu_get_sbe32s(f, &env->access_type); |
a456d59c | 50 | #if defined(TARGET_PPC64) |
9baea4a3 | 51 | qemu_get_betls(f, &env->spr[SPR_ASR]); |
a456d59c BS |
52 | qemu_get_sbe32s(f, &env->slb_nr); |
53 | #endif | |
bb593904 | 54 | qemu_get_betls(f, &sdr1); |
a456d59c BS |
55 | for (i = 0; i < 32; i++) |
56 | qemu_get_betls(f, &env->sr[i]); | |
57 | for (i = 0; i < 2; i++) | |
58 | for (j = 0; j < 8; j++) | |
59 | qemu_get_betls(f, &env->DBAT[i][j]); | |
60 | for (i = 0; i < 2; i++) | |
61 | for (j = 0; j < 8; j++) | |
62 | qemu_get_betls(f, &env->IBAT[i][j]); | |
63 | qemu_get_sbe32s(f, &env->nb_tlb); | |
64 | qemu_get_sbe32s(f, &env->tlb_per_way); | |
65 | qemu_get_sbe32s(f, &env->nb_ways); | |
66 | qemu_get_sbe32s(f, &env->last_way); | |
67 | qemu_get_sbe32s(f, &env->id_tlbs); | |
68 | qemu_get_sbe32s(f, &env->nb_pids); | |
1c53accc | 69 | if (env->tlb.tlb6) { |
a456d59c BS |
70 | // XXX assumes 6xx |
71 | for (i = 0; i < env->nb_tlb; i++) { | |
1c53accc AG |
72 | qemu_get_betls(f, &env->tlb.tlb6[i].pte0); |
73 | qemu_get_betls(f, &env->tlb.tlb6[i].pte1); | |
74 | qemu_get_betls(f, &env->tlb.tlb6[i].EPN); | |
a456d59c BS |
75 | } |
76 | } | |
77 | for (i = 0; i < 4; i++) | |
78 | qemu_get_betls(f, &env->pb[i]); | |
a456d59c BS |
79 | for (i = 0; i < 1024; i++) |
80 | qemu_get_betls(f, &env->spr[i]); | |
e57ca75c | 81 | if (!cpu->vhyp) { |
f3c75d42 AK |
82 | ppc_store_sdr1(env, sdr1); |
83 | } | |
a456d59c BS |
84 | qemu_get_be32s(f, &env->vscr); |
85 | qemu_get_be64s(f, &env->spe_acc); | |
86 | qemu_get_be32s(f, &env->spe_fscr); | |
87 | qemu_get_betls(f, &env->msr_mask); | |
88 | qemu_get_be32s(f, &env->flags); | |
89 | qemu_get_sbe32s(f, &env->error_code); | |
90 | qemu_get_be32s(f, &env->pending_interrupts); | |
a456d59c BS |
91 | qemu_get_be32s(f, &env->irq_input_state); |
92 | for (i = 0; i < POWERPC_EXCP_NB; i++) | |
93 | qemu_get_betls(f, &env->excp_vectors[i]); | |
94 | qemu_get_betls(f, &env->excp_prefix); | |
95 | qemu_get_betls(f, &env->ivor_mask); | |
96 | qemu_get_betls(f, &env->ivpr_mask); | |
97 | qemu_get_betls(f, &env->hreset_vector); | |
a456d59c BS |
98 | qemu_get_betls(f, &env->nip); |
99 | qemu_get_betls(f, &env->hflags); | |
100 | qemu_get_betls(f, &env->hflags_nmsr); | |
9fb04491 | 101 | qemu_get_sbe32(f); /* Discard unused mmu_idx */ |
011aba24 | 102 | qemu_get_sbe32(f); /* Discard unused power_mode */ |
a456d59c | 103 | |
9fb04491 BH |
104 | /* Recompute mmu indices */ |
105 | hreg_compute_mem_idx(env); | |
106 | ||
8dd3dca3 AJ |
107 | return 0; |
108 | } | |
a90db158 | 109 | |
2c21ee76 | 110 | static int get_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field) |
a90db158 AK |
111 | { |
112 | ppc_avr_t *v = pv; | |
113 | ||
114 | v->u64[0] = qemu_get_be64(f); | |
115 | v->u64[1] = qemu_get_be64(f); | |
116 | ||
117 | return 0; | |
118 | } | |
119 | ||
2c21ee76 JD |
120 | static int put_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field, |
121 | QJSON *vmdesc) | |
a90db158 AK |
122 | { |
123 | ppc_avr_t *v = pv; | |
124 | ||
125 | qemu_put_be64(f, v->u64[0]); | |
126 | qemu_put_be64(f, v->u64[1]); | |
2c21ee76 | 127 | return 0; |
a90db158 AK |
128 | } |
129 | ||
cfd54a04 | 130 | static const VMStateInfo vmstate_info_avr = { |
a90db158 AK |
131 | .name = "avr", |
132 | .get = get_avr, | |
133 | .put = put_avr, | |
134 | }; | |
135 | ||
136 | #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \ | |
137 | VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t) | |
138 | ||
139 | #define VMSTATE_AVR_ARRAY(_f, _s, _n) \ | |
140 | VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0) | |
141 | ||
146c11f1 DG |
142 | static bool cpu_pre_2_8_migration(void *opaque, int version_id) |
143 | { | |
144 | PowerPCCPU *cpu = opaque; | |
145 | ||
146 | return cpu->pre_2_8_migration; | |
147 | } | |
148 | ||
44b1ff31 | 149 | static int cpu_pre_save(void *opaque) |
a90db158 AK |
150 | { |
151 | PowerPCCPU *cpu = opaque; | |
152 | CPUPPCState *env = &cpu->env; | |
153 | int i; | |
16a2497b DG |
154 | uint64_t insns_compat_mask = |
155 | PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | |
156 | | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | |
157 | | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES | |
158 | | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT | |
159 | | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | |
160 | | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | |
161 | | PPC_64B | PPC_64BX | PPC_ALTIVEC | |
162 | | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; | |
163 | uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | |
164 | | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | |
165 | | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | |
166 | | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | |
167 | | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | |
168 | | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM; | |
a90db158 AK |
169 | |
170 | env->spr[SPR_LR] = env->lr; | |
171 | env->spr[SPR_CTR] = env->ctr; | |
aa378598 | 172 | env->spr[SPR_XER] = cpu_read_xer(env); |
a90db158 AK |
173 | #if defined(TARGET_PPC64) |
174 | env->spr[SPR_CFAR] = env->cfar; | |
175 | #endif | |
176 | env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr; | |
177 | ||
178 | for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { | |
179 | env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i]; | |
180 | env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i]; | |
181 | env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i]; | |
182 | env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i]; | |
183 | } | |
184 | for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { | |
185 | env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4]; | |
186 | env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4]; | |
187 | env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4]; | |
188 | env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4]; | |
189 | } | |
16a2497b DG |
190 | |
191 | /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */ | |
146c11f1 DG |
192 | if (cpu->pre_2_8_migration) { |
193 | cpu->mig_msr_mask = env->msr_mask; | |
194 | cpu->mig_insns_flags = env->insns_flags & insns_compat_mask; | |
0ab2f8e3 GK |
195 | /* CPU models supported by old machines all have PPC_MEM_TLBIE, |
196 | * so we set it unconditionally to allow backward migration from | |
197 | * a POWER9 host to a POWER8 host. | |
198 | */ | |
199 | cpu->mig_insns_flags |= PPC_MEM_TLBIE; | |
146c11f1 DG |
200 | cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2; |
201 | cpu->mig_nb_BATs = env->nb_BATs; | |
202 | } | |
44b1ff31 DDAG |
203 | |
204 | return 0; | |
a90db158 AK |
205 | } |
206 | ||
d5fc133e DG |
207 | /* |
208 | * Determine if a given PVR is a "close enough" match to the CPU | |
209 | * object. For TCG and KVM PR it would probably be sufficient to | |
210 | * require an exact PVR match. However for KVM HV the user is | |
211 | * restricted to a PVR exactly matching the host CPU. The correct way | |
212 | * to handle this is to put the guest into an architected | |
213 | * compatibility mode. However, to allow a more forgiving transition | |
214 | * and migration from before this was widely done, we allow migration | |
215 | * between sufficiently similar PVRs, as determined by the CPU class's | |
216 | * pvr_match() hook. | |
217 | */ | |
218 | static bool pvr_match(PowerPCCPU *cpu, uint32_t pvr) | |
219 | { | |
220 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); | |
221 | ||
222 | if (pvr == pcc->pvr) { | |
223 | return true; | |
224 | } | |
225 | return pcc->pvr_match(pcc, pvr); | |
226 | } | |
227 | ||
a90db158 AK |
228 | static int cpu_post_load(void *opaque, int version_id) |
229 | { | |
230 | PowerPCCPU *cpu = opaque; | |
231 | CPUPPCState *env = &cpu->env; | |
232 | int i; | |
2360b6e8 | 233 | target_ulong msr; |
a90db158 | 234 | |
569be9f0 | 235 | /* |
d5fc133e DG |
236 | * If we're operating in compat mode, we should be ok as long as |
237 | * the destination supports the same compatiblity mode. | |
238 | * | |
239 | * Otherwise, however, we require that the destination has exactly | |
240 | * the same CPU model as the source. | |
569be9f0 | 241 | */ |
d5fc133e DG |
242 | |
243 | #if defined(TARGET_PPC64) | |
244 | if (cpu->compat_pvr) { | |
e07cc192 | 245 | uint32_t compat_pvr = cpu->compat_pvr; |
d5fc133e DG |
246 | Error *local_err = NULL; |
247 | ||
e07cc192 SJS |
248 | cpu->compat_pvr = 0; |
249 | ppc_set_compat(cpu, compat_pvr, &local_err); | |
d5fc133e DG |
250 | if (local_err) { |
251 | error_report_err(local_err); | |
d5fc133e DG |
252 | return -1; |
253 | } | |
254 | } else | |
255 | #endif | |
256 | { | |
257 | if (!pvr_match(cpu, env->spr[SPR_PVR])) { | |
258 | return -1; | |
259 | } | |
260 | } | |
261 | ||
c363a37a DHB |
262 | /* |
263 | * If we're running with KVM HV, there is a chance that the guest | |
264 | * is running with KVM HV and its kernel does not have the | |
265 | * capability of dealing with a different PVR other than this | |
266 | * exact host PVR in KVM_SET_SREGS. If that happens, the | |
267 | * guest freezes after migration. | |
268 | * | |
269 | * The function kvmppc_pvr_workaround_required does this verification | |
270 | * by first checking if the kernel has the cap, returning true immediately | |
271 | * if that is the case. Otherwise, it checks if we're running in KVM PR. | |
272 | * If the guest kernel does not have the cap and we're not running KVM-PR | |
273 | * (so, it is running KVM-HV), we need to ensure that KVM_SET_SREGS will | |
274 | * receive the PVR it expects as a workaround. | |
275 | * | |
276 | */ | |
277 | #if defined(CONFIG_KVM) | |
278 | if (kvmppc_pvr_workaround_required(cpu)) { | |
279 | env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value; | |
280 | } | |
281 | #endif | |
282 | ||
a90db158 AK |
283 | env->lr = env->spr[SPR_LR]; |
284 | env->ctr = env->spr[SPR_CTR]; | |
6a9620e6 | 285 | cpu_write_xer(env, env->spr[SPR_XER]); |
a90db158 AK |
286 | #if defined(TARGET_PPC64) |
287 | env->cfar = env->spr[SPR_CFAR]; | |
288 | #endif | |
289 | env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR]; | |
290 | ||
291 | for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { | |
292 | env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i]; | |
293 | env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1]; | |
294 | env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i]; | |
295 | env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1]; | |
296 | } | |
297 | for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { | |
298 | env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i]; | |
299 | env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1]; | |
300 | env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i]; | |
301 | env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1]; | |
302 | } | |
303 | ||
e57ca75c | 304 | if (!cpu->vhyp) { |
f3c75d42 AK |
305 | ppc_store_sdr1(env, env->spr[SPR_SDR1]); |
306 | } | |
2360b6e8 | 307 | |
be1b21e8 | 308 | /* Invalidate all supported msr bits except MSR_TGPR/MSR_HVB before restoring */ |
2360b6e8 | 309 | msr = env->msr; |
be1b21e8 | 310 | env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); |
2360b6e8 MCA |
311 | ppc_store_msr(env, msr); |
312 | ||
a90db158 AK |
313 | hreg_compute_mem_idx(env); |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
318 | static bool fpu_needed(void *opaque) | |
319 | { | |
320 | PowerPCCPU *cpu = opaque; | |
321 | ||
322 | return (cpu->env.insns_flags & PPC_FLOAT); | |
323 | } | |
324 | ||
325 | static const VMStateDescription vmstate_fpu = { | |
326 | .name = "cpu/fpu", | |
327 | .version_id = 1, | |
328 | .minimum_version_id = 1, | |
5cd8cada | 329 | .needed = fpu_needed, |
3aff6c2f | 330 | .fields = (VMStateField[]) { |
a90db158 AK |
331 | VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32), |
332 | VMSTATE_UINTTL(env.fpscr, PowerPCCPU), | |
333 | VMSTATE_END_OF_LIST() | |
334 | }, | |
335 | }; | |
336 | ||
337 | static bool altivec_needed(void *opaque) | |
338 | { | |
339 | PowerPCCPU *cpu = opaque; | |
340 | ||
341 | return (cpu->env.insns_flags & PPC_ALTIVEC); | |
342 | } | |
343 | ||
344 | static const VMStateDescription vmstate_altivec = { | |
345 | .name = "cpu/altivec", | |
346 | .version_id = 1, | |
347 | .minimum_version_id = 1, | |
5cd8cada | 348 | .needed = altivec_needed, |
3aff6c2f | 349 | .fields = (VMStateField[]) { |
a90db158 AK |
350 | VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32), |
351 | VMSTATE_UINT32(env.vscr, PowerPCCPU), | |
352 | VMSTATE_END_OF_LIST() | |
353 | }, | |
354 | }; | |
355 | ||
356 | static bool vsx_needed(void *opaque) | |
357 | { | |
358 | PowerPCCPU *cpu = opaque; | |
359 | ||
360 | return (cpu->env.insns_flags2 & PPC2_VSX); | |
361 | } | |
362 | ||
363 | static const VMStateDescription vmstate_vsx = { | |
364 | .name = "cpu/vsx", | |
365 | .version_id = 1, | |
366 | .minimum_version_id = 1, | |
5cd8cada | 367 | .needed = vsx_needed, |
3aff6c2f | 368 | .fields = (VMStateField[]) { |
a90db158 AK |
369 | VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32), |
370 | VMSTATE_END_OF_LIST() | |
371 | }, | |
372 | }; | |
373 | ||
80b3f79b AK |
374 | #ifdef TARGET_PPC64 |
375 | /* Transactional memory state */ | |
376 | static bool tm_needed(void *opaque) | |
377 | { | |
378 | PowerPCCPU *cpu = opaque; | |
379 | CPUPPCState *env = &cpu->env; | |
380 | return msr_ts; | |
381 | } | |
382 | ||
383 | static const VMStateDescription vmstate_tm = { | |
384 | .name = "cpu/tm", | |
385 | .version_id = 1, | |
386 | .minimum_version_id = 1, | |
387 | .minimum_version_id_old = 1, | |
5cd8cada | 388 | .needed = tm_needed, |
80b3f79b AK |
389 | .fields = (VMStateField []) { |
390 | VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32), | |
391 | VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64), | |
392 | VMSTATE_UINT64(env.tm_cr, PowerPCCPU), | |
393 | VMSTATE_UINT64(env.tm_lr, PowerPCCPU), | |
394 | VMSTATE_UINT64(env.tm_ctr, PowerPCCPU), | |
395 | VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU), | |
396 | VMSTATE_UINT64(env.tm_amr, PowerPCCPU), | |
397 | VMSTATE_UINT64(env.tm_ppr, PowerPCCPU), | |
398 | VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU), | |
399 | VMSTATE_UINT32(env.tm_vscr, PowerPCCPU), | |
400 | VMSTATE_UINT64(env.tm_dscr, PowerPCCPU), | |
401 | VMSTATE_UINT64(env.tm_tar, PowerPCCPU), | |
402 | VMSTATE_END_OF_LIST() | |
403 | }, | |
404 | }; | |
405 | #endif | |
406 | ||
a90db158 AK |
407 | static bool sr_needed(void *opaque) |
408 | { | |
409 | #ifdef TARGET_PPC64 | |
410 | PowerPCCPU *cpu = opaque; | |
411 | ||
412 | return !(cpu->env.mmu_model & POWERPC_MMU_64); | |
413 | #else | |
414 | return true; | |
415 | #endif | |
416 | } | |
417 | ||
418 | static const VMStateDescription vmstate_sr = { | |
419 | .name = "cpu/sr", | |
420 | .version_id = 1, | |
421 | .minimum_version_id = 1, | |
5cd8cada | 422 | .needed = sr_needed, |
3aff6c2f | 423 | .fields = (VMStateField[]) { |
a90db158 AK |
424 | VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32), |
425 | VMSTATE_END_OF_LIST() | |
426 | }, | |
427 | }; | |
428 | ||
429 | #ifdef TARGET_PPC64 | |
2c21ee76 | 430 | static int get_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field) |
a90db158 AK |
431 | { |
432 | ppc_slb_t *v = pv; | |
433 | ||
434 | v->esid = qemu_get_be64(f); | |
435 | v->vsid = qemu_get_be64(f); | |
436 | ||
437 | return 0; | |
438 | } | |
439 | ||
2c21ee76 JD |
440 | static int put_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field, |
441 | QJSON *vmdesc) | |
a90db158 AK |
442 | { |
443 | ppc_slb_t *v = pv; | |
444 | ||
445 | qemu_put_be64(f, v->esid); | |
446 | qemu_put_be64(f, v->vsid); | |
2c21ee76 | 447 | return 0; |
a90db158 AK |
448 | } |
449 | ||
cfd54a04 | 450 | static const VMStateInfo vmstate_info_slbe = { |
a90db158 AK |
451 | .name = "slbe", |
452 | .get = get_slbe, | |
453 | .put = put_slbe, | |
454 | }; | |
455 | ||
456 | #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \ | |
457 | VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t) | |
458 | ||
459 | #define VMSTATE_SLB_ARRAY(_f, _s, _n) \ | |
460 | VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0) | |
461 | ||
462 | static bool slb_needed(void *opaque) | |
463 | { | |
464 | PowerPCCPU *cpu = opaque; | |
465 | ||
466 | /* We don't support any of the old segment table based 64-bit CPUs */ | |
467 | return (cpu->env.mmu_model & POWERPC_MMU_64); | |
468 | } | |
469 | ||
cd6a9bb6 DG |
470 | static int slb_post_load(void *opaque, int version_id) |
471 | { | |
472 | PowerPCCPU *cpu = opaque; | |
473 | CPUPPCState *env = &cpu->env; | |
474 | int i; | |
475 | ||
476 | /* We've pulled in the raw esid and vsid values from the migration | |
477 | * stream, but we need to recompute the page size pointers */ | |
478 | for (i = 0; i < env->slb_nr; i++) { | |
479 | if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) { | |
480 | /* Migration source had bad values in its SLB */ | |
481 | return -1; | |
482 | } | |
483 | } | |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
a90db158 AK |
488 | static const VMStateDescription vmstate_slb = { |
489 | .name = "cpu/slb", | |
490 | .version_id = 1, | |
491 | .minimum_version_id = 1, | |
5cd8cada | 492 | .needed = slb_needed, |
cd6a9bb6 | 493 | .post_load = slb_post_load, |
3aff6c2f | 494 | .fields = (VMStateField[]) { |
d2164ad3 | 495 | VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU, NULL), |
d83af167 | 496 | VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES), |
a90db158 AK |
497 | VMSTATE_END_OF_LIST() |
498 | } | |
499 | }; | |
500 | #endif /* TARGET_PPC64 */ | |
501 | ||
502 | static const VMStateDescription vmstate_tlb6xx_entry = { | |
503 | .name = "cpu/tlb6xx_entry", | |
504 | .version_id = 1, | |
505 | .minimum_version_id = 1, | |
3aff6c2f | 506 | .fields = (VMStateField[]) { |
a90db158 AK |
507 | VMSTATE_UINTTL(pte0, ppc6xx_tlb_t), |
508 | VMSTATE_UINTTL(pte1, ppc6xx_tlb_t), | |
509 | VMSTATE_UINTTL(EPN, ppc6xx_tlb_t), | |
510 | VMSTATE_END_OF_LIST() | |
511 | }, | |
512 | }; | |
513 | ||
514 | static bool tlb6xx_needed(void *opaque) | |
515 | { | |
516 | PowerPCCPU *cpu = opaque; | |
517 | CPUPPCState *env = &cpu->env; | |
518 | ||
519 | return env->nb_tlb && (env->tlb_type == TLB_6XX); | |
520 | } | |
521 | ||
522 | static const VMStateDescription vmstate_tlb6xx = { | |
523 | .name = "cpu/tlb6xx", | |
524 | .version_id = 1, | |
525 | .minimum_version_id = 1, | |
5cd8cada | 526 | .needed = tlb6xx_needed, |
3aff6c2f | 527 | .fields = (VMStateField[]) { |
d2164ad3 | 528 | VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), |
a90db158 AK |
529 | VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU, |
530 | env.nb_tlb, | |
531 | vmstate_tlb6xx_entry, | |
532 | ppc6xx_tlb_t), | |
533 | VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4), | |
534 | VMSTATE_END_OF_LIST() | |
535 | } | |
536 | }; | |
537 | ||
538 | static const VMStateDescription vmstate_tlbemb_entry = { | |
539 | .name = "cpu/tlbemb_entry", | |
540 | .version_id = 1, | |
541 | .minimum_version_id = 1, | |
3aff6c2f | 542 | .fields = (VMStateField[]) { |
a90db158 AK |
543 | VMSTATE_UINT64(RPN, ppcemb_tlb_t), |
544 | VMSTATE_UINTTL(EPN, ppcemb_tlb_t), | |
545 | VMSTATE_UINTTL(PID, ppcemb_tlb_t), | |
546 | VMSTATE_UINTTL(size, ppcemb_tlb_t), | |
547 | VMSTATE_UINT32(prot, ppcemb_tlb_t), | |
548 | VMSTATE_UINT32(attr, ppcemb_tlb_t), | |
549 | VMSTATE_END_OF_LIST() | |
550 | }, | |
551 | }; | |
552 | ||
553 | static bool tlbemb_needed(void *opaque) | |
554 | { | |
555 | PowerPCCPU *cpu = opaque; | |
556 | CPUPPCState *env = &cpu->env; | |
557 | ||
558 | return env->nb_tlb && (env->tlb_type == TLB_EMB); | |
559 | } | |
560 | ||
561 | static bool pbr403_needed(void *opaque) | |
562 | { | |
563 | PowerPCCPU *cpu = opaque; | |
564 | uint32_t pvr = cpu->env.spr[SPR_PVR]; | |
565 | ||
566 | return (pvr & 0xffff0000) == 0x00200000; | |
567 | } | |
568 | ||
569 | static const VMStateDescription vmstate_pbr403 = { | |
570 | .name = "cpu/pbr403", | |
571 | .version_id = 1, | |
572 | .minimum_version_id = 1, | |
5cd8cada | 573 | .needed = pbr403_needed, |
3aff6c2f | 574 | .fields = (VMStateField[]) { |
a90db158 AK |
575 | VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4), |
576 | VMSTATE_END_OF_LIST() | |
577 | }, | |
578 | }; | |
579 | ||
580 | static const VMStateDescription vmstate_tlbemb = { | |
581 | .name = "cpu/tlb6xx", | |
582 | .version_id = 1, | |
583 | .minimum_version_id = 1, | |
5cd8cada | 584 | .needed = tlbemb_needed, |
3aff6c2f | 585 | .fields = (VMStateField[]) { |
d2164ad3 | 586 | VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), |
a90db158 AK |
587 | VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU, |
588 | env.nb_tlb, | |
589 | vmstate_tlbemb_entry, | |
590 | ppcemb_tlb_t), | |
591 | /* 403 protection registers */ | |
592 | VMSTATE_END_OF_LIST() | |
593 | }, | |
5cd8cada JQ |
594 | .subsections = (const VMStateDescription*[]) { |
595 | &vmstate_pbr403, | |
596 | NULL | |
a90db158 AK |
597 | } |
598 | }; | |
599 | ||
600 | static const VMStateDescription vmstate_tlbmas_entry = { | |
601 | .name = "cpu/tlbmas_entry", | |
602 | .version_id = 1, | |
603 | .minimum_version_id = 1, | |
3aff6c2f | 604 | .fields = (VMStateField[]) { |
a90db158 AK |
605 | VMSTATE_UINT32(mas8, ppcmas_tlb_t), |
606 | VMSTATE_UINT32(mas1, ppcmas_tlb_t), | |
607 | VMSTATE_UINT64(mas2, ppcmas_tlb_t), | |
608 | VMSTATE_UINT64(mas7_3, ppcmas_tlb_t), | |
609 | VMSTATE_END_OF_LIST() | |
610 | }, | |
611 | }; | |
612 | ||
613 | static bool tlbmas_needed(void *opaque) | |
614 | { | |
615 | PowerPCCPU *cpu = opaque; | |
616 | CPUPPCState *env = &cpu->env; | |
617 | ||
618 | return env->nb_tlb && (env->tlb_type == TLB_MAS); | |
619 | } | |
620 | ||
621 | static const VMStateDescription vmstate_tlbmas = { | |
622 | .name = "cpu/tlbmas", | |
623 | .version_id = 1, | |
624 | .minimum_version_id = 1, | |
5cd8cada | 625 | .needed = tlbmas_needed, |
3aff6c2f | 626 | .fields = (VMStateField[]) { |
d2164ad3 | 627 | VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), |
a90db158 AK |
628 | VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU, |
629 | env.nb_tlb, | |
630 | vmstate_tlbmas_entry, | |
631 | ppcmas_tlb_t), | |
632 | VMSTATE_END_OF_LIST() | |
633 | } | |
634 | }; | |
635 | ||
d5fc133e DG |
636 | static bool compat_needed(void *opaque) |
637 | { | |
638 | PowerPCCPU *cpu = opaque; | |
639 | ||
640 | assert(!(cpu->compat_pvr && !cpu->vhyp)); | |
641 | return !cpu->pre_2_10_migration && cpu->compat_pvr != 0; | |
642 | } | |
643 | ||
644 | static const VMStateDescription vmstate_compat = { | |
645 | .name = "cpu/compat", | |
646 | .version_id = 1, | |
647 | .minimum_version_id = 1, | |
648 | .needed = compat_needed, | |
649 | .fields = (VMStateField[]) { | |
650 | VMSTATE_UINT32(compat_pvr, PowerPCCPU), | |
651 | VMSTATE_END_OF_LIST() | |
652 | } | |
653 | }; | |
654 | ||
a90db158 AK |
655 | const VMStateDescription vmstate_ppc_cpu = { |
656 | .name = "cpu", | |
657 | .version_id = 5, | |
658 | .minimum_version_id = 5, | |
659 | .minimum_version_id_old = 4, | |
660 | .load_state_old = cpu_load_old, | |
661 | .pre_save = cpu_pre_save, | |
662 | .post_load = cpu_post_load, | |
3aff6c2f | 663 | .fields = (VMStateField[]) { |
569be9f0 | 664 | VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */ |
a90db158 AK |
665 | |
666 | /* User mode architected state */ | |
667 | VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32), | |
668 | #if !defined(TARGET_PPC64) | |
669 | VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32), | |
670 | #endif | |
671 | VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8), | |
672 | VMSTATE_UINTTL(env.nip, PowerPCCPU), | |
673 | ||
674 | /* SPRs */ | |
675 | VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024), | |
676 | VMSTATE_UINT64(env.spe_acc, PowerPCCPU), | |
677 | ||
678 | /* Reservation */ | |
679 | VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), | |
680 | ||
681 | /* Supervisor mode architected state */ | |
682 | VMSTATE_UINTTL(env.msr, PowerPCCPU), | |
683 | ||
684 | /* Internal state */ | |
685 | VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU), | |
686 | /* FIXME: access_type? */ | |
687 | ||
688 | /* Sanity checking */ | |
146c11f1 DG |
689 | VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration), |
690 | VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration), | |
691 | VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU, | |
692 | cpu_pre_2_8_migration), | |
693 | VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration), | |
a90db158 AK |
694 | VMSTATE_END_OF_LIST() |
695 | }, | |
5cd8cada JQ |
696 | .subsections = (const VMStateDescription*[]) { |
697 | &vmstate_fpu, | |
698 | &vmstate_altivec, | |
699 | &vmstate_vsx, | |
700 | &vmstate_sr, | |
a90db158 | 701 | #ifdef TARGET_PPC64 |
5cd8cada JQ |
702 | &vmstate_tm, |
703 | &vmstate_slb, | |
a90db158 | 704 | #endif /* TARGET_PPC64 */ |
5cd8cada JQ |
705 | &vmstate_tlb6xx, |
706 | &vmstate_tlbemb, | |
707 | &vmstate_tlbmas, | |
d5fc133e | 708 | &vmstate_compat, |
5cd8cada | 709 | NULL |
a90db158 AK |
710 | } |
711 | }; |