[mirror_qemu.git] / target / ppc / mem_helper.c

/*
 *  PowerPC memory access emulation helpers for QEMU.
 *
 *  Copyright (c) 2003-2007 Jocelyn Mayer
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "qemu/host-utils.h"
#include "exec/helper-proto.h"
#include "helper_regs.h"
#include "exec/cpu_ldst.h"
#include "tcg.h"
#include "internal.h"
#include "qemu/atomic128.h"

/* #define DEBUG_OP */

static inline bool needs_byteswap(const CPUPPCState *env)
{
#if defined(TARGET_WORDS_BIGENDIAN)
  return msr_le;
#else
  return !msr_le;
#endif
}

/*****************************************************************************/
/* Memory load and stores */

static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr,
                                    target_long arg)
{
#if defined(TARGET_PPC64)
    if (!msr_is_64bit(env, env->msr)) {
        return (uint32_t)(addr + arg);
    } else
#endif
    {
        return addr + arg;
    }
}

void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
{
    for (; reg < 32; reg++) {
        if (needs_byteswap(env)) {
            env->gpr[reg] = bswap32(cpu_ldl_data_ra(env, addr, GETPC()));
        } else {
            env->gpr[reg] = cpu_ldl_data_ra(env, addr, GETPC());
        }
        addr = addr_add(env, addr, 4);
    }
}

void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
{
    for (; reg < 32; reg++) {
        if (needs_byteswap(env)) {
            cpu_stl_data_ra(env, addr, bswap32((uint32_t)env->gpr[reg]),
                                                   GETPC());
        } else {
            cpu_stl_data_ra(env, addr, (uint32_t)env->gpr[reg], GETPC());
        }
        addr = addr_add(env, addr, 4);
    }
}

static void do_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
                   uint32_t reg, uintptr_t raddr)
{
    int sh;

    for (; nb > 3; nb -= 4) {
        env->gpr[reg] = cpu_ldl_data_ra(env, addr, raddr);
        reg = (reg + 1) % 32;
        addr = addr_add(env, addr, 4);
    }
    if (unlikely(nb > 0)) {
        env->gpr[reg] = 0;
        for (sh = 24; nb > 0; nb--, sh -= 8) {
            env->gpr[reg] |= cpu_ldub_data_ra(env, addr, raddr) << sh;
            addr = addr_add(env, addr, 1);
        }
    }
}

void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg)
{
    do_lsw(env, addr, nb, reg, GETPC());
}

/*
 * PPC32 specification says we must generate an exception if rA is in
 * the range of registers to be loaded.  In an other hand, IBM says
 * this is valid, but rA won't be loaded.  For now, I'll follow the
 * spec...
 */
void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,
                 uint32_t ra, uint32_t rb)
{
    if (likely(xer_bc != 0)) {
        int num_used_regs = DIV_ROUND_UP(xer_bc, 4);
        if (unlikely((ra != 0 && lsw_reg_in_range(reg, num_used_regs, ra)) ||
                     lsw_reg_in_range(reg, num_used_regs, rb))) {
            raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
                                   POWERPC_EXCP_INVAL |
                                   POWERPC_EXCP_INVAL_LSWX, GETPC());
        } else {
            do_lsw(env, addr, xer_bc, reg, GETPC());
        }
    }
}

void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
                 uint32_t reg)
{
    int sh;

    for (; nb > 3; nb -= 4) {
        cpu_stl_data_ra(env, addr, env->gpr[reg], GETPC());
        reg = (reg + 1) % 32;
        addr = addr_add(env, addr, 4);
    }
    if (unlikely(nb > 0)) {
        for (sh = 24; nb > 0; nb--, sh -= 8) {
            cpu_stb_data_ra(env, addr, (env->gpr[reg] >> sh) & 0xFF, GETPC());
            addr = addr_add(env, addr, 1);
        }
    }
}

static void dcbz_common(CPUPPCState *env, target_ulong addr,
                        uint32_t opcode, bool epid, uintptr_t retaddr)
{
    target_ulong mask, dcbz_size = env->dcache_line_size;
    uint32_t i;
    void *haddr;
    int mmu_idx = epid ? PPC_TLB_EPID_STORE : env->dmmu_idx;

#if defined(TARGET_PPC64)
    /* Check for dcbz vs dcbzl on 970 */
    if (env->excp_model == POWERPC_EXCP_970 &&
        !(opcode & 0x00200000) && ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) {
        dcbz_size = 32;
    }
#endif

    /* Align address */
    mask = ~(dcbz_size - 1);
    addr &= mask;

    /* Check reservation */
    if ((env->reserve_addr & mask) == (addr & mask))  {
        env->reserve_addr = (target_ulong)-1ULL;
    }

    /* Try fast path translate */
    haddr = tlb_vaddr_to_host(env, addr, MMU_DATA_STORE, mmu_idx);
    if (haddr) {
        memset(haddr, 0, dcbz_size);
    } else {
        /* Slow path */
        for (i = 0; i < dcbz_size; i += 8) {
            if (epid) {
#if !defined(CONFIG_USER_ONLY)
                /* Does not make sense on USER_ONLY config */
                cpu_stq_eps_ra(env, addr + i, 0, retaddr);
#endif
            } else {
                cpu_stq_data_ra(env, addr + i, 0, retaddr);
            }
        }
    }
}

void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t opcode)
{
    dcbz_common(env, addr, opcode, false, GETPC());
}

void helper_dcbzep(CPUPPCState *env, target_ulong addr, uint32_t opcode)
{
    dcbz_common(env, addr, opcode, true, GETPC());
}

void helper_icbi(CPUPPCState *env, target_ulong addr)
{
    addr &= ~(env->dcache_line_size - 1);
    /*
     * Invalidate one cache line :
     * PowerPC specification says this is to be treated like a load
     * (not a fetch) by the MMU. To be sure it will be so,
     * do the load "by hand".
     */
    cpu_ldl_data_ra(env, addr, GETPC());
}

void helper_icbiep(CPUPPCState *env, target_ulong addr)
{
#if !defined(CONFIG_USER_ONLY)
    /* See comments above */
    addr &= ~(env->dcache_line_size - 1);
    cpu_ldl_epl_ra(env, addr, GETPC());
#endif
}

/* XXX: to be tested */
target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
                          uint32_t ra, uint32_t rb)
{
    int i, c, d;

    d = 24;
    for (i = 0; i < xer_bc; i++) {
        c = cpu_ldub_data_ra(env, addr, GETPC());
        addr = addr_add(env, addr, 1);
        /* ra (if not 0) and rb are never modified */
        if (likely(reg != rb && (ra == 0 || reg != ra))) {
            env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
        }
        if (unlikely(c == xer_cmp)) {
            break;
        }
        if (likely(d != 0)) {
            d -= 8;
        } else {
            d = 24;
            reg++;
            reg = reg & 0x1F;
        }
    }
    return i;
}

#ifdef TARGET_PPC64
uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr,
                               uint32_t opidx)
{
    Int128 ret;

    /* We will have raised EXCP_ATOMIC from the translator.  */
    assert(HAVE_ATOMIC128);
    ret = helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC());
    env->retxh = int128_gethi(ret);
    return int128_getlo(ret);
}

uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr,
                               uint32_t opidx)
{
    Int128 ret;

    /* We will have raised EXCP_ATOMIC from the translator.  */
    assert(HAVE_ATOMIC128);
    ret = helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC());
    env->retxh = int128_gethi(ret);
    return int128_getlo(ret);
}

void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr,
                            uint64_t lo, uint64_t hi, uint32_t opidx)
{
    Int128 val;

    /* We will have raised EXCP_ATOMIC from the translator.  */
    assert(HAVE_ATOMIC128);
    val = int128_make128(lo, hi);
    helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC());
}

void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr,
                            uint64_t lo, uint64_t hi, uint32_t opidx)
{
    Int128 val;

    /* We will have raised EXCP_ATOMIC from the translator.  */
    assert(HAVE_ATOMIC128);
    val = int128_make128(lo, hi);
    helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC());
}

uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr,
                                  uint64_t new_lo, uint64_t new_hi,
                                  uint32_t opidx)
{
    bool success = false;

    /* We will have raised EXCP_ATOMIC from the translator.  */
    assert(HAVE_CMPXCHG128);

    if (likely(addr == env->reserve_addr)) {
        Int128 oldv, cmpv, newv;

        cmpv = int128_make128(env->reserve_val2, env->reserve_val);
        newv = int128_make128(new_lo, new_hi);
        oldv = helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv,
                                             opidx, GETPC());
        success = int128_eq(oldv, cmpv);
    }
    env->reserve_addr = -1;
    return env->so + success * CRF_EQ_BIT;
}

uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr,
                                  uint64_t new_lo, uint64_t new_hi,
                                  uint32_t opidx)
{
    bool success = false;

    /* We will have raised EXCP_ATOMIC from the translator.  */
    assert(HAVE_CMPXCHG128);

    if (likely(addr == env->reserve_addr)) {
        Int128 oldv, cmpv, newv;

        cmpv = int128_make128(env->reserve_val2, env->reserve_val);
        newv = int128_make128(new_lo, new_hi);
        oldv = helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv,
                                             opidx, GETPC());
        success = int128_eq(oldv, cmpv);
    }
    env->reserve_addr = -1;
    return env->so + success * CRF_EQ_BIT;
}
#endif

/*****************************************************************************/
/* Altivec extension helpers */
#if defined(HOST_WORDS_BIGENDIAN)
#define HI_IDX 0
#define LO_IDX 1
#else
#define HI_IDX 1
#define LO_IDX 0
#endif

/*
 * We use msr_le to determine index ordering in a vector.  However,
 * byteswapping is not simply controlled by msr_le.  We also need to
 * take into account endianness of the target.  This is done for the
 * little-endian PPC64 user-mode target.
 */

#define LVE(name, access, swap, element)                        \
    void helper_##name(CPUPPCState *env, ppc_avr_t *r,          \
                       target_ulong addr)                       \
    {                                                           \
        size_t n_elems = ARRAY_SIZE(r->element);                \
        int adjust = HI_IDX * (n_elems - 1);                    \
        int sh = sizeof(r->element[0]) >> 1;                    \
        int index = (addr & 0xf) >> sh;                         \
        if (msr_le) {                                           \
            index = n_elems - index - 1;                        \
        }                                                       \
                                                                \
        if (needs_byteswap(env)) {                              \
            r->element[LO_IDX ? index : (adjust - index)] =     \
                swap(access(env, addr, GETPC()));               \
        } else {                                                \
            r->element[LO_IDX ? index : (adjust - index)] =     \
                access(env, addr, GETPC());                     \
        }                                                       \
    }
#define I(x) (x)
LVE(lvebx, cpu_ldub_data_ra, I, u8)
LVE(lvehx, cpu_lduw_data_ra, bswap16, u16)
LVE(lvewx, cpu_ldl_data_ra, bswap32, u32)
#undef I
#undef LVE

#define STVE(name, access, swap, element)                               \
    void helper_##name(CPUPPCState *env, ppc_avr_t *r,                  \
                       target_ulong addr)                               \
    {                                                                   \
        size_t n_elems = ARRAY_SIZE(r->element);                        \
        int adjust = HI_IDX * (n_elems - 1);                            \
        int sh = sizeof(r->element[0]) >> 1;                            \
        int index = (addr & 0xf) >> sh;                                 \
        if (msr_le) {                                                   \
            index = n_elems - index - 1;                                \
        }                                                               \
                                                                        \
        if (needs_byteswap(env)) {                                      \
            access(env, addr, swap(r->element[LO_IDX ? index :          \
                                              (adjust - index)]),       \
                        GETPC());                                       \
        } else {                                                        \
            access(env, addr, r->element[LO_IDX ? index :               \
                                         (adjust - index)], GETPC());   \
        }                                                               \
    }
#define I(x) (x)
STVE(stvebx, cpu_stb_data_ra, I, u8)
STVE(stvehx, cpu_stw_data_ra, bswap16, u16)
STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
#undef I
#undef LVE

#ifdef TARGET_PPC64
#define GET_NB(rb) ((rb >> 56) & 0xFF)

#define VSX_LXVL(name, lj)                                              \
void helper_##name(CPUPPCState *env, target_ulong addr,                 \
                   ppc_vsr_t *xt, target_ulong rb)                      \
{                                                                       \
    ppc_vsr_t t;                                                        \
    uint64_t nb = GET_NB(rb);                                           \
    int i;                                                              \
                                                                        \
    t.s128 = int128_zero();                                             \
    if (nb) {                                                           \
        nb = (nb >= 16) ? 16 : nb;                                      \
        if (msr_le && !lj) {                                            \
            for (i = 16; i > 16 - nb; i--) {                            \
                t.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC());   \
                addr = addr_add(env, addr, 1);                          \
            }                                                           \
        } else {                                                        \
            for (i = 0; i < nb; i++) {                                  \
                t.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC());       \
                addr = addr_add(env, addr, 1);                          \
            }                                                           \
        }                                                               \
    }                                                                   \
    *xt = t;                                                            \
}

VSX_LXVL(lxvl, 0)
VSX_LXVL(lxvll, 1)
#undef VSX_LXVL

#define VSX_STXVL(name, lj)                                       \
void helper_##name(CPUPPCState *env, target_ulong addr,           \
                   ppc_vsr_t *xt, target_ulong rb)                \
{                                                                 \
    target_ulong nb = GET_NB(rb);                                 \
    int i;                                                        \
                                                                  \
    if (!nb) {                                                    \
        return;                                                   \
    }                                                             \
                                                                  \
    nb = (nb >= 16) ? 16 : nb;                                    \
    if (msr_le && !lj) {                                          \
        for (i = 16; i > 16 - nb; i--) {                          \
            cpu_stb_data_ra(env, addr, xt->VsrB(i - 1), GETPC()); \
            addr = addr_add(env, addr, 1);                        \
        }                                                         \
    } else {                                                      \
        for (i = 0; i < nb; i++) {                                \
            cpu_stb_data_ra(env, addr, xt->VsrB(i), GETPC());     \
            addr = addr_add(env, addr, 1);                        \
        }                                                         \
    }                                                             \
}

VSX_STXVL(stxvl, 0)
VSX_STXVL(stxvll, 1)
#undef VSX_STXVL
#undef GET_NB
#endif /* TARGET_PPC64 */

#undef HI_IDX
#undef LO_IDX

void helper_tbegin(CPUPPCState *env)
{
    /*
     * As a degenerate implementation, always fail tbegin.  The reason
     * given is "Nesting overflow".  The "persistent" bit is set,
     * providing a hint to the error handler to not retry.  The TFIAR
     * captures the address of the failure, which is this tbegin
     * instruction.  Instruction execution will continue with the next
     * instruction in memory, which is precisely what we want.
     */

    env->spr[SPR_TEXASR] =
        (1ULL << TEXASR_FAILURE_PERSISTENT) |
        (1ULL << TEXASR_NESTING_OVERFLOW) |
        (msr_hv << TEXASR_PRIVILEGE_HV) |
        (msr_pr << TEXASR_PRIVILEGE_PR) |
        (1ULL << TEXASR_FAILURE_SUMMARY) |
        (1ULL << TEXASR_TFIAR_EXACT);
    env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) | msr_pr;
    env->spr[SPR_TFHAR] = env->nip + 4;
    env->crf[0] = 0xB; /* 0b1010 = transaction failure */
}
Commit	Line	Data
9a64fbe4	1	/*
2f5a189c	2	* PowerPC memory access emulation helpers for QEMU.
5fafdf24	3	*
76a66253	4	* Copyright (c) 2003-2007 Jocelyn Mayer
9a64fbe4 FB	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
9a64fbe4	18	*/
0d75590d	19	#include "qemu/osdep.h"
3e457172	20	#include "cpu.h"
63c91552	21	#include "exec/exec-all.h"
1de7afc9	22	#include "qemu/host-utils.h"
2ef6175a	23	#include "exec/helper-proto.h"
0411a972	24	#include "helper_regs.h"
f08b6170	25	#include "exec/cpu_ldst.h"
94bf2658	26	#include "tcg.h"
6914bc4f	27	#include "internal.h"
f34ec0f6	28	#include "qemu/atomic128.h"
3e457172	29
5a2c8b9e	30	/* #define DEBUG_OP */
d12d51d5	31
e22c357b DK	32	static inline bool needs_byteswap(const CPUPPCState *env)
	33	{
	34	#if defined(TARGET_WORDS_BIGENDIAN)
	35	return msr_le;
	36	#else
	37	return !msr_le;
	38	#endif
	39	}
	40
ff4a62cd AJ	41	/*****************************************************************************/
	42	/* Memory load and stores */
	43
2f5a189c BS	44	static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr,
2f5a189c BS	45	target_long arg)
ff4a62cd AJ	46	{
ff4a62cd AJ	47	#if defined(TARGET_PPC64)
e42a61f1	48	if (!msr_is_64bit(env, env->msr)) {
b327c654 BS	49	return (uint32_t)(addr + arg);
b327c654 BS	50	} else
ff4a62cd	51	#endif
b327c654 BS	52	{
	53	return addr + arg;
	54	}
ff4a62cd AJ	55	}
ff4a62cd AJ	56
2f5a189c	57	void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
ff4a62cd	58	{
76db3ba4	59	for (; reg < 32; reg++) {
e22c357b	60	if (needs_byteswap(env)) {
af6d376e	61	env->gpr[reg] = bswap32(cpu_ldl_data_ra(env, addr, GETPC()));
b327c654	62	} else {
af6d376e	63	env->gpr[reg] = cpu_ldl_data_ra(env, addr, GETPC());
b327c654	64	}
2f5a189c	65	addr = addr_add(env, addr, 4);
ff4a62cd AJ	66	}
	67	}
	68
2f5a189c	69	void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
ff4a62cd	70	{
76db3ba4	71	for (; reg < 32; reg++) {
e22c357b	72	if (needs_byteswap(env)) {
af6d376e BH	73	cpu_stl_data_ra(env, addr, bswap32((uint32_t)env->gpr[reg]),
af6d376e BH	74	GETPC());
b327c654	75	} else {
af6d376e	76	cpu_stl_data_ra(env, addr, (uint32_t)env->gpr[reg], GETPC());
b327c654	77	}
2f5a189c	78	addr = addr_add(env, addr, 4);
ff4a62cd AJ	79	}
	80	}
	81
e41029b3 BH	82	static void do_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
e41029b3 BH	83	uint32_t reg, uintptr_t raddr)
dfbc799d AJ	84	{
dfbc799d AJ	85	int sh;
b327c654	86
76db3ba4	87	for (; nb > 3; nb -= 4) {
e41029b3	88	env->gpr[reg] = cpu_ldl_data_ra(env, addr, raddr);
dfbc799d	89	reg = (reg + 1) % 32;
2f5a189c	90	addr = addr_add(env, addr, 4);
dfbc799d AJ	91	}
	92	if (unlikely(nb > 0)) {
	93	env->gpr[reg] = 0;
76db3ba4	94	for (sh = 24; nb > 0; nb--, sh -= 8) {
e41029b3	95	env->gpr[reg] \|= cpu_ldub_data_ra(env, addr, raddr) << sh;
2f5a189c	96	addr = addr_add(env, addr, 1);
dfbc799d AJ	97	}
	98	}
	99	}
e41029b3 BH	100
	101	void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg)
	102	{
	103	do_lsw(env, addr, nb, reg, GETPC());
	104	}
	105
5a2c8b9e DG	106	/*
	107	* PPC32 specification says we must generate an exception if rA is in
	108	* the range of registers to be loaded. In an other hand, IBM says
	109	* this is valid, but rA won't be loaded. For now, I'll follow the
	110	* spec...
dfbc799d	111	*/
2f5a189c BS	112	void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,
2f5a189c BS	113	uint32_t ra, uint32_t rb)
dfbc799d AJ	114	{
dfbc799d AJ	115	if (likely(xer_bc != 0)) {
f0704d78	116	int num_used_regs = DIV_ROUND_UP(xer_bc, 4);
537d3e8e TH	117	if (unlikely((ra != 0 && lsw_reg_in_range(reg, num_used_regs, ra)) \|\|
537d3e8e TH	118	lsw_reg_in_range(reg, num_used_regs, rb))) {
e41029b3 BH	119	raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
	120	POWERPC_EXCP_INVAL \|
	121	POWERPC_EXCP_INVAL_LSWX, GETPC());
dfbc799d	122	} else {
e41029b3	123	do_lsw(env, addr, xer_bc, reg, GETPC());
dfbc799d AJ	124	}
	125	}
	126	}
	127
2f5a189c BS	128	void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
2f5a189c BS	129	uint32_t reg)
dfbc799d AJ	130	{
dfbc799d AJ	131	int sh;
b327c654	132
76db3ba4	133	for (; nb > 3; nb -= 4) {
e41029b3	134	cpu_stl_data_ra(env, addr, env->gpr[reg], GETPC());
dfbc799d	135	reg = (reg + 1) % 32;
2f5a189c	136	addr = addr_add(env, addr, 4);
dfbc799d AJ	137	}
dfbc799d AJ	138	if (unlikely(nb > 0)) {
a16b45e7	139	for (sh = 24; nb > 0; nb--, sh -= 8) {
e41029b3	140	cpu_stb_data_ra(env, addr, (env->gpr[reg] >> sh) & 0xFF, GETPC());
2f5a189c	141	addr = addr_add(env, addr, 1);
a16b45e7	142	}
dfbc799d AJ	143	}
	144	}
	145
50728199 RK	146	static void dcbz_common(CPUPPCState *env, target_ulong addr,
50728199 RK	147	uint32_t opcode, bool epid, uintptr_t retaddr)
799a8c8d	148	{
c9f82d01 BH	149	target_ulong mask, dcbz_size = env->dcache_line_size;
	150	uint32_t i;
	151	void *haddr;
50728199	152	int mmu_idx = epid ? PPC_TLB_EPID_STORE : env->dmmu_idx;
799a8c8d	153
414f5d14	154	#if defined(TARGET_PPC64)
c9f82d01 BH	155	/* Check for dcbz vs dcbzl on 970 */
	156	if (env->excp_model == POWERPC_EXCP_970 &&
	157	!(opcode & 0x00200000) && ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) {
8e33944f	158	dcbz_size = 32;
b327c654	159	}
8e33944f AG	160	#endif
8e33944f AG	161
c9f82d01 BH	162	/* Align address */
	163	mask = ~(dcbz_size - 1);
	164	addr &= mask;
	165
	166	/* Check reservation */
	167	if ((env->reserve_addr & mask) == (addr & mask)) {
	168	env->reserve_addr = (target_ulong)-1ULL;
	169	}
8e33944f	170
c9f82d01	171	/* Try fast path translate */
50728199	172	haddr = tlb_vaddr_to_host(env, addr, MMU_DATA_STORE, mmu_idx);
c9f82d01 BH	173	if (haddr) {
	174	memset(haddr, 0, dcbz_size);
	175	} else {
	176	/* Slow path */
	177	for (i = 0; i < dcbz_size; i += 8) {
50728199 RK	178	if (epid) {
	179	#if !defined(CONFIG_USER_ONLY)
	180	/* Does not make sense on USER_ONLY config */
	181	cpu_stq_eps_ra(env, addr + i, 0, retaddr);
	182	#endif
	183	} else {
	184	cpu_stq_data_ra(env, addr + i, 0, retaddr);
	185	}
c9f82d01 BH	186	}
c9f82d01 BH	187	}
799a8c8d AJ	188	}
799a8c8d AJ	189
50728199 RK	190	void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t opcode)
	191	{
	192	dcbz_common(env, addr, opcode, false, GETPC());
	193	}
	194
	195	void helper_dcbzep(CPUPPCState *env, target_ulong addr, uint32_t opcode)
	196	{
	197	dcbz_common(env, addr, opcode, true, GETPC());
	198	}
	199
2f5a189c	200	void helper_icbi(CPUPPCState *env, target_ulong addr)
37d269df	201	{
76db3ba4	202	addr &= ~(env->dcache_line_size - 1);
5a2c8b9e DG	203	/*
5a2c8b9e DG	204	* Invalidate one cache line :
37d269df AJ	205	* PowerPC specification says this is to be treated like a load
	206	* (not a fetch) by the MMU. To be sure it will be so,
	207	* do the load "by hand".
	208	*/
af6d376e	209	cpu_ldl_data_ra(env, addr, GETPC());
37d269df AJ	210	}
37d269df AJ	211
50728199 RK	212	void helper_icbiep(CPUPPCState *env, target_ulong addr)
	213	{
	214	#if !defined(CONFIG_USER_ONLY)
	215	/* See comments above */
	216	addr &= ~(env->dcache_line_size - 1);
	217	cpu_ldl_epl_ra(env, addr, GETPC());
	218	#endif
	219	}
	220
b327c654	221	/* XXX: to be tested */
2f5a189c BS	222	target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
2f5a189c BS	223	uint32_t ra, uint32_t rb)
bdb4b689 AJ	224	{
bdb4b689 AJ	225	int i, c, d;
b327c654	226
bdb4b689 AJ	227	d = 24;
bdb4b689 AJ	228	for (i = 0; i < xer_bc; i++) {
b00a3b36	229	c = cpu_ldub_data_ra(env, addr, GETPC());
2f5a189c	230	addr = addr_add(env, addr, 1);
bdb4b689 AJ	231	/* ra (if not 0) and rb are never modified */
	232	if (likely(reg != rb && (ra == 0 \|\| reg != ra))) {
	233	env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) \| (c << d);
	234	}
b327c654	235	if (unlikely(c == xer_cmp)) {
bdb4b689	236	break;
b327c654	237	}
bdb4b689 AJ	238	if (likely(d != 0)) {
	239	d -= 8;
	240	} else {
	241	d = 24;
	242	reg++;
	243	reg = reg & 0x1F;
	244	}
	245	}
	246	return i;
	247	}
	248
f34ec0f6	249	#ifdef TARGET_PPC64
94bf2658 RH	250	uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr,
	251	uint32_t opidx)
	252	{
f34ec0f6 RH	253	Int128 ret;
	254
	255	/* We will have raised EXCP_ATOMIC from the translator. */
	256	assert(HAVE_ATOMIC128);
	257	ret = helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC());
94bf2658 RH	258	env->retxh = int128_gethi(ret);
	259	return int128_getlo(ret);
	260	}
	261
	262	uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr,
	263	uint32_t opidx)
	264	{
f34ec0f6 RH	265	Int128 ret;
	266
	267	/* We will have raised EXCP_ATOMIC from the translator. */
	268	assert(HAVE_ATOMIC128);
	269	ret = helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC());
94bf2658 RH	270	env->retxh = int128_gethi(ret);
	271	return int128_getlo(ret);
	272	}
f89ced5f RH	273
	274	void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr,
	275	uint64_t lo, uint64_t hi, uint32_t opidx)
	276	{
f34ec0f6 RH	277	Int128 val;
	278
	279	/* We will have raised EXCP_ATOMIC from the translator. */
	280	assert(HAVE_ATOMIC128);
	281	val = int128_make128(lo, hi);
f89ced5f RH	282	helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC());
	283	}
	284
	285	void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr,
	286	uint64_t lo, uint64_t hi, uint32_t opidx)
	287	{
f34ec0f6 RH	288	Int128 val;
	289
	290	/* We will have raised EXCP_ATOMIC from the translator. */
	291	assert(HAVE_ATOMIC128);
	292	val = int128_make128(lo, hi);
f89ced5f RH	293	helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC());
f89ced5f RH	294	}
4a9b3c5d RH	295
	296	uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr,
	297	uint64_t new_lo, uint64_t new_hi,
	298	uint32_t opidx)
	299	{
	300	bool success = false;
	301
f34ec0f6 RH	302	/* We will have raised EXCP_ATOMIC from the translator. */
	303	assert(HAVE_CMPXCHG128);
	304
4a9b3c5d RH	305	if (likely(addr == env->reserve_addr)) {
	306	Int128 oldv, cmpv, newv;
	307
	308	cmpv = int128_make128(env->reserve_val2, env->reserve_val);
	309	newv = int128_make128(new_lo, new_hi);
	310	oldv = helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv,
	311	opidx, GETPC());
	312	success = int128_eq(oldv, cmpv);
	313	}
	314	env->reserve_addr = -1;
	315	return env->so + success * CRF_EQ_BIT;
	316	}
	317
	318	uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr,
	319	uint64_t new_lo, uint64_t new_hi,
	320	uint32_t opidx)
	321	{
	322	bool success = false;
	323
f34ec0f6 RH	324	/* We will have raised EXCP_ATOMIC from the translator. */
	325	assert(HAVE_CMPXCHG128);
	326
4a9b3c5d RH	327	if (likely(addr == env->reserve_addr)) {
	328	Int128 oldv, cmpv, newv;
	329
	330	cmpv = int128_make128(env->reserve_val2, env->reserve_val);
	331	newv = int128_make128(new_lo, new_hi);
	332	oldv = helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv,
	333	opidx, GETPC());
	334	success = int128_eq(oldv, cmpv);
	335	}
	336	env->reserve_addr = -1;
	337	return env->so + success * CRF_EQ_BIT;
	338	}
94bf2658 RH	339	#endif
94bf2658 RH	340
d6a46fe8 AJ	341	/*****************************************************************************/
d6a46fe8 AJ	342	/* Altivec extension helpers */
e2542fe2	343	#if defined(HOST_WORDS_BIGENDIAN)
d6a46fe8 AJ	344	#define HI_IDX 0
	345	#define LO_IDX 1
	346	#else
	347	#define HI_IDX 1
	348	#define LO_IDX 0
	349	#endif
	350
5a2c8b9e DG	351	/*
	352	* We use msr_le to determine index ordering in a vector. However,
	353	* byteswapping is not simply controlled by msr_le. We also need to
	354	* take into account endianness of the target. This is done for the
	355	* little-endian PPC64 user-mode target.
	356	*/
e22c357b	357
cbfb6ae9	358	#define LVE(name, access, swap, element) \
2f5a189c BS	359	void helper_##name(CPUPPCState env, ppc_avr_t r, \
2f5a189c BS	360	target_ulong addr) \
cbfb6ae9 AJ	361	{ \
cbfb6ae9 AJ	362	size_t n_elems = ARRAY_SIZE(r->element); \
5a2c8b9e	363	int adjust = HI_IDX * (n_elems - 1); \
cbfb6ae9 AJ	364	int sh = sizeof(r->element[0]) >> 1; \
cbfb6ae9 AJ	365	int index = (addr & 0xf) >> sh; \
b327c654	366	if (msr_le) { \
bbfb6f13	367	index = n_elems - index - 1; \
e22c357b DK	368	} \
	369	\
	370	if (needs_byteswap(env)) { \
b327c654	371	r->element[LO_IDX ? index : (adjust - index)] = \
bcd510b1	372	swap(access(env, addr, GETPC())); \
b327c654 BS	373	} else { \
b327c654 BS	374	r->element[LO_IDX ? index : (adjust - index)] = \
bcd510b1	375	access(env, addr, GETPC()); \
b327c654	376	} \
cbfb6ae9 AJ	377	}
cbfb6ae9 AJ	378	#define I(x) (x)
bcd510b1 BH	379	LVE(lvebx, cpu_ldub_data_ra, I, u8)
	380	LVE(lvehx, cpu_lduw_data_ra, bswap16, u16)
	381	LVE(lvewx, cpu_ldl_data_ra, bswap32, u32)
cbfb6ae9 AJ	382	#undef I
	383	#undef LVE
	384
b327c654	385	#define STVE(name, access, swap, element) \
2f5a189c BS	386	void helper_##name(CPUPPCState env, ppc_avr_t r, \
2f5a189c BS	387	target_ulong addr) \
b327c654 BS	388	{ \
	389	size_t n_elems = ARRAY_SIZE(r->element); \
	390	int adjust = HI_IDX * (n_elems - 1); \
	391	int sh = sizeof(r->element[0]) >> 1; \
	392	int index = (addr & 0xf) >> sh; \
b327c654	393	if (msr_le) { \
bbfb6f13	394	index = n_elems - index - 1; \
e22c357b DK	395	} \
	396	\
	397	if (needs_byteswap(env)) { \
2f5a189c	398	access(env, addr, swap(r->element[LO_IDX ? index : \
bcd510b1 BH	399	(adjust - index)]), \
bcd510b1 BH	400	GETPC()); \
cbfb6ae9	401	} else { \
2f5a189c	402	access(env, addr, r->element[LO_IDX ? index : \
bcd510b1	403	(adjust - index)], GETPC()); \
cbfb6ae9 AJ	404	} \
	405	}
	406	#define I(x) (x)
bcd510b1 BH	407	STVE(stvebx, cpu_stb_data_ra, I, u8)
	408	STVE(stvehx, cpu_stw_data_ra, bswap16, u16)
	409	STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
cbfb6ae9 AJ	410	#undef I
	411	#undef LVE
	412
6914bc4f ND	413	#ifdef TARGET_PPC64
	414	#define GET_NB(rb) ((rb >> 56) & 0xFF)
	415
	416	#define VSX_LXVL(name, lj) \
	417	void helper_##name(CPUPPCState *env, target_ulong addr, \
2aba168e	418	ppc_vsr_t *xt, target_ulong rb) \
6914bc4f	419	{ \
2a175830	420	ppc_vsr_t t; \
6914bc4f	421	uint64_t nb = GET_NB(rb); \
2a175830	422	int i; \
6914bc4f	423	\
2a175830	424	t.s128 = int128_zero(); \
6914bc4f ND	425	if (nb) { \
	426	nb = (nb >= 16) ? 16 : nb; \
	427	if (msr_le && !lj) { \
	428	for (i = 16; i > 16 - nb; i--) { \
2a175830	429	t.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC()); \
6914bc4f ND	430	addr = addr_add(env, addr, 1); \
	431	} \
	432	} else { \
	433	for (i = 0; i < nb; i++) { \
2a175830	434	t.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC()); \
6914bc4f ND	435	addr = addr_add(env, addr, 1); \
	436	} \
	437	} \
	438	} \
2a175830	439	*xt = t; \
6914bc4f ND	440	}
	441
	442	VSX_LXVL(lxvl, 0)
176e44e7	443	VSX_LXVL(lxvll, 1)
6914bc4f	444	#undef VSX_LXVL
681c2478 ND	445
	446	#define VSX_STXVL(name, lj) \
	447	void helper_##name(CPUPPCState *env, target_ulong addr, \
2aba168e	448	ppc_vsr_t *xt, target_ulong rb) \
681c2478	449	{ \
681c2478	450	target_ulong nb = GET_NB(rb); \
2a175830	451	int i; \
681c2478 ND	452	\
	453	if (!nb) { \
	454	return; \
	455	} \
2a175830	456	\
681c2478 ND	457	nb = (nb >= 16) ? 16 : nb; \
	458	if (msr_le && !lj) { \
	459	for (i = 16; i > 16 - nb; i--) { \
2a175830	460	cpu_stb_data_ra(env, addr, xt->VsrB(i - 1), GETPC()); \
681c2478 ND	461	addr = addr_add(env, addr, 1); \
	462	} \
	463	} else { \
	464	for (i = 0; i < nb; i++) { \
2a175830	465	cpu_stb_data_ra(env, addr, xt->VsrB(i), GETPC()); \
681c2478 ND	466	addr = addr_add(env, addr, 1); \
	467	} \
	468	} \
	469	}
	470
	471	VSX_STXVL(stxvl, 0)
e122090d	472	VSX_STXVL(stxvll, 1)
681c2478	473	#undef VSX_STXVL
6914bc4f ND	474	#undef GET_NB
	475	#endif /* TARGET_PPC64 */
	476
d6a46fe8 AJ	477	#undef HI_IDX
d6a46fe8 AJ	478	#undef LO_IDX
0ff93d11 TM	479
	480	void helper_tbegin(CPUPPCState *env)
	481	{
5a2c8b9e DG	482	/*
5a2c8b9e DG	483	* As a degenerate implementation, always fail tbegin. The reason
0ff93d11 TM	484	* given is "Nesting overflow". The "persistent" bit is set,
	485	* providing a hint to the error handler to not retry. The TFIAR
	486	* captures the address of the failure, which is this tbegin
5a2c8b9e DG	487	* instruction. Instruction execution will continue with the next
5a2c8b9e DG	488	* instruction in memory, which is precisely what we want.
0ff93d11 TM	489	*/
	490
	491	env->spr[SPR_TEXASR] =
	492	(1ULL << TEXASR_FAILURE_PERSISTENT) \|
	493	(1ULL << TEXASR_NESTING_OVERFLOW) \|
	494	(msr_hv << TEXASR_PRIVILEGE_HV) \|
	495	(msr_pr << TEXASR_PRIVILEGE_PR) \|
	496	(1ULL << TEXASR_FAILURE_SUMMARY) \|
	497	(1ULL << TEXASR_TFIAR_EXACT);
	498	env->spr[SPR_TFIAR] = env->nip \| (msr_hv << 1) \| msr_pr;
	499	env->spr[SPR_TFHAR] = env->nip + 4;
	500	env->crf[0] = 0xB; /* 0b1010 = transaction failure */
	501	}