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Merge remote-tracking branch 'remotes/cminyard/tags/for-qemu-i2c-5' into staging
[mirror_qemu.git] / target / riscv / insn_trans / trans_rvv.inc.c
CommitLineData
2b7168fc
LZ		 1/*
2 * RISC-V translation routines for the RVV Standard Extension.
3 *
4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
751538d5
LZ		 18#include "tcg/tcg-op-gvec.h"
19#include "tcg/tcg-gvec-desc.h"
20#include "internals.h"
2b7168fc
LZ		 21
22static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
23{
24 TCGv s1, s2, dst;
25
26 if (!has_ext(ctx, RVV)) {
27 return false;
28 }
29
30 s2 = tcg_temp_new();
31 dst = tcg_temp_new();
32
33 /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
34 if (a->rs1 == 0) {
35 /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
36 s1 = tcg_const_tl(RV_VLEN_MAX);
37 } else {
38 s1 = tcg_temp_new();
39 gen_get_gpr(s1, a->rs1);
40 }
41 gen_get_gpr(s2, a->rs2);
42 gen_helper_vsetvl(dst, cpu_env, s1, s2);
43 gen_set_gpr(a->rd, dst);
44 tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
45 lookup_and_goto_ptr(ctx);
46 ctx->base.is_jmp = DISAS_NORETURN;
47
48 tcg_temp_free(s1);
49 tcg_temp_free(s2);
50 tcg_temp_free(dst);
51 return true;
52}
53
54static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
55{
56 TCGv s1, s2, dst;
57
58 if (!has_ext(ctx, RVV)) {
59 return false;
60 }
61
62 s2 = tcg_const_tl(a->zimm);
63 dst = tcg_temp_new();
64
65 /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
66 if (a->rs1 == 0) {
67 /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
68 s1 = tcg_const_tl(RV_VLEN_MAX);
69 } else {
70 s1 = tcg_temp_new();
71 gen_get_gpr(s1, a->rs1);
72 }
73 gen_helper_vsetvl(dst, cpu_env, s1, s2);
74 gen_set_gpr(a->rd, dst);
75 gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
76 ctx->base.is_jmp = DISAS_NORETURN;
77
78 tcg_temp_free(s1);
79 tcg_temp_free(s2);
80 tcg_temp_free(dst);
81 return true;
82}
751538d5
LZ		 83
84/* vector register offset from env */
85static uint32_t vreg_ofs(DisasContext *s, int reg)
86{
87 return offsetof(CPURISCVState, vreg) + reg * s->vlen / 8;
88}
89
90/* check functions */
91
92/*
93 * In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
94 * So RVV is also be checked in this function.
95 */
96static bool vext_check_isa_ill(DisasContext *s)
97{
98 return !s->vill;
99}
100
101/*
102 * There are two rules check here.
103 *
104 * 1. Vector register numbers are multiples of LMUL. (Section 3.2)
105 *
106 * 2. For all widening instructions, the destination LMUL value must also be
107 * a supported LMUL value. (Section 11.2)
108 */
109static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen)
110{
111 /*
112 * The destination vector register group results are arranged as if both
113 * SEW and LMUL were at twice their current settings. (Section 11.2).
114 */
115 int legal = widen ? 2 << s->lmul : 1 << s->lmul;
116
117 return !((s->lmul == 0x3 && widen) || (reg % legal));
118}
119
120/*
121 * There are two rules check here.
122 *
123 * 1. The destination vector register group for a masked vector instruction can
124 * only overlap the source mask register (v0) when LMUL=1. (Section 5.3)
125 *
126 * 2. In widen instructions and some other insturctions, like vslideup.vx,
127 * there is no need to check whether LMUL=1.
128 */
129static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm,
130 bool force)
131{
132 return (vm != 0 || vd != 0) || (!force && (s->lmul == 0));
133}
134
135/* The LMUL setting must be such that LMUL * NFIELDS <= 8. (Section 7.8) */
136static bool vext_check_nf(DisasContext *s, uint32_t nf)
137{
138 return (1 << s->lmul) * nf <= 8;
139}
140
8fcdf776
LZ		 141/*
142 * The destination vector register group cannot overlap a source vector register
143 * group of a different element width. (Section 11.2)
144 */
145static inline bool vext_check_overlap_group(int rd, int dlen, int rs, int slen)
146{
147 return ((rd >= rs + slen) || (rs >= rd + dlen));
148}
751538d5
LZ		 149/* common translation macro */
150#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \
151static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
152{ \
153 if (CHECK(s, a)) { \
154 return OP(s, a, SEQ); \
155 } \
156 return false; \
157}
158
159/*
160 *** unit stride load and store
161 */
162typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCGv,
163 TCGv_env, TCGv_i32);
164
165static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
166 gen_helper_ldst_us *fn, DisasContext *s)
167{
168 TCGv_ptr dest, mask;
169 TCGv base;
170 TCGv_i32 desc;
171
172 TCGLabel *over = gen_new_label();
173 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
174
175 dest = tcg_temp_new_ptr();
176 mask = tcg_temp_new_ptr();
177 base = tcg_temp_new();
178
179 /*
180 * As simd_desc supports at most 256 bytes, and in this implementation,
181 * the max vector group length is 2048 bytes. So split it into two parts.
182 *
183 * The first part is vlen in bytes, encoded in maxsz of simd_desc.
184 * The second part is lmul, encoded in data of simd_desc.
185 */
186 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
187
188 gen_get_gpr(base, rs1);
189 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
190 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
191
192 fn(dest, mask, base, cpu_env, desc);
193
194 tcg_temp_free_ptr(dest);
195 tcg_temp_free_ptr(mask);
196 tcg_temp_free(base);
197 tcg_temp_free_i32(desc);
198 gen_set_label(over);
199 return true;
200}
201
202static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
203{
204 uint32_t data = 0;
205 gen_helper_ldst_us *fn;
206 static gen_helper_ldst_us * const fns[2][7][4] = {
207 /* masked unit stride load */
208 { { gen_helper_vlb_v_b_mask, gen_helper_vlb_v_h_mask,
209 gen_helper_vlb_v_w_mask, gen_helper_vlb_v_d_mask },
210 { NULL, gen_helper_vlh_v_h_mask,
211 gen_helper_vlh_v_w_mask, gen_helper_vlh_v_d_mask },
212 { NULL, NULL,
213 gen_helper_vlw_v_w_mask, gen_helper_vlw_v_d_mask },
214 { gen_helper_vle_v_b_mask, gen_helper_vle_v_h_mask,
215 gen_helper_vle_v_w_mask, gen_helper_vle_v_d_mask },
216 { gen_helper_vlbu_v_b_mask, gen_helper_vlbu_v_h_mask,
217 gen_helper_vlbu_v_w_mask, gen_helper_vlbu_v_d_mask },
218 { NULL, gen_helper_vlhu_v_h_mask,
219 gen_helper_vlhu_v_w_mask, gen_helper_vlhu_v_d_mask },
220 { NULL, NULL,
221 gen_helper_vlwu_v_w_mask, gen_helper_vlwu_v_d_mask } },
222 /* unmasked unit stride load */
223 { { gen_helper_vlb_v_b, gen_helper_vlb_v_h,
224 gen_helper_vlb_v_w, gen_helper_vlb_v_d },
225 { NULL, gen_helper_vlh_v_h,
226 gen_helper_vlh_v_w, gen_helper_vlh_v_d },
227 { NULL, NULL,
228 gen_helper_vlw_v_w, gen_helper_vlw_v_d },
229 { gen_helper_vle_v_b, gen_helper_vle_v_h,
230 gen_helper_vle_v_w, gen_helper_vle_v_d },
231 { gen_helper_vlbu_v_b, gen_helper_vlbu_v_h,
232 gen_helper_vlbu_v_w, gen_helper_vlbu_v_d },
233 { NULL, gen_helper_vlhu_v_h,
234 gen_helper_vlhu_v_w, gen_helper_vlhu_v_d },
235 { NULL, NULL,
236 gen_helper_vlwu_v_w, gen_helper_vlwu_v_d } }
237 };
238
239 fn = fns[a->vm][seq][s->sew];
240 if (fn == NULL) {
241 return false;
242 }
243
244 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
245 data = FIELD_DP32(data, VDATA, VM, a->vm);
246 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
247 data = FIELD_DP32(data, VDATA, NF, a->nf);
248 return ldst_us_trans(a->rd, a->rs1, data, fn, s);
249}
250
251static bool ld_us_check(DisasContext *s, arg_r2nfvm* a)
252{
253 return (vext_check_isa_ill(s) &&
254 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
255 vext_check_reg(s, a->rd, false) &&
256 vext_check_nf(s, a->nf));
257}
258
259GEN_VEXT_TRANS(vlb_v, 0, r2nfvm, ld_us_op, ld_us_check)
260GEN_VEXT_TRANS(vlh_v, 1, r2nfvm, ld_us_op, ld_us_check)
261GEN_VEXT_TRANS(vlw_v, 2, r2nfvm, ld_us_op, ld_us_check)
262GEN_VEXT_TRANS(vle_v, 3, r2nfvm, ld_us_op, ld_us_check)
263GEN_VEXT_TRANS(vlbu_v, 4, r2nfvm, ld_us_op, ld_us_check)
264GEN_VEXT_TRANS(vlhu_v, 5, r2nfvm, ld_us_op, ld_us_check)
265GEN_VEXT_TRANS(vlwu_v, 6, r2nfvm, ld_us_op, ld_us_check)
266
267static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
268{
269 uint32_t data = 0;
270 gen_helper_ldst_us *fn;
271 static gen_helper_ldst_us * const fns[2][4][4] = {
272 /* masked unit stride load and store */
273 { { gen_helper_vsb_v_b_mask, gen_helper_vsb_v_h_mask,
274 gen_helper_vsb_v_w_mask, gen_helper_vsb_v_d_mask },
275 { NULL, gen_helper_vsh_v_h_mask,
276 gen_helper_vsh_v_w_mask, gen_helper_vsh_v_d_mask },
277 { NULL, NULL,
278 gen_helper_vsw_v_w_mask, gen_helper_vsw_v_d_mask },
279 { gen_helper_vse_v_b_mask, gen_helper_vse_v_h_mask,
280 gen_helper_vse_v_w_mask, gen_helper_vse_v_d_mask } },
281 /* unmasked unit stride store */
282 { { gen_helper_vsb_v_b, gen_helper_vsb_v_h,
283 gen_helper_vsb_v_w, gen_helper_vsb_v_d },
284 { NULL, gen_helper_vsh_v_h,
285 gen_helper_vsh_v_w, gen_helper_vsh_v_d },
286 { NULL, NULL,
287 gen_helper_vsw_v_w, gen_helper_vsw_v_d },
288 { gen_helper_vse_v_b, gen_helper_vse_v_h,
289 gen_helper_vse_v_w, gen_helper_vse_v_d } }
290 };
291
292 fn = fns[a->vm][seq][s->sew];
293 if (fn == NULL) {
294 return false;
295 }
296
297 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
298 data = FIELD_DP32(data, VDATA, VM, a->vm);
299 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
300 data = FIELD_DP32(data, VDATA, NF, a->nf);
301 return ldst_us_trans(a->rd, a->rs1, data, fn, s);
302}
303
304static bool st_us_check(DisasContext *s, arg_r2nfvm* a)
305{
306 return (vext_check_isa_ill(s) &&
307 vext_check_reg(s, a->rd, false) &&
308 vext_check_nf(s, a->nf));
309}
310
311GEN_VEXT_TRANS(vsb_v, 0, r2nfvm, st_us_op, st_us_check)
312GEN_VEXT_TRANS(vsh_v, 1, r2nfvm, st_us_op, st_us_check)
313GEN_VEXT_TRANS(vsw_v, 2, r2nfvm, st_us_op, st_us_check)
314GEN_VEXT_TRANS(vse_v, 3, r2nfvm, st_us_op, st_us_check)
315
316/*
317 *** stride load and store
318 */
319typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv,
320 TCGv, TCGv_env, TCGv_i32);
321
322static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
323 uint32_t data, gen_helper_ldst_stride *fn,
324 DisasContext *s)
325{
326 TCGv_ptr dest, mask;
327 TCGv base, stride;
328 TCGv_i32 desc;
329
330 TCGLabel *over = gen_new_label();
331 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
332
333 dest = tcg_temp_new_ptr();
334 mask = tcg_temp_new_ptr();
335 base = tcg_temp_new();
336 stride = tcg_temp_new();
337 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
338
339 gen_get_gpr(base, rs1);
340 gen_get_gpr(stride, rs2);
341 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
342 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
343
344 fn(dest, mask, base, stride, cpu_env, desc);
345
346 tcg_temp_free_ptr(dest);
347 tcg_temp_free_ptr(mask);
348 tcg_temp_free(base);
349 tcg_temp_free(stride);
350 tcg_temp_free_i32(desc);
351 gen_set_label(over);
352 return true;
353}
354
355static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
356{
357 uint32_t data = 0;
358 gen_helper_ldst_stride *fn;
359 static gen_helper_ldst_stride * const fns[7][4] = {
360 { gen_helper_vlsb_v_b, gen_helper_vlsb_v_h,
361 gen_helper_vlsb_v_w, gen_helper_vlsb_v_d },
362 { NULL, gen_helper_vlsh_v_h,
363 gen_helper_vlsh_v_w, gen_helper_vlsh_v_d },
364 { NULL, NULL,
365 gen_helper_vlsw_v_w, gen_helper_vlsw_v_d },
366 { gen_helper_vlse_v_b, gen_helper_vlse_v_h,
367 gen_helper_vlse_v_w, gen_helper_vlse_v_d },
368 { gen_helper_vlsbu_v_b, gen_helper_vlsbu_v_h,
369 gen_helper_vlsbu_v_w, gen_helper_vlsbu_v_d },
370 { NULL, gen_helper_vlshu_v_h,
371 gen_helper_vlshu_v_w, gen_helper_vlshu_v_d },
372 { NULL, NULL,
373 gen_helper_vlswu_v_w, gen_helper_vlswu_v_d },
374 };
375
376 fn = fns[seq][s->sew];
377 if (fn == NULL) {
378 return false;
379 }
380
381 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
382 data = FIELD_DP32(data, VDATA, VM, a->vm);
383 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
384 data = FIELD_DP32(data, VDATA, NF, a->nf);
385 return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
386}
387
388static bool ld_stride_check(DisasContext *s, arg_rnfvm* a)
389{
390 return (vext_check_isa_ill(s) &&
391 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
392 vext_check_reg(s, a->rd, false) &&
393 vext_check_nf(s, a->nf));
394}
395
396GEN_VEXT_TRANS(vlsb_v, 0, rnfvm, ld_stride_op, ld_stride_check)
397GEN_VEXT_TRANS(vlsh_v, 1, rnfvm, ld_stride_op, ld_stride_check)
398GEN_VEXT_TRANS(vlsw_v, 2, rnfvm, ld_stride_op, ld_stride_check)
399GEN_VEXT_TRANS(vlse_v, 3, rnfvm, ld_stride_op, ld_stride_check)
400GEN_VEXT_TRANS(vlsbu_v, 4, rnfvm, ld_stride_op, ld_stride_check)
401GEN_VEXT_TRANS(vlshu_v, 5, rnfvm, ld_stride_op, ld_stride_check)
402GEN_VEXT_TRANS(vlswu_v, 6, rnfvm, ld_stride_op, ld_stride_check)
403
404static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
405{
406 uint32_t data = 0;
407 gen_helper_ldst_stride *fn;
408 static gen_helper_ldst_stride * const fns[4][4] = {
409 /* masked stride store */
410 { gen_helper_vssb_v_b, gen_helper_vssb_v_h,
411 gen_helper_vssb_v_w, gen_helper_vssb_v_d },
412 { NULL, gen_helper_vssh_v_h,
413 gen_helper_vssh_v_w, gen_helper_vssh_v_d },
414 { NULL, NULL,
415 gen_helper_vssw_v_w, gen_helper_vssw_v_d },
416 { gen_helper_vsse_v_b, gen_helper_vsse_v_h,
417 gen_helper_vsse_v_w, gen_helper_vsse_v_d }
418 };
419
420 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
421 data = FIELD_DP32(data, VDATA, VM, a->vm);
422 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
423 data = FIELD_DP32(data, VDATA, NF, a->nf);
424 fn = fns[seq][s->sew];
425 if (fn == NULL) {
426 return false;
427 }
428
429 return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
430}
431
432static bool st_stride_check(DisasContext *s, arg_rnfvm* a)
433{
434 return (vext_check_isa_ill(s) &&
435 vext_check_reg(s, a->rd, false) &&
436 vext_check_nf(s, a->nf));
437}
438
439GEN_VEXT_TRANS(vssb_v, 0, rnfvm, st_stride_op, st_stride_check)
440GEN_VEXT_TRANS(vssh_v, 1, rnfvm, st_stride_op, st_stride_check)
441GEN_VEXT_TRANS(vssw_v, 2, rnfvm, st_stride_op, st_stride_check)
442GEN_VEXT_TRANS(vsse_v, 3, rnfvm, st_stride_op, st_stride_check)
f732560e
LZ		 443
444/*
445 *** index load and store
446 */
447typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv,
448 TCGv_ptr, TCGv_env, TCGv_i32);
449
450static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
451 uint32_t data, gen_helper_ldst_index *fn,
452 DisasContext *s)
453{
454 TCGv_ptr dest, mask, index;
455 TCGv base;
456 TCGv_i32 desc;
457
458 TCGLabel *over = gen_new_label();
459 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
460
461 dest = tcg_temp_new_ptr();
462 mask = tcg_temp_new_ptr();
463 index = tcg_temp_new_ptr();
464 base = tcg_temp_new();
465 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
466
467 gen_get_gpr(base, rs1);
468 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
469 tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
470 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
471
472 fn(dest, mask, base, index, cpu_env, desc);
473
474 tcg_temp_free_ptr(dest);
475 tcg_temp_free_ptr(mask);
476 tcg_temp_free_ptr(index);
477 tcg_temp_free(base);
478 tcg_temp_free_i32(desc);
479 gen_set_label(over);
480 return true;
481}
482
483static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
484{
485 uint32_t data = 0;
486 gen_helper_ldst_index *fn;
487 static gen_helper_ldst_index * const fns[7][4] = {
488 { gen_helper_vlxb_v_b, gen_helper_vlxb_v_h,
489 gen_helper_vlxb_v_w, gen_helper_vlxb_v_d },
490 { NULL, gen_helper_vlxh_v_h,
491 gen_helper_vlxh_v_w, gen_helper_vlxh_v_d },
492 { NULL, NULL,
493 gen_helper_vlxw_v_w, gen_helper_vlxw_v_d },
494 { gen_helper_vlxe_v_b, gen_helper_vlxe_v_h,
495 gen_helper_vlxe_v_w, gen_helper_vlxe_v_d },
496 { gen_helper_vlxbu_v_b, gen_helper_vlxbu_v_h,
497 gen_helper_vlxbu_v_w, gen_helper_vlxbu_v_d },
498 { NULL, gen_helper_vlxhu_v_h,
499 gen_helper_vlxhu_v_w, gen_helper_vlxhu_v_d },
500 { NULL, NULL,
501 gen_helper_vlxwu_v_w, gen_helper_vlxwu_v_d },
502 };
503
504 fn = fns[seq][s->sew];
505 if (fn == NULL) {
506 return false;
507 }
508
509 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
510 data = FIELD_DP32(data, VDATA, VM, a->vm);
511 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
512 data = FIELD_DP32(data, VDATA, NF, a->nf);
513 return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
514}
515
516static bool ld_index_check(DisasContext *s, arg_rnfvm* a)
517{
518 return (vext_check_isa_ill(s) &&
519 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
520 vext_check_reg(s, a->rd, false) &&
521 vext_check_reg(s, a->rs2, false) &&
522 vext_check_nf(s, a->nf));
523}
524
525GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check)
526GEN_VEXT_TRANS(vlxh_v, 1, rnfvm, ld_index_op, ld_index_check)
527GEN_VEXT_TRANS(vlxw_v, 2, rnfvm, ld_index_op, ld_index_check)
528GEN_VEXT_TRANS(vlxe_v, 3, rnfvm, ld_index_op, ld_index_check)
529GEN_VEXT_TRANS(vlxbu_v, 4, rnfvm, ld_index_op, ld_index_check)
530GEN_VEXT_TRANS(vlxhu_v, 5, rnfvm, ld_index_op, ld_index_check)
531GEN_VEXT_TRANS(vlxwu_v, 6, rnfvm, ld_index_op, ld_index_check)
532
533static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
534{
535 uint32_t data = 0;
536 gen_helper_ldst_index *fn;
537 static gen_helper_ldst_index * const fns[4][4] = {
538 { gen_helper_vsxb_v_b, gen_helper_vsxb_v_h,
539 gen_helper_vsxb_v_w, gen_helper_vsxb_v_d },
540 { NULL, gen_helper_vsxh_v_h,
541 gen_helper_vsxh_v_w, gen_helper_vsxh_v_d },
542 { NULL, NULL,
543 gen_helper_vsxw_v_w, gen_helper_vsxw_v_d },
544 { gen_helper_vsxe_v_b, gen_helper_vsxe_v_h,
545 gen_helper_vsxe_v_w, gen_helper_vsxe_v_d }
546 };
547
548 fn = fns[seq][s->sew];
549 if (fn == NULL) {
550 return false;
551 }
552
553 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
554 data = FIELD_DP32(data, VDATA, VM, a->vm);
555 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
556 data = FIELD_DP32(data, VDATA, NF, a->nf);
557 return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
558}
559
560static bool st_index_check(DisasContext *s, arg_rnfvm* a)
561{
562 return (vext_check_isa_ill(s) &&
563 vext_check_reg(s, a->rd, false) &&
564 vext_check_reg(s, a->rs2, false) &&
565 vext_check_nf(s, a->nf));
566}
567
568GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check)
569GEN_VEXT_TRANS(vsxh_v, 1, rnfvm, st_index_op, st_index_check)
570GEN_VEXT_TRANS(vsxw_v, 2, rnfvm, st_index_op, st_index_check)
571GEN_VEXT_TRANS(vsxe_v, 3, rnfvm, st_index_op, st_index_check)
022b4ecf
LZ		 572
573/*
574 *** unit stride fault-only-first load
575 */
576static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
577 gen_helper_ldst_us *fn, DisasContext *s)
578{
579 TCGv_ptr dest, mask;
580 TCGv base;
581 TCGv_i32 desc;
582
583 TCGLabel *over = gen_new_label();
584 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
585
586 dest = tcg_temp_new_ptr();
587 mask = tcg_temp_new_ptr();
588 base = tcg_temp_new();
589 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
590
591 gen_get_gpr(base, rs1);
592 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
593 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
594
595 fn(dest, mask, base, cpu_env, desc);
596
597 tcg_temp_free_ptr(dest);
598 tcg_temp_free_ptr(mask);
599 tcg_temp_free(base);
600 tcg_temp_free_i32(desc);
601 gen_set_label(over);
602 return true;
603}
604
605static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
606{
607 uint32_t data = 0;
608 gen_helper_ldst_us *fn;
609 static gen_helper_ldst_us * const fns[7][4] = {
610 { gen_helper_vlbff_v_b, gen_helper_vlbff_v_h,
611 gen_helper_vlbff_v_w, gen_helper_vlbff_v_d },
612 { NULL, gen_helper_vlhff_v_h,
613 gen_helper_vlhff_v_w, gen_helper_vlhff_v_d },
614 { NULL, NULL,
615 gen_helper_vlwff_v_w, gen_helper_vlwff_v_d },
616 { gen_helper_vleff_v_b, gen_helper_vleff_v_h,
617 gen_helper_vleff_v_w, gen_helper_vleff_v_d },
618 { gen_helper_vlbuff_v_b, gen_helper_vlbuff_v_h,
619 gen_helper_vlbuff_v_w, gen_helper_vlbuff_v_d },
620 { NULL, gen_helper_vlhuff_v_h,
621 gen_helper_vlhuff_v_w, gen_helper_vlhuff_v_d },
622 { NULL, NULL,
623 gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d }
624 };
625
626 fn = fns[seq][s->sew];
627 if (fn == NULL) {
628 return false;
629 }
630
631 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
632 data = FIELD_DP32(data, VDATA, VM, a->vm);
633 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
634 data = FIELD_DP32(data, VDATA, NF, a->nf);
635 return ldff_trans(a->rd, a->rs1, data, fn, s);
636}
637
638GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check)
639GEN_VEXT_TRANS(vlhff_v, 1, r2nfvm, ldff_op, ld_us_check)
640GEN_VEXT_TRANS(vlwff_v, 2, r2nfvm, ldff_op, ld_us_check)
641GEN_VEXT_TRANS(vleff_v, 3, r2nfvm, ldff_op, ld_us_check)
642GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check)
643GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check)
644GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check)
268fcca6
LZ		 645
646/*
647 *** vector atomic operation
648 */
649typedef void gen_helper_amo(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr,
650 TCGv_env, TCGv_i32);
651
652static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
653 uint32_t data, gen_helper_amo *fn, DisasContext *s)
654{
655 TCGv_ptr dest, mask, index;
656 TCGv base;
657 TCGv_i32 desc;
658
659 TCGLabel *over = gen_new_label();
660 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
661
662 dest = tcg_temp_new_ptr();
663 mask = tcg_temp_new_ptr();
664 index = tcg_temp_new_ptr();
665 base = tcg_temp_new();
666 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
667
668 gen_get_gpr(base, rs1);
669 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
670 tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
671 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
672
673 fn(dest, mask, base, index, cpu_env, desc);
674
675 tcg_temp_free_ptr(dest);
676 tcg_temp_free_ptr(mask);
677 tcg_temp_free_ptr(index);
678 tcg_temp_free(base);
679 tcg_temp_free_i32(desc);
680 gen_set_label(over);
681 return true;
682}
683
684static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
685{
686 uint32_t data = 0;
687 gen_helper_amo *fn;
688 static gen_helper_amo *const fnsw[9] = {
689 /* no atomic operation */
690 gen_helper_vamoswapw_v_w,
691 gen_helper_vamoaddw_v_w,
692 gen_helper_vamoxorw_v_w,
693 gen_helper_vamoandw_v_w,
694 gen_helper_vamoorw_v_w,
695 gen_helper_vamominw_v_w,
696 gen_helper_vamomaxw_v_w,
697 gen_helper_vamominuw_v_w,
698 gen_helper_vamomaxuw_v_w
699 };
700#ifdef TARGET_RISCV64
701 static gen_helper_amo *const fnsd[18] = {
702 gen_helper_vamoswapw_v_d,
703 gen_helper_vamoaddw_v_d,
704 gen_helper_vamoxorw_v_d,
705 gen_helper_vamoandw_v_d,
706 gen_helper_vamoorw_v_d,
707 gen_helper_vamominw_v_d,
708 gen_helper_vamomaxw_v_d,
709 gen_helper_vamominuw_v_d,
710 gen_helper_vamomaxuw_v_d,
711 gen_helper_vamoswapd_v_d,
712 gen_helper_vamoaddd_v_d,
713 gen_helper_vamoxord_v_d,
714 gen_helper_vamoandd_v_d,
715 gen_helper_vamoord_v_d,
716 gen_helper_vamomind_v_d,
717 gen_helper_vamomaxd_v_d,
718 gen_helper_vamominud_v_d,
719 gen_helper_vamomaxud_v_d
720 };
721#endif
722
723 if (tb_cflags(s->base.tb) & CF_PARALLEL) {
724 gen_helper_exit_atomic(cpu_env);
725 s->base.is_jmp = DISAS_NORETURN;
726 return true;
727 } else {
728 if (s->sew == 3) {
729#ifdef TARGET_RISCV64
730 fn = fnsd[seq];
731#else
732 /* Check done in amo_check(). */
733 g_assert_not_reached();
734#endif
735 } else {
736 fn = fnsw[seq];
737 }
738 }
739
740 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
741 data = FIELD_DP32(data, VDATA, VM, a->vm);
742 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
743 data = FIELD_DP32(data, VDATA, WD, a->wd);
744 return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
745}
746/*
747 * There are two rules check here.
748 *
749 * 1. SEW must be at least as wide as the AMO memory element size.
750 *
751 * 2. If SEW is greater than XLEN, an illegal instruction exception is raised.
752 */
753static bool amo_check(DisasContext *s, arg_rwdvm* a)
754{
755 return (!s->vill && has_ext(s, RVA) &&
756 (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) &&
757 vext_check_reg(s, a->rd, false) &&
758 vext_check_reg(s, a->rs2, false) &&
759 ((1 << s->sew) <= sizeof(target_ulong)) &&
760 ((1 << s->sew) >= 4));
761}
762
763GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
764GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check)
765GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check)
766GEN_VEXT_TRANS(vamoandw_v, 3, rwdvm, amo_op, amo_check)
767GEN_VEXT_TRANS(vamoorw_v, 4, rwdvm, amo_op, amo_check)
768GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check)
769GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check)
770GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check)
771GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check)
772#ifdef TARGET_RISCV64
773GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check)
774GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check)
775GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check)
776GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check)
777GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check)
778GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check)
779GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
780GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
781GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
782#endif
43740e3a
LZ		 783
784/*
785 *** Vector Integer Arithmetic Instructions
786 */
787#define MAXSZ(s) (s->vlen >> (3 - s->lmul))
788
789static bool opivv_check(DisasContext *s, arg_rmrr *a)
790{
791 return (vext_check_isa_ill(s) &&
792 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
793 vext_check_reg(s, a->rd, false) &&
794 vext_check_reg(s, a->rs2, false) &&
795 vext_check_reg(s, a->rs1, false));
796}
797
798typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
799 uint32_t, uint32_t, uint32_t);
800
801static inline bool
802do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
803 gen_helper_gvec_4_ptr *fn)
804{
805 TCGLabel *over = gen_new_label();
806 if (!opivv_check(s, a)) {
807 return false;
808 }
809
810 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
811
812 if (a->vm && s->vl_eq_vlmax) {
813 gvec_fn(s->sew, vreg_ofs(s, a->rd),
814 vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1),
815 MAXSZ(s), MAXSZ(s));
816 } else {
817 uint32_t data = 0;
818
819 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
820 data = FIELD_DP32(data, VDATA, VM, a->vm);
821 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
822 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
823 vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
824 cpu_env, 0, s->vlen / 8, data, fn);
825 }
826 gen_set_label(over);
827 return true;
828}
829
830/* OPIVV with GVEC IR */
831#define GEN_OPIVV_GVEC_TRANS(NAME, SUF) \
832static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
833{ \
834 static gen_helper_gvec_4_ptr * const fns[4] = { \
835 gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
836 gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
837 }; \
838 return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
839}
840
841GEN_OPIVV_GVEC_TRANS(vadd_vv, add)
842GEN_OPIVV_GVEC_TRANS(vsub_vv, sub)
843
844typedef void gen_helper_opivx(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr,
845 TCGv_env, TCGv_i32);
846
847static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
848 gen_helper_opivx *fn, DisasContext *s)
849{
850 TCGv_ptr dest, src2, mask;
851 TCGv src1;
852 TCGv_i32 desc;
853 uint32_t data = 0;
854
855 TCGLabel *over = gen_new_label();
856 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
857
858 dest = tcg_temp_new_ptr();
859 mask = tcg_temp_new_ptr();
860 src2 = tcg_temp_new_ptr();
861 src1 = tcg_temp_new();
862 gen_get_gpr(src1, rs1);
863
864 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
865 data = FIELD_DP32(data, VDATA, VM, vm);
866 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
867 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
868
869 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
870 tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
871 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
872
873 fn(dest, mask, src1, src2, cpu_env, desc);
874
875 tcg_temp_free_ptr(dest);
876 tcg_temp_free_ptr(mask);
877 tcg_temp_free_ptr(src2);
878 tcg_temp_free(src1);
879 tcg_temp_free_i32(desc);
880 gen_set_label(over);
881 return true;
882}
883
884static bool opivx_check(DisasContext *s, arg_rmrr *a)
885{
886 return (vext_check_isa_ill(s) &&
887 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
888 vext_check_reg(s, a->rd, false) &&
889 vext_check_reg(s, a->rs2, false));
890}
891
892typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, TCGv_i64,
893 uint32_t, uint32_t);
894
895static inline bool
896do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
897 gen_helper_opivx *fn)
898{
899 if (!opivx_check(s, a)) {
900 return false;
901 }
902
903 if (a->vm && s->vl_eq_vlmax) {
904 TCGv_i64 src1 = tcg_temp_new_i64();
905 TCGv tmp = tcg_temp_new();
906
907 gen_get_gpr(tmp, a->rs1);
908 tcg_gen_ext_tl_i64(src1, tmp);
909 gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
910 src1, MAXSZ(s), MAXSZ(s));
911
912 tcg_temp_free_i64(src1);
913 tcg_temp_free(tmp);
914 return true;
915 }
916 return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
917}
918
919/* OPIVX with GVEC IR */
920#define GEN_OPIVX_GVEC_TRANS(NAME, SUF) \
921static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
922{ \
923 static gen_helper_opivx * const fns[4] = { \
924 gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
925 gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
926 }; \
927 return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
928}
929
930GEN_OPIVX_GVEC_TRANS(vadd_vx, adds)
931GEN_OPIVX_GVEC_TRANS(vsub_vx, subs)
932
933static void gen_vec_rsub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
934{
935 tcg_gen_vec_sub8_i64(d, b, a);
936}
937
938static void gen_vec_rsub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
939{
1989205c 940 tcg_gen_vec_sub16_i64(d, b, a);
43740e3a
LZ		 941}
942
943static void gen_rsub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
944{
945 tcg_gen_sub_i32(ret, arg2, arg1);
946}
947
948static void gen_rsub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
949{
950 tcg_gen_sub_i64(ret, arg2, arg1);
951}
952
953static void gen_rsub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
954{
955 tcg_gen_sub_vec(vece, r, b, a);
956}
957
958static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs,
959 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
960{
7acafcfa 961 static const TCGOpcode vecop_list[] = { INDEX_op_sub_vec, 0 };
43740e3a
LZ		 962 static const GVecGen2s rsub_op[4] = {
963 { .fni8 = gen_vec_rsub8_i64,
964 .fniv = gen_rsub_vec,
965 .fno = gen_helper_vec_rsubs8,
7acafcfa 966 .opt_opc = vecop_list,
43740e3a
LZ		 967 .vece = MO_8 },
968 { .fni8 = gen_vec_rsub16_i64,
969 .fniv = gen_rsub_vec,
970 .fno = gen_helper_vec_rsubs16,
7acafcfa 971 .opt_opc = vecop_list,
43740e3a
LZ		 972 .vece = MO_16 },
973 { .fni4 = gen_rsub_i32,
974 .fniv = gen_rsub_vec,
975 .fno = gen_helper_vec_rsubs32,
7acafcfa 976 .opt_opc = vecop_list,
43740e3a
LZ		 977 .vece = MO_32 },
978 { .fni8 = gen_rsub_i64,
979 .fniv = gen_rsub_vec,
980 .fno = gen_helper_vec_rsubs64,
7acafcfa 981 .opt_opc = vecop_list,
43740e3a
LZ		 982 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
983 .vece = MO_64 },
984 };
985
986 tcg_debug_assert(vece <= MO_64);
987 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &rsub_op[vece]);
988}
989
990GEN_OPIVX_GVEC_TRANS(vrsub_vx, rsubs)
991
992static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
993 gen_helper_opivx *fn, DisasContext *s, int zx)
994{
995 TCGv_ptr dest, src2, mask;
996 TCGv src1;
997 TCGv_i32 desc;
998 uint32_t data = 0;
999
1000 TCGLabel *over = gen_new_label();
1001 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1002
1003 dest = tcg_temp_new_ptr();
1004 mask = tcg_temp_new_ptr();
1005 src2 = tcg_temp_new_ptr();
1006 if (zx) {
1007 src1 = tcg_const_tl(imm);
1008 } else {
1009 src1 = tcg_const_tl(sextract64(imm, 0, 5));
1010 }
1011 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
1012 data = FIELD_DP32(data, VDATA, VM, vm);
1013 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
1014 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
1015
1016 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
1017 tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
1018 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
1019
1020 fn(dest, mask, src1, src2, cpu_env, desc);
1021
1022 tcg_temp_free_ptr(dest);
1023 tcg_temp_free_ptr(mask);
1024 tcg_temp_free_ptr(src2);
1025 tcg_temp_free(src1);
1026 tcg_temp_free_i32(desc);
1027 gen_set_label(over);
1028 return true;
1029}
1030
1031typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
1032 uint32_t, uint32_t);
1033
1034static inline bool
1035do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
1036 gen_helper_opivx *fn, int zx)
1037{
1038 if (!opivx_check(s, a)) {
1039 return false;
1040 }
1041
1042 if (a->vm && s->vl_eq_vlmax) {
1043 if (zx) {
1044 gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
1045 extract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s));
1046 } else {
1047 gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
1048 sextract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s));
1049 }
1050 } else {
1051 return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx);
1052 }
1053 return true;
1054}
1055
1056/* OPIVI with GVEC IR */
1057#define GEN_OPIVI_GVEC_TRANS(NAME, ZX, OPIVX, SUF) \
1058static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1059{ \
1060 static gen_helper_opivx * const fns[4] = { \
1061 gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \
1062 gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \
1063 }; \
1064 return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \
1065 fns[s->sew], ZX); \
1066}
1067
1068GEN_OPIVI_GVEC_TRANS(vadd_vi, 0, vadd_vx, addi)
1069
1070static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs,
1071 int64_t c, uint32_t oprsz, uint32_t maxsz)
1072{
1073 TCGv_i64 tmp = tcg_const_i64(c);
1074 tcg_gen_gvec_rsubs(vece, dofs, aofs, tmp, oprsz, maxsz);
1075 tcg_temp_free_i64(tmp);
1076}
1077
1078GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi)
8fcdf776
LZ		 1079
1080/* Vector Widening Integer Add/Subtract */
1081
1082/* OPIVV with WIDEN */
1083static bool opivv_widen_check(DisasContext *s, arg_rmrr *a)
1084{
1085 return (vext_check_isa_ill(s) &&
1086 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
1087 vext_check_reg(s, a->rd, true) &&
1088 vext_check_reg(s, a->rs2, false) &&
1089 vext_check_reg(s, a->rs1, false) &&
1090 vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
1091 1 << s->lmul) &&
1092 vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
1093 1 << s->lmul) &&
1094 (s->lmul < 0x3) && (s->sew < 0x3));
1095}
1096
1097static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
1098 gen_helper_gvec_4_ptr *fn,
1099 bool (*checkfn)(DisasContext *, arg_rmrr *))
1100{
1101 if (checkfn(s, a)) {
1102 uint32_t data = 0;
1103 TCGLabel *over = gen_new_label();
1104 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1105
1106 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
1107 data = FIELD_DP32(data, VDATA, VM, a->vm);
1108 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
1109 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
1110 vreg_ofs(s, a->rs1),
1111 vreg_ofs(s, a->rs2),
1112 cpu_env, 0, s->vlen / 8,
1113 data, fn);
1114 gen_set_label(over);
1115 return true;
1116 }
1117 return false;
1118}
1119
1120#define GEN_OPIVV_WIDEN_TRANS(NAME, CHECK) \
1121static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1122{ \
1123 static gen_helper_gvec_4_ptr * const fns[3] = { \
1124 gen_helper_##NAME##_b, \
1125 gen_helper_##NAME##_h, \
1126 gen_helper_##NAME##_w \
1127 }; \
1128 return do_opivv_widen(s, a, fns[s->sew], CHECK); \
1129}
1130
1131GEN_OPIVV_WIDEN_TRANS(vwaddu_vv, opivv_widen_check)
1132GEN_OPIVV_WIDEN_TRANS(vwadd_vv, opivv_widen_check)
1133GEN_OPIVV_WIDEN_TRANS(vwsubu_vv, opivv_widen_check)
1134GEN_OPIVV_WIDEN_TRANS(vwsub_vv, opivv_widen_check)
1135
1136/* OPIVX with WIDEN */
1137static bool opivx_widen_check(DisasContext *s, arg_rmrr *a)
1138{
1139 return (vext_check_isa_ill(s) &&
1140 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
1141 vext_check_reg(s, a->rd, true) &&
1142 vext_check_reg(s, a->rs2, false) &&
1143 vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
1144 1 << s->lmul) &&
1145 (s->lmul < 0x3) && (s->sew < 0x3));
1146}
1147
1148static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
1149 gen_helper_opivx *fn)
1150{
1151 if (opivx_widen_check(s, a)) {
1152 return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
1153 }
a69f97c1 1154 return false;
8fcdf776
LZ		 1155}
1156
1157#define GEN_OPIVX_WIDEN_TRANS(NAME) \
1158static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1159{ \
1160 static gen_helper_opivx * const fns[3] = { \
1161 gen_helper_##NAME##_b, \
1162 gen_helper_##NAME##_h, \
1163 gen_helper_##NAME##_w \
1164 }; \
1165 return do_opivx_widen(s, a, fns[s->sew]); \
1166}
1167
1168GEN_OPIVX_WIDEN_TRANS(vwaddu_vx)
1169GEN_OPIVX_WIDEN_TRANS(vwadd_vx)
1170GEN_OPIVX_WIDEN_TRANS(vwsubu_vx)
1171GEN_OPIVX_WIDEN_TRANS(vwsub_vx)
1172
1173/* WIDEN OPIVV with WIDEN */
1174static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a)
1175{
1176 return (vext_check_isa_ill(s) &&
1177 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
1178 vext_check_reg(s, a->rd, true) &&
1179 vext_check_reg(s, a->rs2, true) &&
1180 vext_check_reg(s, a->rs1, false) &&
1181 vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
1182 1 << s->lmul) &&
1183 (s->lmul < 0x3) && (s->sew < 0x3));
1184}
1185
1186static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
1187 gen_helper_gvec_4_ptr *fn)
1188{
1189 if (opiwv_widen_check(s, a)) {
1190 uint32_t data = 0;
1191 TCGLabel *over = gen_new_label();
1192 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1193
1194 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
1195 data = FIELD_DP32(data, VDATA, VM, a->vm);
1196 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
1197 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
1198 vreg_ofs(s, a->rs1),
1199 vreg_ofs(s, a->rs2),
1200 cpu_env, 0, s->vlen / 8, data, fn);
1201 gen_set_label(over);
1202 return true;
1203 }
1204 return false;
1205}
1206
1207#define GEN_OPIWV_WIDEN_TRANS(NAME) \
1208static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1209{ \
1210 static gen_helper_gvec_4_ptr * const fns[3] = { \
1211 gen_helper_##NAME##_b, \
1212 gen_helper_##NAME##_h, \
1213 gen_helper_##NAME##_w \
1214 }; \
1215 return do_opiwv_widen(s, a, fns[s->sew]); \
1216}
1217
1218GEN_OPIWV_WIDEN_TRANS(vwaddu_wv)
1219GEN_OPIWV_WIDEN_TRANS(vwadd_wv)
1220GEN_OPIWV_WIDEN_TRANS(vwsubu_wv)
1221GEN_OPIWV_WIDEN_TRANS(vwsub_wv)
1222
1223/* WIDEN OPIVX with WIDEN */
1224static bool opiwx_widen_check(DisasContext *s, arg_rmrr *a)
1225{
1226 return (vext_check_isa_ill(s) &&
1227 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
1228 vext_check_reg(s, a->rd, true) &&
1229 vext_check_reg(s, a->rs2, true) &&
1230 (s->lmul < 0x3) && (s->sew < 0x3));
1231}
1232
1233static bool do_opiwx_widen(DisasContext *s, arg_rmrr *a,
1234 gen_helper_opivx *fn)
1235{
1236 if (opiwx_widen_check(s, a)) {
1237 return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
1238 }
1239 return false;
1240}
1241
1242#define GEN_OPIWX_WIDEN_TRANS(NAME) \
1243static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1244{ \
1245 static gen_helper_opivx * const fns[3] = { \
1246 gen_helper_##NAME##_b, \
1247 gen_helper_##NAME##_h, \
1248 gen_helper_##NAME##_w \
1249 }; \
1250 return do_opiwx_widen(s, a, fns[s->sew]); \
1251}
1252
1253GEN_OPIWX_WIDEN_TRANS(vwaddu_wx)
1254GEN_OPIWX_WIDEN_TRANS(vwadd_wx)
1255GEN_OPIWX_WIDEN_TRANS(vwsubu_wx)
1256GEN_OPIWX_WIDEN_TRANS(vwsub_wx)
3a6f8f68
LZ		 1257
1258/* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
1259/* OPIVV without GVEC IR */
1260#define GEN_OPIVV_TRANS(NAME, CHECK) \
1261static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1262{ \
1263 if (CHECK(s, a)) { \
1264 uint32_t data = 0; \
1265 static gen_helper_gvec_4_ptr * const fns[4] = { \
1266 gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
1267 gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
1268 }; \
1269 TCGLabel *over = gen_new_label(); \
1270 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
1271 \
1272 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
1273 data = FIELD_DP32(data, VDATA, VM, a->vm); \
1274 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
1275 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
1276 vreg_ofs(s, a->rs1), \
1277 vreg_ofs(s, a->rs2), cpu_env, 0, \
1278 s->vlen / 8, data, fns[s->sew]); \
1279 gen_set_label(over); \
1280 return true; \
1281 } \
1282 return false; \
1283}
1284
1285/*
1286 * For vadc and vsbc, an illegal instruction exception is raised if the
1287 * destination vector register is v0 and LMUL > 1. (Section 12.3)
1288 */
1289static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
1290{
1291 return (vext_check_isa_ill(s) &&
1292 vext_check_reg(s, a->rd, false) &&
1293 vext_check_reg(s, a->rs2, false) &&
1294 vext_check_reg(s, a->rs1, false) &&
1295 ((a->rd != 0) || (s->lmul == 0)));
1296}
1297
1298GEN_OPIVV_TRANS(vadc_vvm, opivv_vadc_check)
1299GEN_OPIVV_TRANS(vsbc_vvm, opivv_vadc_check)
1300
1301/*
1302 * For vmadc and vmsbc, an illegal instruction exception is raised if the
1303 * destination vector register overlaps a source vector register group.
1304 */
1305static bool opivv_vmadc_check(DisasContext *s, arg_rmrr *a)
1306{
1307 return (vext_check_isa_ill(s) &&
1308 vext_check_reg(s, a->rs2, false) &&
1309 vext_check_reg(s, a->rs1, false) &&
1310 vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
1311 vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul));
1312}
1313
1314GEN_OPIVV_TRANS(vmadc_vvm, opivv_vmadc_check)
1315GEN_OPIVV_TRANS(vmsbc_vvm, opivv_vmadc_check)
1316
1317static bool opivx_vadc_check(DisasContext *s, arg_rmrr *a)
1318{
1319 return (vext_check_isa_ill(s) &&
1320 vext_check_reg(s, a->rd, false) &&
1321 vext_check_reg(s, a->rs2, false) &&
1322 ((a->rd != 0) || (s->lmul == 0)));
1323}
1324
1325/* OPIVX without GVEC IR */
1326#define GEN_OPIVX_TRANS(NAME, CHECK) \
1327static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1328{ \
1329 if (CHECK(s, a)) { \
1330 static gen_helper_opivx * const fns[4] = { \
1331 gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
1332 gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
1333 }; \
1334 \
1335 return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
1336 } \
1337 return false; \
1338}
1339
1340GEN_OPIVX_TRANS(vadc_vxm, opivx_vadc_check)
1341GEN_OPIVX_TRANS(vsbc_vxm, opivx_vadc_check)
1342
1343static bool opivx_vmadc_check(DisasContext *s, arg_rmrr *a)
1344{
1345 return (vext_check_isa_ill(s) &&
1346 vext_check_reg(s, a->rs2, false) &&
1347 vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul));
1348}
1349
1350GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check)
1351GEN_OPIVX_TRANS(vmsbc_vxm, opivx_vmadc_check)
1352
1353/* OPIVI without GVEC IR */
1354#define GEN_OPIVI_TRANS(NAME, ZX, OPIVX, CHECK) \
1355static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1356{ \
1357 if (CHECK(s, a)) { \
1358 static gen_helper_opivx * const fns[4] = { \
1359 gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \
1360 gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \
1361 }; \
1362 return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \
1363 fns[s->sew], s, ZX); \
1364 } \
1365 return false; \
1366}
1367
1368GEN_OPIVI_TRANS(vadc_vim, 0, vadc_vxm, opivx_vadc_check)
1369GEN_OPIVI_TRANS(vmadc_vim, 0, vmadc_vxm, opivx_vmadc_check)
d3842924
LZ		 1370
1371/* Vector Bitwise Logical Instructions */
1372GEN_OPIVV_GVEC_TRANS(vand_vv, and)
1373GEN_OPIVV_GVEC_TRANS(vor_vv, or)
1374GEN_OPIVV_GVEC_TRANS(vxor_vv, xor)
1375GEN_OPIVX_GVEC_TRANS(vand_vx, ands)
1376GEN_OPIVX_GVEC_TRANS(vor_vx, ors)
1377GEN_OPIVX_GVEC_TRANS(vxor_vx, xors)
1378GEN_OPIVI_GVEC_TRANS(vand_vi, 0, vand_vx, andi)
1379GEN_OPIVI_GVEC_TRANS(vor_vi, 0, vor_vx, ori)
1380GEN_OPIVI_GVEC_TRANS(vxor_vi, 0, vxor_vx, xori)
3277d955
LZ		 1381
1382/* Vector Single-Width Bit Shift Instructions */
1383GEN_OPIVV_GVEC_TRANS(vsll_vv, shlv)
1384GEN_OPIVV_GVEC_TRANS(vsrl_vv, shrv)
1385GEN_OPIVV_GVEC_TRANS(vsra_vv, sarv)
1386
1387typedef void GVecGen2sFn32(unsigned, uint32_t, uint32_t, TCGv_i32,
1388 uint32_t, uint32_t);
1389
1390static inline bool
1391do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
1392 gen_helper_opivx *fn)
1393{
1394 if (!opivx_check(s, a)) {
1395 return false;
1396 }
1397
1398 if (a->vm && s->vl_eq_vlmax) {
1399 TCGv_i32 src1 = tcg_temp_new_i32();
1400 TCGv tmp = tcg_temp_new();
1401
1402 gen_get_gpr(tmp, a->rs1);
1403 tcg_gen_trunc_tl_i32(src1, tmp);
1404 tcg_gen_extract_i32(src1, src1, 0, s->sew + 3);
1405 gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
1406 src1, MAXSZ(s), MAXSZ(s));
1407
1408 tcg_temp_free_i32(src1);
1409 tcg_temp_free(tmp);
1410 return true;
1411 }
1412 return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
1413}
1414
1415#define GEN_OPIVX_GVEC_SHIFT_TRANS(NAME, SUF) \
1416static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1417{ \
1418 static gen_helper_opivx * const fns[4] = { \
1419 gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
1420 gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
1421 }; \
1422 \
1423 return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
1424}
1425
1426GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls)
1427GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs)
1428GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
1429
1430GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli)
1431GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri)
1432GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari)
7689b028
LZ		 1433
1434/* Vector Narrowing Integer Right Shift Instructions */
1435static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
1436{
1437 return (vext_check_isa_ill(s) &&
1438 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
1439 vext_check_reg(s, a->rd, false) &&
1440 vext_check_reg(s, a->rs2, true) &&
1441 vext_check_reg(s, a->rs1, false) &&
1442 vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
1443 2 << s->lmul) &&
1444 (s->lmul < 0x3) && (s->sew < 0x3));
1445}
1446
1447/* OPIVV with NARROW */
1448#define GEN_OPIVV_NARROW_TRANS(NAME) \
1449static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1450{ \
1451 if (opivv_narrow_check(s, a)) { \
1452 uint32_t data = 0; \
1453 static gen_helper_gvec_4_ptr * const fns[3] = { \
1454 gen_helper_##NAME##_b, \
1455 gen_helper_##NAME##_h, \
1456 gen_helper_##NAME##_w, \
1457 }; \
1458 TCGLabel *over = gen_new_label(); \
1459 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
1460 \
1461 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
1462 data = FIELD_DP32(data, VDATA, VM, a->vm); \
1463 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
1464 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
1465 vreg_ofs(s, a->rs1), \
1466 vreg_ofs(s, a->rs2), cpu_env, 0, \
1467 s->vlen / 8, data, fns[s->sew]); \
1468 gen_set_label(over); \
1469 return true; \
1470 } \
1471 return false; \
1472}
1473GEN_OPIVV_NARROW_TRANS(vnsra_vv)
1474GEN_OPIVV_NARROW_TRANS(vnsrl_vv)
1475
1476static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
1477{
1478 return (vext_check_isa_ill(s) &&
1479 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
1480 vext_check_reg(s, a->rd, false) &&
1481 vext_check_reg(s, a->rs2, true) &&
1482 vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
1483 2 << s->lmul) &&
1484 (s->lmul < 0x3) && (s->sew < 0x3));
1485}
1486
1487/* OPIVX with NARROW */
1488#define GEN_OPIVX_NARROW_TRANS(NAME) \
1489static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1490{ \
1491 if (opivx_narrow_check(s, a)) { \
1492 static gen_helper_opivx * const fns[3] = { \
1493 gen_helper_##NAME##_b, \
1494 gen_helper_##NAME##_h, \
1495 gen_helper_##NAME##_w, \
1496 }; \
1497 return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
1498 } \
1499 return false; \
1500}
1501
1502GEN_OPIVX_NARROW_TRANS(vnsra_vx)
1503GEN_OPIVX_NARROW_TRANS(vnsrl_vx)
1504
1505/* OPIVI with NARROW */
1506#define GEN_OPIVI_NARROW_TRANS(NAME, ZX, OPIVX) \
1507static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1508{ \
1509 if (opivx_narrow_check(s, a)) { \
1510 static gen_helper_opivx * const fns[3] = { \
1511 gen_helper_##OPIVX##_b, \
1512 gen_helper_##OPIVX##_h, \
1513 gen_helper_##OPIVX##_w, \
1514 }; \
1515 return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \
1516 fns[s->sew], s, ZX); \
1517 } \
1518 return false; \
1519}
1520
1521GEN_OPIVI_NARROW_TRANS(vnsra_vi, 1, vnsra_vx)
1522GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx)
1366fc79
LZ		 1523
1524/* Vector Integer Comparison Instructions */
1525/*
1526 * For all comparison instructions, an illegal instruction exception is raised
1527 * if the destination vector register overlaps a source vector register group
1528 * and LMUL > 1.
1529 */
1530static bool opivv_cmp_check(DisasContext *s, arg_rmrr *a)
1531{
1532 return (vext_check_isa_ill(s) &&
1533 vext_check_reg(s, a->rs2, false) &&
1534 vext_check_reg(s, a->rs1, false) &&
1535 ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
1536 vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) ||
1537 (s->lmul == 0)));
1538}
1539GEN_OPIVV_TRANS(vmseq_vv, opivv_cmp_check)
1540GEN_OPIVV_TRANS(vmsne_vv, opivv_cmp_check)
1541GEN_OPIVV_TRANS(vmsltu_vv, opivv_cmp_check)
1542GEN_OPIVV_TRANS(vmslt_vv, opivv_cmp_check)
1543GEN_OPIVV_TRANS(vmsleu_vv, opivv_cmp_check)
1544GEN_OPIVV_TRANS(vmsle_vv, opivv_cmp_check)
1545
1546static bool opivx_cmp_check(DisasContext *s, arg_rmrr *a)
1547{
1548 return (vext_check_isa_ill(s) &&
1549 vext_check_reg(s, a->rs2, false) &&
1550 (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) ||
1551 (s->lmul == 0)));
1552}
1553
1554GEN_OPIVX_TRANS(vmseq_vx, opivx_cmp_check)
1555GEN_OPIVX_TRANS(vmsne_vx, opivx_cmp_check)
1556GEN_OPIVX_TRANS(vmsltu_vx, opivx_cmp_check)
1557GEN_OPIVX_TRANS(vmslt_vx, opivx_cmp_check)
1558GEN_OPIVX_TRANS(vmsleu_vx, opivx_cmp_check)
1559GEN_OPIVX_TRANS(vmsle_vx, opivx_cmp_check)
1560GEN_OPIVX_TRANS(vmsgtu_vx, opivx_cmp_check)
1561GEN_OPIVX_TRANS(vmsgt_vx, opivx_cmp_check)
1562
1563GEN_OPIVI_TRANS(vmseq_vi, 0, vmseq_vx, opivx_cmp_check)
1564GEN_OPIVI_TRANS(vmsne_vi, 0, vmsne_vx, opivx_cmp_check)
1565GEN_OPIVI_TRANS(vmsleu_vi, 1, vmsleu_vx, opivx_cmp_check)
1566GEN_OPIVI_TRANS(vmsle_vi, 0, vmsle_vx, opivx_cmp_check)
1567GEN_OPIVI_TRANS(vmsgtu_vi, 1, vmsgtu_vx, opivx_cmp_check)
1568GEN_OPIVI_TRANS(vmsgt_vi, 0, vmsgt_vx, opivx_cmp_check)
558fa779
LZ		 1569
1570/* Vector Integer Min/Max Instructions */
1571GEN_OPIVV_GVEC_TRANS(vminu_vv, umin)
1572GEN_OPIVV_GVEC_TRANS(vmin_vv, smin)
1573GEN_OPIVV_GVEC_TRANS(vmaxu_vv, umax)
1574GEN_OPIVV_GVEC_TRANS(vmax_vv, smax)
1575GEN_OPIVX_TRANS(vminu_vx, opivx_check)
1576GEN_OPIVX_TRANS(vmin_vx, opivx_check)
1577GEN_OPIVX_TRANS(vmaxu_vx, opivx_check)
1578GEN_OPIVX_TRANS(vmax_vx, opivx_check)
958b85f3
LZ		 1579
1580/* Vector Single-Width Integer Multiply Instructions */
1581GEN_OPIVV_GVEC_TRANS(vmul_vv, mul)
1582GEN_OPIVV_TRANS(vmulh_vv, opivv_check)
1583GEN_OPIVV_TRANS(vmulhu_vv, opivv_check)
1584GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check)
1585GEN_OPIVX_GVEC_TRANS(vmul_vx, muls)
1586GEN_OPIVX_TRANS(vmulh_vx, opivx_check)
1587GEN_OPIVX_TRANS(vmulhu_vx, opivx_check)
1588GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check)
85e6658c
LZ		 1589
1590/* Vector Integer Divide Instructions */
1591GEN_OPIVV_TRANS(vdivu_vv, opivv_check)
1592GEN_OPIVV_TRANS(vdiv_vv, opivv_check)
1593GEN_OPIVV_TRANS(vremu_vv, opivv_check)
1594GEN_OPIVV_TRANS(vrem_vv, opivv_check)
1595GEN_OPIVX_TRANS(vdivu_vx, opivx_check)
1596GEN_OPIVX_TRANS(vdiv_vx, opivx_check)
1597GEN_OPIVX_TRANS(vremu_vx, opivx_check)
1598GEN_OPIVX_TRANS(vrem_vx, opivx_check)
97b1cba3
LZ		 1599
1600/* Vector Widening Integer Multiply Instructions */
1601GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check)
1602GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check)
1603GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check)
1604GEN_OPIVX_WIDEN_TRANS(vwmul_vx)
1605GEN_OPIVX_WIDEN_TRANS(vwmulu_vx)
1606GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx)
54df813a
LZ		 1607
1608/* Vector Single-Width Integer Multiply-Add Instructions */
1609GEN_OPIVV_TRANS(vmacc_vv, opivv_check)
1610GEN_OPIVV_TRANS(vnmsac_vv, opivv_check)
1611GEN_OPIVV_TRANS(vmadd_vv, opivv_check)
1612GEN_OPIVV_TRANS(vnmsub_vv, opivv_check)
1613GEN_OPIVX_TRANS(vmacc_vx, opivx_check)
1614GEN_OPIVX_TRANS(vnmsac_vx, opivx_check)
1615GEN_OPIVX_TRANS(vmadd_vx, opivx_check)
1616GEN_OPIVX_TRANS(vnmsub_vx, opivx_check)
2b587b33
LZ		 1617
1618/* Vector Widening Integer Multiply-Add Instructions */
1619GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check)
1620GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check)
1621GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check)
1622GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx)
1623GEN_OPIVX_WIDEN_TRANS(vwmacc_vx)
1624GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx)
1625GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx)
f020a7a1
LZ		 1626
1627/* Vector Integer Merge and Move Instructions */
1628static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
1629{
1630 if (vext_check_isa_ill(s) &&
1631 vext_check_reg(s, a->rd, false) &&
1632 vext_check_reg(s, a->rs1, false)) {
1633
1634 if (s->vl_eq_vlmax) {
1635 tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
1636 vreg_ofs(s, a->rs1),
1637 MAXSZ(s), MAXSZ(s));
1638 } else {
1639 uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
1640 static gen_helper_gvec_2_ptr * const fns[4] = {
1641 gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
1642 gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
1643 };
1644 TCGLabel *over = gen_new_label();
1645 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1646
1647 tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
1648 cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
1649 gen_set_label(over);
1650 }
1651 return true;
1652 }
1653 return false;
1654}
1655
1656typedef void gen_helper_vmv_vx(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32);
1657static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
1658{
1659 if (vext_check_isa_ill(s) &&
1660 vext_check_reg(s, a->rd, false)) {
1661
1662 TCGv s1;
1663 TCGLabel *over = gen_new_label();
1664 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1665
1666 s1 = tcg_temp_new();
1667 gen_get_gpr(s1, a->rs1);
1668
1669 if (s->vl_eq_vlmax) {
1670 tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
1671 MAXSZ(s), MAXSZ(s), s1);
1672 } else {
1673 TCGv_i32 desc ;
1674 TCGv_i64 s1_i64 = tcg_temp_new_i64();
1675 TCGv_ptr dest = tcg_temp_new_ptr();
1676 uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
1677 static gen_helper_vmv_vx * const fns[4] = {
1678 gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
1679 gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
1680 };
1681
1682 tcg_gen_ext_tl_i64(s1_i64, s1);
1683 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
1684 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
1685 fns[s->sew](dest, s1_i64, cpu_env, desc);
1686
1687 tcg_temp_free_ptr(dest);
1688 tcg_temp_free_i32(desc);
1689 tcg_temp_free_i64(s1_i64);
1690 }
1691
1692 tcg_temp_free(s1);
1693 gen_set_label(over);
1694 return true;
1695 }
1696 return false;
1697}
1698
1699static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
1700{
1701 if (vext_check_isa_ill(s) &&
1702 vext_check_reg(s, a->rd, false)) {
1703
1704 int64_t simm = sextract64(a->rs1, 0, 5);
1705 if (s->vl_eq_vlmax) {
1706 tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
1707 MAXSZ(s), MAXSZ(s), simm);
1708 } else {
1709 TCGv_i32 desc;
1710 TCGv_i64 s1;
1711 TCGv_ptr dest;
1712 uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
1713 static gen_helper_vmv_vx * const fns[4] = {
1714 gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
1715 gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
1716 };
1717 TCGLabel *over = gen_new_label();
1718 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1719
1720 s1 = tcg_const_i64(simm);
1721 dest = tcg_temp_new_ptr();
1722 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
1723 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
1724 fns[s->sew](dest, s1, cpu_env, desc);
1725
1726 tcg_temp_free_ptr(dest);
1727 tcg_temp_free_i32(desc);
1728 tcg_temp_free_i64(s1);
1729 gen_set_label(over);
1730 }
1731 return true;
1732 }
1733 return false;
1734}
1735
1736GEN_OPIVV_TRANS(vmerge_vvm, opivv_vadc_check)
1737GEN_OPIVX_TRANS(vmerge_vxm, opivx_vadc_check)
1738GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vadc_check)
eb2650e3
LZ		 1739
1740/*
1741 *** Vector Fixed-Point Arithmetic Instructions
1742 */
1743
1744/* Vector Single-Width Saturating Add and Subtract */
1745GEN_OPIVV_TRANS(vsaddu_vv, opivv_check)
1746GEN_OPIVV_TRANS(vsadd_vv, opivv_check)
1747GEN_OPIVV_TRANS(vssubu_vv, opivv_check)
1748GEN_OPIVV_TRANS(vssub_vv, opivv_check)
1749GEN_OPIVX_TRANS(vsaddu_vx, opivx_check)
1750GEN_OPIVX_TRANS(vsadd_vx, opivx_check)
1751GEN_OPIVX_TRANS(vssubu_vx, opivx_check)
1752GEN_OPIVX_TRANS(vssub_vx, opivx_check)
1753GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check)
1754GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check)
b7aee481
LZ		 1755
1756/* Vector Single-Width Averaging Add and Subtract */
1757GEN_OPIVV_TRANS(vaadd_vv, opivv_check)
1758GEN_OPIVV_TRANS(vasub_vv, opivv_check)
1759GEN_OPIVX_TRANS(vaadd_vx, opivx_check)
1760GEN_OPIVX_TRANS(vasub_vx, opivx_check)
1761GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check)
9f0ff9e5
LZ		 1762
1763/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
1764GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
1765GEN_OPIVX_TRANS(vsmul_vx, opivx_check)
0a1eaf00
LZ		 1766
1767/* Vector Widening Saturating Scaled Multiply-Add */
1768GEN_OPIVV_WIDEN_TRANS(vwsmaccu_vv, opivv_widen_check)
1769GEN_OPIVV_WIDEN_TRANS(vwsmacc_vv, opivv_widen_check)
1770GEN_OPIVV_WIDEN_TRANS(vwsmaccsu_vv, opivv_widen_check)
1771GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx)
1772GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx)
1773GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx)
1774GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx)
04a61406
LZ		 1775
1776/* Vector Single-Width Scaling Shift Instructions */
1777GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
1778GEN_OPIVV_TRANS(vssra_vv, opivv_check)
1779GEN_OPIVX_TRANS(vssrl_vx, opivx_check)
1780GEN_OPIVX_TRANS(vssra_vx, opivx_check)
1781GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check)
1782GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check)
9ff3d287
LZ		 1783
1784/* Vector Narrowing Fixed-Point Clip Instructions */
1785GEN_OPIVV_NARROW_TRANS(vnclipu_vv)
1786GEN_OPIVV_NARROW_TRANS(vnclip_vv)
1787GEN_OPIVX_NARROW_TRANS(vnclipu_vx)
1788GEN_OPIVX_NARROW_TRANS(vnclip_vx)
1789GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx)
1790GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx)
ce2a0343
LZ		 1791
1792/*
1793 *** Vector Float Point Arithmetic Instructions
1794 */
1795/* Vector Single-Width Floating-Point Add/Subtract Instructions */
1796
1797/*
1798 * If the current SEW does not correspond to a supported IEEE floating-point
1799 * type, an illegal instruction exception is raised.
1800 */
1801static bool opfvv_check(DisasContext *s, arg_rmrr *a)
1802{
1803 return (vext_check_isa_ill(s) &&
1804 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
1805 vext_check_reg(s, a->rd, false) &&
1806 vext_check_reg(s, a->rs2, false) &&
1807 vext_check_reg(s, a->rs1, false) &&
1808 (s->sew != 0));
1809}
1810
1811/* OPFVV without GVEC IR */
1812#define GEN_OPFVV_TRANS(NAME, CHECK) \
1813static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1814{ \
1815 if (CHECK(s, a)) { \
1816 uint32_t data = 0; \
1817 static gen_helper_gvec_4_ptr * const fns[3] = { \
1818 gen_helper_##NAME##_h, \
1819 gen_helper_##NAME##_w, \
1820 gen_helper_##NAME##_d, \
1821 }; \
1822 TCGLabel *over = gen_new_label(); \
1823 gen_set_rm(s, 7); \
1824 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
1825 \
1826 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
1827 data = FIELD_DP32(data, VDATA, VM, a->vm); \
1828 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
1829 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
1830 vreg_ofs(s, a->rs1), \
1831 vreg_ofs(s, a->rs2), cpu_env, 0, \
1832 s->vlen / 8, data, fns[s->sew - 1]); \
1833 gen_set_label(over); \
1834 return true; \
1835 } \
1836 return false; \
1837}
1838GEN_OPFVV_TRANS(vfadd_vv, opfvv_check)
1839GEN_OPFVV_TRANS(vfsub_vv, opfvv_check)
1840
1841typedef void gen_helper_opfvf(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_ptr,
1842 TCGv_env, TCGv_i32);
1843
1844static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
1845 uint32_t data, gen_helper_opfvf *fn, DisasContext *s)
1846{
1847 TCGv_ptr dest, src2, mask;
1848 TCGv_i32 desc;
1849
1850 TCGLabel *over = gen_new_label();
1851 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1852
1853 dest = tcg_temp_new_ptr();
1854 mask = tcg_temp_new_ptr();
1855 src2 = tcg_temp_new_ptr();
1856 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
1857
1858 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
1859 tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
1860 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
1861
1862 fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc);
1863
1864 tcg_temp_free_ptr(dest);
1865 tcg_temp_free_ptr(mask);
1866 tcg_temp_free_ptr(src2);
1867 tcg_temp_free_i32(desc);
1868 gen_set_label(over);
1869 return true;
1870}
1871
1872static bool opfvf_check(DisasContext *s, arg_rmrr *a)
1873{
1874/*
1875 * If the current SEW does not correspond to a supported IEEE floating-point
1876 * type, an illegal instruction exception is raised
1877 */
1878 return (vext_check_isa_ill(s) &&
1879 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
1880 vext_check_reg(s, a->rd, false) &&
1881 vext_check_reg(s, a->rs2, false) &&
1882 (s->sew != 0));
1883}
1884
1885/* OPFVF without GVEC IR */
1886#define GEN_OPFVF_TRANS(NAME, CHECK) \
1887static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1888{ \
1889 if (CHECK(s, a)) { \
1890 uint32_t data = 0; \
1891 static gen_helper_opfvf *const fns[3] = { \
1892 gen_helper_##NAME##_h, \
1893 gen_helper_##NAME##_w, \
1894 gen_helper_##NAME##_d, \
1895 }; \
1896 gen_set_rm(s, 7); \
1897 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
1898 data = FIELD_DP32(data, VDATA, VM, a->vm); \
1899 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
1900 return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
1901 fns[s->sew - 1], s); \
1902 } \
1903 return false; \
1904}
1905
1906GEN_OPFVF_TRANS(vfadd_vf, opfvf_check)
1907GEN_OPFVF_TRANS(vfsub_vf, opfvf_check)
1908GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
eeffab2e
LZ		 1909
1910/* Vector Widening Floating-Point Add/Subtract Instructions */
1911static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
1912{
1913 return (vext_check_isa_ill(s) &&
1914 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
1915 vext_check_reg(s, a->rd, true) &&
1916 vext_check_reg(s, a->rs2, false) &&
1917 vext_check_reg(s, a->rs1, false) &&
1918 vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
1919 1 << s->lmul) &&
1920 vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
1921 1 << s->lmul) &&
1922 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
1923}
1924
1925/* OPFVV with WIDEN */
1926#define GEN_OPFVV_WIDEN_TRANS(NAME, CHECK) \
1927static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1928{ \
1929 if (CHECK(s, a)) { \
1930 uint32_t data = 0; \
1931 static gen_helper_gvec_4_ptr * const fns[2] = { \
1932 gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
1933 }; \
1934 TCGLabel *over = gen_new_label(); \
1935 gen_set_rm(s, 7); \
1936 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
1937 \
1938 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
1939 data = FIELD_DP32(data, VDATA, VM, a->vm); \
1940 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
1941 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
1942 vreg_ofs(s, a->rs1), \
1943 vreg_ofs(s, a->rs2), cpu_env, 0, \
1944 s->vlen / 8, data, fns[s->sew - 1]); \
1945 gen_set_label(over); \
1946 return true; \
1947 } \
1948 return false; \
1949}
1950
1951GEN_OPFVV_WIDEN_TRANS(vfwadd_vv, opfvv_widen_check)
1952GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
1953
1954static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
1955{
1956 return (vext_check_isa_ill(s) &&
1957 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
1958 vext_check_reg(s, a->rd, true) &&
1959 vext_check_reg(s, a->rs2, false) &&
1960 vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
1961 1 << s->lmul) &&
1962 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
1963}
1964
1965/* OPFVF with WIDEN */
1966#define GEN_OPFVF_WIDEN_TRANS(NAME) \
1967static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
1968{ \
1969 if (opfvf_widen_check(s, a)) { \
1970 uint32_t data = 0; \
1971 static gen_helper_opfvf *const fns[2] = { \
1972 gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
1973 }; \
1974 gen_set_rm(s, 7); \
1975 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
1976 data = FIELD_DP32(data, VDATA, VM, a->vm); \
1977 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
1978 return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
1979 fns[s->sew - 1], s); \
1980 } \
1981 return false; \
1982}
1983
1984GEN_OPFVF_WIDEN_TRANS(vfwadd_vf)
1985GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
1986
1987static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
1988{
1989 return (vext_check_isa_ill(s) &&
1990 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
1991 vext_check_reg(s, a->rd, true) &&
1992 vext_check_reg(s, a->rs2, true) &&
1993 vext_check_reg(s, a->rs1, false) &&
1994 vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
1995 1 << s->lmul) &&
1996 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
1997}
1998
1999/* WIDEN OPFVV with WIDEN */
2000#define GEN_OPFWV_WIDEN_TRANS(NAME) \
2001static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
2002{ \
2003 if (opfwv_widen_check(s, a)) { \
2004 uint32_t data = 0; \
2005 static gen_helper_gvec_4_ptr * const fns[2] = { \
2006 gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
2007 }; \
2008 TCGLabel *over = gen_new_label(); \
2009 gen_set_rm(s, 7); \
2010 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
2011 \
2012 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
2013 data = FIELD_DP32(data, VDATA, VM, a->vm); \
2014 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2015 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2016 vreg_ofs(s, a->rs1), \
2017 vreg_ofs(s, a->rs2), cpu_env, 0, \
2018 s->vlen / 8, data, fns[s->sew - 1]); \
2019 gen_set_label(over); \
2020 return true; \
2021 } \
2022 return false; \
2023}
2024
2025GEN_OPFWV_WIDEN_TRANS(vfwadd_wv)
2026GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
2027
2028static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
2029{
2030 return (vext_check_isa_ill(s) &&
2031 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
2032 vext_check_reg(s, a->rd, true) &&
2033 vext_check_reg(s, a->rs2, true) &&
2034 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
2035}
2036
2037/* WIDEN OPFVF with WIDEN */
2038#define GEN_OPFWF_WIDEN_TRANS(NAME) \
2039static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
2040{ \
2041 if (opfwf_widen_check(s, a)) { \
2042 uint32_t data = 0; \
2043 static gen_helper_opfvf *const fns[2] = { \
2044 gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
2045 }; \
2046 gen_set_rm(s, 7); \
2047 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
2048 data = FIELD_DP32(data, VDATA, VM, a->vm); \
2049 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2050 return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
2051 fns[s->sew - 1], s); \
2052 } \
2053 return false; \
2054}
2055
2056GEN_OPFWF_WIDEN_TRANS(vfwadd_wf)
2057GEN_OPFWF_WIDEN_TRANS(vfwsub_wf)
0e0057cb
LZ		 2058
2059/* Vector Single-Width Floating-Point Multiply/Divide Instructions */
2060GEN_OPFVV_TRANS(vfmul_vv, opfvv_check)
2061GEN_OPFVV_TRANS(vfdiv_vv, opfvv_check)
2062GEN_OPFVF_TRANS(vfmul_vf, opfvf_check)
2063GEN_OPFVF_TRANS(vfdiv_vf, opfvf_check)
2064GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check)
f7c7b7cd
LZ		 2065
2066/* Vector Widening Floating-Point Multiply */
2067GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check)
2068GEN_OPFVF_WIDEN_TRANS(vfwmul_vf)
4aa5a8fe
LZ		 2069
2070/* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
2071GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check)
2072GEN_OPFVV_TRANS(vfnmacc_vv, opfvv_check)
2073GEN_OPFVV_TRANS(vfmsac_vv, opfvv_check)
2074GEN_OPFVV_TRANS(vfnmsac_vv, opfvv_check)
2075GEN_OPFVV_TRANS(vfmadd_vv, opfvv_check)
2076GEN_OPFVV_TRANS(vfnmadd_vv, opfvv_check)
2077GEN_OPFVV_TRANS(vfmsub_vv, opfvv_check)
2078GEN_OPFVV_TRANS(vfnmsub_vv, opfvv_check)
2079GEN_OPFVF_TRANS(vfmacc_vf, opfvf_check)
2080GEN_OPFVF_TRANS(vfnmacc_vf, opfvf_check)
2081GEN_OPFVF_TRANS(vfmsac_vf, opfvf_check)
2082GEN_OPFVF_TRANS(vfnmsac_vf, opfvf_check)
2083GEN_OPFVF_TRANS(vfmadd_vf, opfvf_check)
2084GEN_OPFVF_TRANS(vfnmadd_vf, opfvf_check)
2085GEN_OPFVF_TRANS(vfmsub_vf, opfvf_check)
2086GEN_OPFVF_TRANS(vfnmsub_vf, opfvf_check)
0dd50959
LZ		 2087
2088/* Vector Widening Floating-Point Fused Multiply-Add Instructions */
2089GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check)
2090GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check)
2091GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check)
2092GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check)
2093GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf)
2094GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf)
2095GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf)
2096GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf)
d9e4ce72
LZ		 2097
2098/* Vector Floating-Point Square-Root Instruction */
2099
2100/*
2101 * If the current SEW does not correspond to a supported IEEE floating-point
2102 * type, an illegal instruction exception is raised
2103 */
2104static bool opfv_check(DisasContext *s, arg_rmr *a)
2105{
2106 return (vext_check_isa_ill(s) &&
2107 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
2108 vext_check_reg(s, a->rd, false) &&
2109 vext_check_reg(s, a->rs2, false) &&
2110 (s->sew != 0));
2111}
2112
2113#define GEN_OPFV_TRANS(NAME, CHECK) \
2114static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
2115{ \
2116 if (CHECK(s, a)) { \
2117 uint32_t data = 0; \
2118 static gen_helper_gvec_3_ptr * const fns[3] = { \
2119 gen_helper_##NAME##_h, \
2120 gen_helper_##NAME##_w, \
2121 gen_helper_##NAME##_d, \
2122 }; \
2123 TCGLabel *over = gen_new_label(); \
2124 gen_set_rm(s, 7); \
2125 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
2126 \
2127 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
2128 data = FIELD_DP32(data, VDATA, VM, a->vm); \
2129 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2130 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2131 vreg_ofs(s, a->rs2), cpu_env, 0, \
2132 s->vlen / 8, data, fns[s->sew - 1]); \
2133 gen_set_label(over); \
2134 return true; \
2135 } \
2136 return false; \
2137}
2138
2139GEN_OPFV_TRANS(vfsqrt_v, opfv_check)
230b53dd
LZ		 2140
2141/* Vector Floating-Point MIN/MAX Instructions */
2142GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
2143GEN_OPFVV_TRANS(vfmax_vv, opfvv_check)
2144GEN_OPFVF_TRANS(vfmin_vf, opfvf_check)
2145GEN_OPFVF_TRANS(vfmax_vf, opfvf_check)
1d426b81
LZ		 2146
2147/* Vector Floating-Point Sign-Injection Instructions */
2148GEN_OPFVV_TRANS(vfsgnj_vv, opfvv_check)
2149GEN_OPFVV_TRANS(vfsgnjn_vv, opfvv_check)
2150GEN_OPFVV_TRANS(vfsgnjx_vv, opfvv_check)
2151GEN_OPFVF_TRANS(vfsgnj_vf, opfvf_check)
2152GEN_OPFVF_TRANS(vfsgnjn_vf, opfvf_check)
2153GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check)
2a68e9e5
LZ		 2154
2155/* Vector Floating-Point Compare Instructions */
2156static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
2157{
2158 return (vext_check_isa_ill(s) &&
2159 vext_check_reg(s, a->rs2, false) &&
2160 vext_check_reg(s, a->rs1, false) &&
2161 (s->sew != 0) &&
2162 ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
2163 vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) ||
2164 (s->lmul == 0)));
2165}
2166
2167GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
2168GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check)
2169GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check)
2170GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check)
2171GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check)
2172
2173static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
2174{
2175 return (vext_check_isa_ill(s) &&
2176 vext_check_reg(s, a->rs2, false) &&
2177 (s->sew != 0) &&
2178 (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) ||
2179 (s->lmul == 0)));
2180}
2181
2182GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
2183GEN_OPFVF_TRANS(vmfne_vf, opfvf_cmp_check)
2184GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check)
2185GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check)
2186GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
2187GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
2188GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
121ddbb3
LZ		 2189
2190/* Vector Floating-Point Classify Instruction */
2191GEN_OPFV_TRANS(vfclass_v, opfv_check)
64ab5846
LZ		 2192
2193/* Vector Floating-Point Merge Instruction */
2194GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check)
2195
2196static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
2197{
2198 if (vext_check_isa_ill(s) &&
2199 vext_check_reg(s, a->rd, false) &&
2200 (s->sew != 0)) {
2201
2202 if (s->vl_eq_vlmax) {
2203 tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
2204 MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
2205 } else {
2206 TCGv_ptr dest;
2207 TCGv_i32 desc;
2208 uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
2209 static gen_helper_vmv_vx * const fns[3] = {
2210 gen_helper_vmv_v_x_h,
2211 gen_helper_vmv_v_x_w,
2212 gen_helper_vmv_v_x_d,
2213 };
2214 TCGLabel *over = gen_new_label();
2215 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
2216
2217 dest = tcg_temp_new_ptr();
2218 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
2219 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
2220 fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
2221
2222 tcg_temp_free_ptr(dest);
2223 tcg_temp_free_i32(desc);
2224 gen_set_label(over);
2225 }
2226 return true;
2227 }
2228 return false;
2229}
92100973
LZ		 2230
2231/* Single-Width Floating-Point/Integer Type-Convert Instructions */
2232GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check)
2233GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check)
2234GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check)
2235GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check)
4514b7b1
LZ		 2236
2237/* Widening Floating-Point/Integer Type-Convert Instructions */
2238
2239/*
2240 * If the current SEW does not correspond to a supported IEEE floating-point
2241 * type, an illegal instruction exception is raised
2242 */
2243static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
2244{
2245 return (vext_check_isa_ill(s) &&
2246 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
2247 vext_check_reg(s, a->rd, true) &&
2248 vext_check_reg(s, a->rs2, false) &&
2249 vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
2250 1 << s->lmul) &&
2251 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
2252}
2253
2254#define GEN_OPFV_WIDEN_TRANS(NAME) \
2255static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
2256{ \
2257 if (opfv_widen_check(s, a)) { \
2258 uint32_t data = 0; \
2259 static gen_helper_gvec_3_ptr * const fns[2] = { \
2260 gen_helper_##NAME##_h, \
2261 gen_helper_##NAME##_w, \
2262 }; \
2263 TCGLabel *over = gen_new_label(); \
2264 gen_set_rm(s, 7); \
2265 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
2266 \
2267 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
2268 data = FIELD_DP32(data, VDATA, VM, a->vm); \
2269 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2270 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2271 vreg_ofs(s, a->rs2), cpu_env, 0, \
2272 s->vlen / 8, data, fns[s->sew - 1]); \
2273 gen_set_label(over); \
2274 return true; \
2275 } \
2276 return false; \
2277}
2278
2279GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v)
2280GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v)
2281GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v)
2282GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v)
2283GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v)
878d406e
LZ		 2284
2285/* Narrowing Floating-Point/Integer Type-Convert Instructions */
2286
2287/*
2288 * If the current SEW does not correspond to a supported IEEE floating-point
2289 * type, an illegal instruction exception is raised
2290 */
2291static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
2292{
2293 return (vext_check_isa_ill(s) &&
2294 vext_check_overlap_mask(s, a->rd, a->vm, false) &&
2295 vext_check_reg(s, a->rd, false) &&
2296 vext_check_reg(s, a->rs2, true) &&
2297 vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
2298 2 << s->lmul) &&
2299 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
2300}
2301
2302#define GEN_OPFV_NARROW_TRANS(NAME) \
2303static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
2304{ \
2305 if (opfv_narrow_check(s, a)) { \
2306 uint32_t data = 0; \
2307 static gen_helper_gvec_3_ptr * const fns[2] = { \
2308 gen_helper_##NAME##_h, \
2309 gen_helper_##NAME##_w, \
2310 }; \
2311 TCGLabel *over = gen_new_label(); \
2312 gen_set_rm(s, 7); \
2313 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
2314 \
2315 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
2316 data = FIELD_DP32(data, VDATA, VM, a->vm); \
2317 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2318 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2319 vreg_ofs(s, a->rs2), cpu_env, 0, \
2320 s->vlen / 8, data, fns[s->sew - 1]); \
2321 gen_set_label(over); \
2322 return true; \
2323 } \
2324 return false; \
2325}
2326
2327GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v)
2328GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v)
2329GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v)
2330GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v)
2331GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v)
fe5c9ab1
LZ		 2332
2333/*
2334 *** Vector Reduction Operations
2335 */
2336/* Vector Single-Width Integer Reduction Instructions */
2337static bool reduction_check(DisasContext *s, arg_rmrr *a)
2338{
2339 return vext_check_isa_ill(s) && vext_check_reg(s, a->rs2, false);
2340}
2341
2342GEN_OPIVV_TRANS(vredsum_vs, reduction_check)
2343GEN_OPIVV_TRANS(vredmaxu_vs, reduction_check)
2344GEN_OPIVV_TRANS(vredmax_vs, reduction_check)
2345GEN_OPIVV_TRANS(vredminu_vs, reduction_check)
2346GEN_OPIVV_TRANS(vredmin_vs, reduction_check)
2347GEN_OPIVV_TRANS(vredand_vs, reduction_check)
2348GEN_OPIVV_TRANS(vredor_vs, reduction_check)
2349GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
bba71820
LZ		 2350
2351/* Vector Widening Integer Reduction Instructions */
2352GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check)
2353GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check)
523547f1
LZ		 2354
2355/* Vector Single-Width Floating-Point Reduction Instructions */
2356GEN_OPFVV_TRANS(vfredsum_vs, reduction_check)
2357GEN_OPFVV_TRANS(vfredmax_vs, reduction_check)
2358GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
696b0c26
LZ		 2359
2360/* Vector Widening Floating-Point Reduction Instructions */
2361GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
c21f34ae
LZ		 2362
2363/*
2364 *** Vector Mask Operations
2365 */
2366
2367/* Vector Mask-Register Logical Instructions */
2368#define GEN_MM_TRANS(NAME) \
2369static bool trans_##NAME(DisasContext *s, arg_r *a) \
2370{ \
2371 if (vext_check_isa_ill(s)) { \
2372 uint32_t data = 0; \
2373 gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
2374 TCGLabel *over = gen_new_label(); \
2375 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
2376 \
2377 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
2378 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2379 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2380 vreg_ofs(s, a->rs1), \
2381 vreg_ofs(s, a->rs2), cpu_env, 0, \
2382 s->vlen / 8, data, fn); \
2383 gen_set_label(over); \
2384 return true; \
2385 } \
2386 return false; \
2387}
2388
2389GEN_MM_TRANS(vmand_mm)
2390GEN_MM_TRANS(vmnand_mm)
2391GEN_MM_TRANS(vmandnot_mm)
2392GEN_MM_TRANS(vmxor_mm)
2393GEN_MM_TRANS(vmor_mm)
2394GEN_MM_TRANS(vmnor_mm)
2395GEN_MM_TRANS(vmornot_mm)
2396GEN_MM_TRANS(vmxnor_mm)
2e88f551
LZ		 2397
2398/* Vector mask population count vmpopc */
2399static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
2400{
2401 if (vext_check_isa_ill(s)) {
2402 TCGv_ptr src2, mask;
2403 TCGv dst;
2404 TCGv_i32 desc;
2405 uint32_t data = 0;
2406 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
2407 data = FIELD_DP32(data, VDATA, VM, a->vm);
2408 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
2409
2410 mask = tcg_temp_new_ptr();
2411 src2 = tcg_temp_new_ptr();
2412 dst = tcg_temp_new();
2413 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
2414
2415 tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
2416 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
2417
2418 gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc);
2419 gen_set_gpr(a->rd, dst);
2420
2421 tcg_temp_free_ptr(mask);
2422 tcg_temp_free_ptr(src2);
2423 tcg_temp_free(dst);
2424 tcg_temp_free_i32(desc);
2425 return true;
2426 }
2427 return false;
2428}
0db67e1c
LZ		 2429
2430/* vmfirst find-first-set mask bit */
2431static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
2432{
2433 if (vext_check_isa_ill(s)) {
2434 TCGv_ptr src2, mask;
2435 TCGv dst;
2436 TCGv_i32 desc;
2437 uint32_t data = 0;
2438 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
2439 data = FIELD_DP32(data, VDATA, VM, a->vm);
2440 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
2441
2442 mask = tcg_temp_new_ptr();
2443 src2 = tcg_temp_new_ptr();
2444 dst = tcg_temp_new();
2445 desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
2446
2447 tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
2448 tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
2449
2450 gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc);
2451 gen_set_gpr(a->rd, dst);
2452
2453 tcg_temp_free_ptr(mask);
2454 tcg_temp_free_ptr(src2);
2455 tcg_temp_free(dst);
2456 tcg_temp_free_i32(desc);
2457 return true;
2458 }
2459 return false;
2460}
81fbf7da
LZ		 2461
2462/* vmsbf.m set-before-first mask bit */
2463/* vmsif.m set-includ-first mask bit */
2464/* vmsof.m set-only-first mask bit */
2465#define GEN_M_TRANS(NAME) \
2466static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
2467{ \
2468 if (vext_check_isa_ill(s)) { \
2469 uint32_t data = 0; \
2470 gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
2471 TCGLabel *over = gen_new_label(); \
2472 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
2473 \
2474 data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
2475 data = FIELD_DP32(data, VDATA, VM, a->vm); \
2476 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2477 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
2478 vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
2479 cpu_env, 0, s->vlen / 8, data, fn); \
2480 gen_set_label(over); \
2481 return true; \
2482 } \
2483 return false; \
2484}
2485
2486GEN_M_TRANS(vmsbf_m)
2487GEN_M_TRANS(vmsif_m)
2488GEN_M_TRANS(vmsof_m)
78d90cfe
LZ		 2489
2490/* Vector Iota Instruction */
2491static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
2492{
2493 if (vext_check_isa_ill(s) &&
2494 vext_check_reg(s, a->rd, false) &&
2495 vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, 1) &&
2496 (a->vm != 0 || a->rd != 0)) {
2497 uint32_t data = 0;
2498 TCGLabel *over = gen_new_label();
2499 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
2500
2501 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
2502 data = FIELD_DP32(data, VDATA, VM, a->vm);
2503 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
2504 static gen_helper_gvec_3_ptr * const fns[4] = {
2505 gen_helper_viota_m_b, gen_helper_viota_m_h,
2506 gen_helper_viota_m_w, gen_helper_viota_m_d,
2507 };
2508 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
2509 vreg_ofs(s, a->rs2), cpu_env, 0,
2510 s->vlen / 8, data, fns[s->sew]);
2511 gen_set_label(over);
2512 return true;
2513 }
2514 return false;
2515}
126bec3f
LZ		 2516
2517/* Vector Element Index Instruction */
2518static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
2519{
2520 if (vext_check_isa_ill(s) &&
2521 vext_check_reg(s, a->rd, false) &&
2522 vext_check_overlap_mask(s, a->rd, a->vm, false)) {
2523 uint32_t data = 0;
2524 TCGLabel *over = gen_new_label();
2525 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
2526
2527 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
2528 data = FIELD_DP32(data, VDATA, VM, a->vm);
2529 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
2530 static gen_helper_gvec_2_ptr * const fns[4] = {
2531 gen_helper_vid_v_b, gen_helper_vid_v_h,
2532 gen_helper_vid_v_w, gen_helper_vid_v_d,
2533 };
2534 tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
2535 cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
2536 gen_set_label(over);
2537 return true;
2538 }
2539 return false;
2540}
90355f39
LZ		 2541
2542/*
2543 *** Vector Permutation Instructions
2544 */
2545
2546/* Integer Extract Instruction */
2547
2548static void load_element(TCGv_i64 dest, TCGv_ptr base,
2549 int ofs, int sew)
2550{
2551 switch (sew) {
2552 case MO_8:
2553 tcg_gen_ld8u_i64(dest, base, ofs);
2554 break;
2555 case MO_16:
2556 tcg_gen_ld16u_i64(dest, base, ofs);
2557 break;
2558 case MO_32:
2559 tcg_gen_ld32u_i64(dest, base, ofs);
2560 break;
2561 case MO_64:
2562 tcg_gen_ld_i64(dest, base, ofs);
2563 break;
2564 default:
2565 g_assert_not_reached();
2566 break;
2567 }
2568}
2569
2570/* offset of the idx element with base regsiter r */
2571static uint32_t endian_ofs(DisasContext *s, int r, int idx)
2572{
2573#ifdef HOST_WORDS_BIGENDIAN
2574 return vreg_ofs(s, r) + ((idx ^ (7 >> s->sew)) << s->sew);
2575#else
2576 return vreg_ofs(s, r) + (idx << s->sew);
2577#endif
2578}
2579
2580/* adjust the index according to the endian */
2581static void endian_adjust(TCGv_i32 ofs, int sew)
2582{
2583#ifdef HOST_WORDS_BIGENDIAN
2584 tcg_gen_xori_i32(ofs, ofs, 7 >> sew);
2585#endif
2586}
2587
2588/* Load idx >= VLMAX ? 0 : vreg[idx] */
2589static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
2590 int vreg, TCGv idx, int vlmax)
2591{
2592 TCGv_i32 ofs = tcg_temp_new_i32();
2593 TCGv_ptr base = tcg_temp_new_ptr();
2594 TCGv_i64 t_idx = tcg_temp_new_i64();
2595 TCGv_i64 t_vlmax, t_zero;
2596
2597 /*
2598 * Mask the index to the length so that we do
2599 * not produce an out-of-range load.
2600 */
2601 tcg_gen_trunc_tl_i32(ofs, idx);
2602 tcg_gen_andi_i32(ofs, ofs, vlmax - 1);
2603
2604 /* Convert the index to an offset. */
2605 endian_adjust(ofs, s->sew);
2606 tcg_gen_shli_i32(ofs, ofs, s->sew);
2607
2608 /* Convert the index to a pointer. */
2609 tcg_gen_ext_i32_ptr(base, ofs);
2610 tcg_gen_add_ptr(base, base, cpu_env);
2611
2612 /* Perform the load. */
2613 load_element(dest, base,
2614 vreg_ofs(s, vreg), s->sew);
2615 tcg_temp_free_ptr(base);
2616 tcg_temp_free_i32(ofs);
2617
2618 /* Flush out-of-range indexing to zero. */
2619 t_vlmax = tcg_const_i64(vlmax);
2620 t_zero = tcg_const_i64(0);
2621 tcg_gen_extu_tl_i64(t_idx, idx);
2622
2623 tcg_gen_movcond_i64(TCG_COND_LTU, dest, t_idx,
2624 t_vlmax, dest, t_zero);
2625
2626 tcg_temp_free_i64(t_vlmax);
2627 tcg_temp_free_i64(t_zero);
2628 tcg_temp_free_i64(t_idx);
2629}
2630
2631static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
2632 int vreg, int idx)
2633{
2634 load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew);
2635}
2636
2637static bool trans_vext_x_v(DisasContext *s, arg_r *a)
2638{
2639 TCGv_i64 tmp = tcg_temp_new_i64();
2640 TCGv dest = tcg_temp_new();
2641
2642 if (a->rs1 == 0) {
2643 /* Special case vmv.x.s rd, vs2. */
2644 vec_element_loadi(s, tmp, a->rs2, 0);
2645 } else {
2646 /* This instruction ignores LMUL and vector register groups */
2647 int vlmax = s->vlen >> (3 + s->sew);
2648 vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax);
2649 }
2650 tcg_gen_trunc_i64_tl(dest, tmp);
2651 gen_set_gpr(a->rd, dest);
2652
2653 tcg_temp_free(dest);
2654 tcg_temp_free_i64(tmp);
2655 return true;
2656}
9fc08be6
LZ		 2657
2658/* Integer Scalar Move Instruction */
2659
2660static void store_element(TCGv_i64 val, TCGv_ptr base,
2661 int ofs, int sew)
2662{
2663 switch (sew) {
2664 case MO_8:
2665 tcg_gen_st8_i64(val, base, ofs);
2666 break;
2667 case MO_16:
2668 tcg_gen_st16_i64(val, base, ofs);
2669 break;
2670 case MO_32:
2671 tcg_gen_st32_i64(val, base, ofs);
2672 break;
2673 case MO_64:
2674 tcg_gen_st_i64(val, base, ofs);
2675 break;
2676 default:
2677 g_assert_not_reached();
2678 break;
2679 }
2680}
2681
2682/*
2683 * Store vreg[idx] = val.
2684 * The index must be in range of VLMAX.
2685 */
2686static void vec_element_storei(DisasContext *s, int vreg,
2687 int idx, TCGv_i64 val)
2688{
2689 store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew);
2690}
2691
2692/* vmv.s.x vd, rs1 # vd[0] = rs1 */
2693static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
2694{
2695 if (vext_check_isa_ill(s)) {
2696 /* This instruction ignores LMUL and vector register groups */
2697 int maxsz = s->vlen >> 3;
2698 TCGv_i64 t1;
2699 TCGLabel *over = gen_new_label();
2700
2701 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
2702 tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0);
2703 if (a->rs1 == 0) {
2704 goto done;
2705 }
2706
2707 t1 = tcg_temp_new_i64();
2708 tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
2709 vec_element_storei(s, a->rd, 0, t1);
2710 tcg_temp_free_i64(t1);
2711 done:
2712 gen_set_label(over);
2713 return true;
2714 }
2715 return false;
2716}
2843420a
LZ		 2717
2718/* Floating-Point Scalar Move Instructions */
2719static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
2720{
2721 if (!s->vill && has_ext(s, RVF) &&
2722 (s->mstatus_fs != 0) && (s->sew != 0)) {
2723 unsigned int len = 8 << s->sew;
2724
2725 vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0);
2726 if (len < 64) {
2727 tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
2728 MAKE_64BIT_MASK(len, 64 - len));
2729 }
2730
2731 mark_fs_dirty(s);
2732 return true;
2733 }
2734 return false;
2735}
2736
2737/* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */
2738static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
2739{
2740 if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) {
2741 TCGv_i64 t1;
2742 /* The instructions ignore LMUL and vector register group. */
2743 uint32_t vlmax = s->vlen >> 3;
2744
2745 /* if vl == 0, skip vector register write back */
2746 TCGLabel *over = gen_new_label();
2747 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
2748
2749 /* zeroed all elements */
2750 tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0);
2751
2752 /* NaN-box f[rs1] as necessary for SEW */
2753 t1 = tcg_temp_new_i64();
2754 if (s->sew == MO_64 && !has_ext(s, RVD)) {
2755 tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32));
2756 } else {
2757 tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]);
2758 }
2759 vec_element_storei(s, a->rd, 0, t1);
2760 tcg_temp_free_i64(t1);
2761 gen_set_label(over);
2762 return true;
2763 }
2764 return false;
2765}
ec17e036
LZ		 2766
2767/* Vector Slide Instructions */
2768static bool slideup_check(DisasContext *s, arg_rmrr *a)
2769{
2770 return (vext_check_isa_ill(s) &&
2771 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
2772 vext_check_reg(s, a->rd, false) &&
2773 vext_check_reg(s, a->rs2, false) &&
2774 (a->rd != a->rs2));
2775}
2776
2777GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
2778GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
2779GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
2780
2781GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
2782GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
2783GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
e4b83d5c
LZ		 2784
2785/* Vector Register Gather Instruction */
2786static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
2787{
2788 return (vext_check_isa_ill(s) &&
2789 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
2790 vext_check_reg(s, a->rd, false) &&
2791 vext_check_reg(s, a->rs1, false) &&
2792 vext_check_reg(s, a->rs2, false) &&
2793 (a->rd != a->rs2) && (a->rd != a->rs1));
2794}
2795
2796GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check)
2797
2798static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a)
2799{
2800 return (vext_check_isa_ill(s) &&
2801 vext_check_overlap_mask(s, a->rd, a->vm, true) &&
2802 vext_check_reg(s, a->rd, false) &&
2803 vext_check_reg(s, a->rs2, false) &&
2804 (a->rd != a->rs2));
2805}
2806
2807/* vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
2808static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
2809{
2810 if (!vrgather_vx_check(s, a)) {
2811 return false;
2812 }
2813
2814 if (a->vm && s->vl_eq_vlmax) {
2815 int vlmax = s->vlen / s->mlen;
2816 TCGv_i64 dest = tcg_temp_new_i64();
2817
2818 if (a->rs1 == 0) {
2819 vec_element_loadi(s, dest, a->rs2, 0);
2820 } else {
2821 vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax);
2822 }
2823
2824 tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
2825 MAXSZ(s), MAXSZ(s), dest);
2826 tcg_temp_free_i64(dest);
2827 } else {
2828 static gen_helper_opivx * const fns[4] = {
2829 gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
2830 gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d
2831 };
2832 return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);
2833 }
2834 return true;
2835}
2836
2837/* vrgather.vi vd, vs2, imm, vm # vd[i] = (imm >= VLMAX) ? 0 : vs2[imm] */
2838static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
2839{
2840 if (!vrgather_vx_check(s, a)) {
2841 return false;
2842 }
2843
2844 if (a->vm && s->vl_eq_vlmax) {
2845 if (a->rs1 >= s->vlen / s->mlen) {
2846 tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd),
2847 MAXSZ(s), MAXSZ(s), 0);
2848 } else {
2849 tcg_gen_gvec_dup_mem(s->sew, vreg_ofs(s, a->rd),
2850 endian_ofs(s, a->rs2, a->rs1),
2851 MAXSZ(s), MAXSZ(s));
2852 }
2853 } else {
2854 static gen_helper_opivx * const fns[4] = {
2855 gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
2856 gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d
2857 };
2858 return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s, 1);
2859 }
2860 return true;
2861}
31bf42a2
LZ		 2862
2863/* Vector Compress Instruction */
2864static bool vcompress_vm_check(DisasContext *s, arg_r *a)
2865{
2866 return (vext_check_isa_ill(s) &&
2867 vext_check_reg(s, a->rd, false) &&
2868 vext_check_reg(s, a->rs2, false) &&
2869 vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs1, 1) &&
2870 (a->rd != a->rs2));
2871}
2872
2873static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
2874{
2875 if (vcompress_vm_check(s, a)) {
2876 uint32_t data = 0;
2877 static gen_helper_gvec_4_ptr * const fns[4] = {
2878 gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h,
2879 gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d,
2880 };
2881 TCGLabel *over = gen_new_label();
2882 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
2883
2884 data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
2885 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
2886 tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
2887 vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
2888 cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
2889 gen_set_label(over);
2890 return true;
2891 }
2892 return false;
2893}
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