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a4633e16 AF |
1 | /* |
2 | * QEMU Xtensa CPU | |
3 | * | |
5087a72c | 4 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. |
a4633e16 AF |
5 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
6 | * All rights reserved. | |
7 | * | |
8 | * Redistribution and use in source and binary forms, with or without | |
9 | * modification, are permitted provided that the following conditions are met: | |
10 | * * Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | |
12 | * * Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in the | |
14 | * documentation and/or other materials provided with the distribution. | |
15 | * * Neither the name of the Open Source and Linux Lab nor the | |
16 | * names of its contributors may be used to endorse or promote products | |
17 | * derived from this software without specific prior written permission. | |
18 | * | |
19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
23 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
26 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
29 | */ | |
30 | ||
09aae23d | 31 | #include "qemu/osdep.h" |
da34e65c | 32 | #include "qapi/error.h" |
15be3171 | 33 | #include "cpu.h" |
cfa9f051 | 34 | #include "fpu/softfloat.h" |
0b8fa32f | 35 | #include "qemu/module.h" |
004a5690 | 36 | #include "migration/vmstate.h" |
9e377be1 | 37 | #include "hw/qdev-clock.h" |
9585201a PMD |
38 | #ifndef CONFIG_USER_ONLY |
39 | #include "exec/memory.h" | |
40 | #endif | |
a4633e16 AF |
41 | |
42 | ||
f45748f1 AF |
43 | static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) |
44 | { | |
45 | XtensaCPU *cpu = XTENSA_CPU(cs); | |
46 | ||
47 | cpu->env.pc = value; | |
48 | } | |
49 | ||
e4fdf9df RH |
50 | static vaddr xtensa_cpu_get_pc(CPUState *cs) |
51 | { | |
52 | XtensaCPU *cpu = XTENSA_CPU(cs); | |
53 | ||
54 | return cpu->env.pc; | |
55 | } | |
56 | ||
044dcfc5 RH |
57 | static void xtensa_restore_state_to_opc(CPUState *cs, |
58 | const TranslationBlock *tb, | |
59 | const uint64_t *data) | |
60 | { | |
61 | XtensaCPU *cpu = XTENSA_CPU(cs); | |
62 | ||
63 | cpu->env.pc = data[0]; | |
64 | } | |
65 | ||
8c2e1b00 AF |
66 | static bool xtensa_cpu_has_work(CPUState *cs) |
67 | { | |
ba7651fb | 68 | #ifndef CONFIG_USER_ONLY |
8c2e1b00 AF |
69 | XtensaCPU *cpu = XTENSA_CPU(cs); |
70 | ||
bd527a83 | 71 | return !cpu->env.runstall && cpu->env.pending_irq_level; |
ba7651fb MF |
72 | #else |
73 | return true; | |
74 | #endif | |
8c2e1b00 AF |
75 | } |
76 | ||
130ea832 MF |
77 | #ifdef CONFIG_USER_ONLY |
78 | static bool abi_call0; | |
79 | ||
80 | void xtensa_set_abi_call0(void) | |
81 | { | |
82 | abi_call0 = true; | |
83 | } | |
84 | ||
85 | bool xtensa_abi_call0(void) | |
86 | { | |
87 | return abi_call0; | |
88 | } | |
89 | #endif | |
90 | ||
d66e64dd | 91 | static void xtensa_cpu_reset_hold(Object *obj) |
a4633e16 | 92 | { |
d66e64dd | 93 | CPUState *s = CPU(obj); |
a4633e16 AF |
94 | XtensaCPU *cpu = XTENSA_CPU(s); |
95 | XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); | |
96 | CPUXtensaState *env = &cpu->env; | |
cfa9f051 MF |
97 | bool dfpu = xtensa_option_enabled(env->config, |
98 | XTENSA_OPTION_DFP_COPROCESSOR); | |
a4633e16 | 99 | |
d66e64dd PM |
100 | if (xcc->parent_phases.hold) { |
101 | xcc->parent_phases.hold(obj); | |
102 | } | |
a4633e16 | 103 | |
17ab14ac | 104 | env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors]; |
5087a72c | 105 | env->sregs[LITBASE] &= ~1; |
ba7651fb | 106 | #ifndef CONFIG_USER_ONLY |
5087a72c AF |
107 | env->sregs[PS] = xtensa_option_enabled(env->config, |
108 | XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; | |
ba7651fb MF |
109 | env->pending_irq_level = 0; |
110 | #else | |
130ea832 MF |
111 | env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT); |
112 | if (xtensa_option_enabled(env->config, | |
113 | XTENSA_OPTION_WINDOWED_REGISTER) && | |
114 | !xtensa_abi_call0()) { | |
115 | env->sregs[PS] |= PS_WOE; | |
116 | } | |
ab97f050 | 117 | env->sregs[CPENABLE] = 0xff; |
ba7651fb | 118 | #endif |
5087a72c AF |
119 | env->sregs[VECBASE] = env->config->vecbase; |
120 | env->sregs[IBREAKENABLE] = 0; | |
9e03ade4 | 121 | env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask; |
fcc803d1 MF |
122 | env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, |
123 | XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; | |
604e1f9c MF |
124 | env->sregs[CONFIGID0] = env->config->configid[0]; |
125 | env->sregs[CONFIGID1] = env->config->configid[1]; | |
b345e140 | 126 | env->exclusive_addr = -1; |
5087a72c | 127 | |
ba7651fb | 128 | #ifndef CONFIG_USER_ONLY |
5087a72c | 129 | reset_mmu(env); |
bd527a83 | 130 | s->halted = env->runstall; |
ba7651fb | 131 | #endif |
cfa9f051 MF |
132 | set_no_signaling_nans(!dfpu, &env->fp_status); |
133 | set_use_first_nan(!dfpu, &env->fp_status); | |
a4633e16 AF |
134 | } |
135 | ||
67cce561 AF |
136 | static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) |
137 | { | |
138 | ObjectClass *oc; | |
139 | char *typename; | |
140 | ||
a5247d76 | 141 | typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model); |
67cce561 AF |
142 | oc = object_class_by_name(typename); |
143 | g_free(typename); | |
d5be19f5 | 144 | |
67cce561 AF |
145 | return oc; |
146 | } | |
147 | ||
5a6539e6 MF |
148 | static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) |
149 | { | |
150 | XtensaCPU *cpu = XTENSA_CPU(cs); | |
151 | ||
152 | info->private_data = cpu->env.config->isa; | |
153 | info->print_insn = print_insn_xtensa; | |
154 | } | |
155 | ||
5f6c9643 AF |
156 | static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) |
157 | { | |
a0e372f0 | 158 | CPUState *cs = CPU(dev); |
5f6c9643 | 159 | XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev); |
ce5b1bbf LV |
160 | Error *local_err = NULL; |
161 | ||
ba7651fb MF |
162 | #ifndef CONFIG_USER_ONLY |
163 | xtensa_irq_init(&XTENSA_CPU(dev)->env); | |
164 | #endif | |
8e36271b | 165 | |
ce5b1bbf LV |
166 | cpu_exec_realizefn(cs, &local_err); |
167 | if (local_err != NULL) { | |
168 | error_propagate(errp, local_err); | |
169 | return; | |
170 | } | |
5f6c9643 | 171 | |
a0e372f0 AF |
172 | cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs; |
173 | ||
14a10fc3 AF |
174 | qemu_init_vcpu(cs); |
175 | ||
5f6c9643 AF |
176 | xcc->parent_realize(dev, errp); |
177 | } | |
178 | ||
e554bbc6 AF |
179 | static void xtensa_cpu_initfn(Object *obj) |
180 | { | |
181 | XtensaCPU *cpu = XTENSA_CPU(obj); | |
67cce561 | 182 | XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); |
e554bbc6 AF |
183 | CPUXtensaState *env = &cpu->env; |
184 | ||
67cce561 | 185 | env->config = xcc->config; |
25733ead | 186 | |
ba7651fb | 187 | #ifndef CONFIG_USER_ONLY |
3a3c9dc4 MF |
188 | env->address_space_er = g_malloc(sizeof(*env->address_space_er)); |
189 | env->system_er = g_malloc(sizeof(*env->system_er)); | |
09d98b69 | 190 | memory_region_init_io(env->system_er, obj, NULL, env, "er", |
3a3c9dc4 MF |
191 | UINT64_C(0x100000000)); |
192 | address_space_init(env->address_space_er, env->system_er, "ER"); | |
9e377be1 MF |
193 | |
194 | cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0); | |
195 | clock_set_hz(cpu->clock, env->config->clock_freq_khz * 1000); | |
ba7651fb | 196 | #endif |
e554bbc6 AF |
197 | } |
198 | ||
9e377be1 MF |
199 | XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk) |
200 | { | |
201 | DeviceState *cpu; | |
202 | ||
203 | cpu = DEVICE(object_new(cpu_type)); | |
204 | qdev_connect_clock_in(cpu, "clk-in", cpu_refclk); | |
205 | qdev_realize(cpu, NULL, &error_abort); | |
206 | ||
207 | return XTENSA_CPU(cpu); | |
208 | } | |
209 | ||
4336073b | 210 | #ifndef CONFIG_USER_ONLY |
004a5690 AF |
211 | static const VMStateDescription vmstate_xtensa_cpu = { |
212 | .name = "cpu", | |
213 | .unmigratable = 1, | |
214 | }; | |
8b80bd28 PMD |
215 | |
216 | #include "hw/core/sysemu-cpu-ops.h" | |
217 | ||
218 | static const struct SysemuCPUOps xtensa_sysemu_ops = { | |
08928c6d | 219 | .get_phys_page_debug = xtensa_cpu_get_phys_page_debug, |
8b80bd28 | 220 | }; |
4336073b | 221 | #endif |
004a5690 | 222 | |
78271684 CF |
223 | #include "hw/core/tcg-cpu-ops.h" |
224 | ||
1764ad70 | 225 | static const TCGCPUOps xtensa_tcg_ops = { |
78271684 | 226 | .initialize = xtensa_translate_init, |
78271684 | 227 | .debug_excp_handler = xtensa_breakpoint_handler, |
044dcfc5 | 228 | .restore_state_to_opc = xtensa_restore_state_to_opc, |
78271684 CF |
229 | |
230 | #ifndef CONFIG_USER_ONLY | |
6407f64f | 231 | .tlb_fill = xtensa_cpu_tlb_fill, |
f364a7f9 | 232 | .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, |
78271684 CF |
233 | .do_interrupt = xtensa_cpu_do_interrupt, |
234 | .do_transaction_failed = xtensa_cpu_do_transaction_failed, | |
235 | .do_unaligned_access = xtensa_cpu_do_unaligned_access, | |
5f3ebbc8 | 236 | .debug_check_breakpoint = xtensa_debug_check_breakpoint, |
78271684 CF |
237 | #endif /* !CONFIG_USER_ONLY */ |
238 | }; | |
239 | ||
a4633e16 AF |
240 | static void xtensa_cpu_class_init(ObjectClass *oc, void *data) |
241 | { | |
004a5690 | 242 | DeviceClass *dc = DEVICE_CLASS(oc); |
a4633e16 AF |
243 | CPUClass *cc = CPU_CLASS(oc); |
244 | XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc); | |
d66e64dd | 245 | ResettableClass *rc = RESETTABLE_CLASS(oc); |
a4633e16 | 246 | |
bf853881 PMD |
247 | device_class_set_parent_realize(dc, xtensa_cpu_realizefn, |
248 | &xcc->parent_realize); | |
5f6c9643 | 249 | |
d66e64dd PM |
250 | resettable_class_set_parent_phases(rc, NULL, xtensa_cpu_reset_hold, NULL, |
251 | &xcc->parent_phases); | |
004a5690 | 252 | |
67cce561 | 253 | cc->class_by_name = xtensa_cpu_class_by_name; |
8c2e1b00 | 254 | cc->has_work = xtensa_cpu_has_work; |
878096ee | 255 | cc->dump_state = xtensa_cpu_dump_state; |
f45748f1 | 256 | cc->set_pc = xtensa_cpu_set_pc; |
e4fdf9df | 257 | cc->get_pc = xtensa_cpu_get_pc; |
5b50e790 AF |
258 | cc->gdb_read_register = xtensa_cpu_gdb_read_register; |
259 | cc->gdb_write_register = xtensa_cpu_gdb_write_register; | |
2472b6c0 | 260 | cc->gdb_stop_before_watchpoint = true; |
b008c456 | 261 | #ifndef CONFIG_USER_ONLY |
8b80bd28 | 262 | cc->sysemu_ops = &xtensa_sysemu_ops; |
4336073b | 263 | dc->vmsd = &vmstate_xtensa_cpu; |
00b941e5 | 264 | #endif |
5a6539e6 | 265 | cc->disas_set_info = xtensa_cpu_disas_set_info; |
78271684 | 266 | cc->tcg_ops = &xtensa_tcg_ops; |
a4633e16 AF |
267 | } |
268 | ||
269 | static const TypeInfo xtensa_cpu_type_info = { | |
270 | .name = TYPE_XTENSA_CPU, | |
271 | .parent = TYPE_CPU, | |
272 | .instance_size = sizeof(XtensaCPU), | |
f669c992 | 273 | .instance_align = __alignof(XtensaCPU), |
e554bbc6 | 274 | .instance_init = xtensa_cpu_initfn, |
67cce561 | 275 | .abstract = true, |
a4633e16 AF |
276 | .class_size = sizeof(XtensaCPUClass), |
277 | .class_init = xtensa_cpu_class_init, | |
278 | }; | |
279 | ||
280 | static void xtensa_cpu_register_types(void) | |
281 | { | |
282 | type_register_static(&xtensa_cpu_type_info); | |
283 | } | |
284 | ||
285 | type_init(xtensa_cpu_register_types) |