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CommitLineData
8f2e8c07
KB
1/*
2 * Optimizations for Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2010 Samsung Electronics.
5 * Contributed by Kirill Batuzov <batuzovk@ispras.ru>
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
757e725b 26#include "qemu/osdep.h"
00f6da6a 27#include "exec/cpu-common.h"
8f2e8c07
KB
28#include "tcg-op.h"
29
8f2e8c07
KB
30#define CASE_OP_32_64(x) \
31 glue(glue(case INDEX_op_, x), _i32): \
32 glue(glue(case INDEX_op_, x), _i64)
8f2e8c07 33
170ba88f
RH
34#define CASE_OP_32_64_VEC(x) \
35 glue(glue(case INDEX_op_, x), _i32): \
36 glue(glue(case INDEX_op_, x), _i64): \
37 glue(glue(case INDEX_op_, x), _vec)
38
22613af4 39struct tcg_temp_info {
b41059dd 40 bool is_const;
6349039d
RH
41 TCGTemp *prev_copy;
42 TCGTemp *next_copy;
22613af4 43 tcg_target_ulong val;
3a9d8b17 44 tcg_target_ulong mask;
22613af4
KB
45};
46
6349039d 47static inline struct tcg_temp_info *ts_info(TCGTemp *ts)
d9c769c6 48{
6349039d 49 return ts->state_ptr;
d9c769c6
AJ
50}
51
6349039d 52static inline struct tcg_temp_info *arg_info(TCGArg arg)
d9c769c6 53{
6349039d
RH
54 return ts_info(arg_temp(arg));
55}
56
57static inline bool ts_is_const(TCGTemp *ts)
58{
59 return ts_info(ts)->is_const;
60}
61
62static inline bool arg_is_const(TCGArg arg)
63{
64 return ts_is_const(arg_temp(arg));
65}
66
67static inline bool ts_is_copy(TCGTemp *ts)
68{
69 return ts_info(ts)->next_copy != ts;
d9c769c6
AJ
70}
71
b41059dd 72/* Reset TEMP's state, possibly removing the temp for the list of copies. */
6349039d
RH
73static void reset_ts(TCGTemp *ts)
74{
75 struct tcg_temp_info *ti = ts_info(ts);
76 struct tcg_temp_info *pi = ts_info(ti->prev_copy);
77 struct tcg_temp_info *ni = ts_info(ti->next_copy);
78
79 ni->prev_copy = ti->prev_copy;
80 pi->next_copy = ti->next_copy;
81 ti->next_copy = ts;
82 ti->prev_copy = ts;
83 ti->is_const = false;
84 ti->mask = -1;
85}
86
87static void reset_temp(TCGArg arg)
22613af4 88{
6349039d 89 reset_ts(arg_temp(arg));
22613af4
KB
90}
91
1208d7dd 92/* Initialize and activate a temporary. */
34184b07
EC
93static void init_ts_info(struct tcg_temp_info *infos,
94 TCGTempSet *temps_used, TCGTemp *ts)
1208d7dd 95{
6349039d 96 size_t idx = temp_idx(ts);
34184b07
EC
97 if (!test_bit(idx, temps_used->l)) {
98 struct tcg_temp_info *ti = &infos[idx];
6349039d
RH
99
100 ts->state_ptr = ti;
101 ti->next_copy = ts;
102 ti->prev_copy = ts;
103 ti->is_const = false;
104 ti->mask = -1;
34184b07 105 set_bit(idx, temps_used->l);
1208d7dd
AJ
106 }
107}
108
34184b07
EC
109static void init_arg_info(struct tcg_temp_info *infos,
110 TCGTempSet *temps_used, TCGArg arg)
6349039d 111{
34184b07 112 init_ts_info(infos, temps_used, arg_temp(arg));
6349039d
RH
113}
114
6349039d 115static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts)
e590d4e6 116{
6349039d 117 TCGTemp *i;
e590d4e6
AJ
118
119 /* If this is already a global, we can't do better. */
fa477d25 120 if (ts->temp_global) {
6349039d 121 return ts;
e590d4e6
AJ
122 }
123
124 /* Search for a global first. */
6349039d
RH
125 for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) {
126 if (i->temp_global) {
e590d4e6
AJ
127 return i;
128 }
129 }
130
131 /* If it is a temp, search for a temp local. */
fa477d25 132 if (!ts->temp_local) {
6349039d
RH
133 for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) {
134 if (ts->temp_local) {
e590d4e6
AJ
135 return i;
136 }
137 }
138 }
139
140 /* Failure to find a better representation, return the same temp. */
6349039d 141 return ts;
e590d4e6
AJ
142}
143
6349039d 144static bool ts_are_copies(TCGTemp *ts1, TCGTemp *ts2)
e590d4e6 145{
6349039d 146 TCGTemp *i;
e590d4e6 147
6349039d 148 if (ts1 == ts2) {
e590d4e6
AJ
149 return true;
150 }
151
6349039d 152 if (!ts_is_copy(ts1) || !ts_is_copy(ts2)) {
e590d4e6
AJ
153 return false;
154 }
155
6349039d
RH
156 for (i = ts_info(ts1)->next_copy; i != ts1; i = ts_info(i)->next_copy) {
157 if (i == ts2) {
e590d4e6
AJ
158 return true;
159 }
160 }
161
162 return false;
163}
164
6349039d
RH
165static bool args_are_copies(TCGArg arg1, TCGArg arg2)
166{
167 return ts_are_copies(arg_temp(arg1), arg_temp(arg2));
168}
169
acd93701 170static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val)
97a79eb7 171{
170ba88f
RH
172 const TCGOpDef *def;
173 TCGOpcode new_op;
97a79eb7 174 tcg_target_ulong mask;
6349039d 175 struct tcg_temp_info *di = arg_info(dst);
97a79eb7 176
170ba88f
RH
177 def = &tcg_op_defs[op->opc];
178 if (def->flags & TCG_OPF_VECTOR) {
179 new_op = INDEX_op_dupi_vec;
180 } else if (def->flags & TCG_OPF_64BIT) {
181 new_op = INDEX_op_movi_i64;
182 } else {
183 new_op = INDEX_op_movi_i32;
184 }
97a79eb7 185 op->opc = new_op;
170ba88f
RH
186 /* TCGOP_VECL and TCGOP_VECE remain unchanged. */
187 op->args[0] = dst;
188 op->args[1] = val;
97a79eb7
AJ
189
190 reset_temp(dst);
6349039d
RH
191 di->is_const = true;
192 di->val = val;
97a79eb7 193 mask = val;
96152126 194 if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_movi_i32) {
97a79eb7
AJ
195 /* High bits of the destination are now garbage. */
196 mask |= ~0xffffffffull;
197 }
6349039d 198 di->mask = mask;
97a79eb7
AJ
199}
200
acd93701 201static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
22613af4 202{
6349039d
RH
203 TCGTemp *dst_ts = arg_temp(dst);
204 TCGTemp *src_ts = arg_temp(src);
170ba88f 205 const TCGOpDef *def;
6349039d
RH
206 struct tcg_temp_info *di;
207 struct tcg_temp_info *si;
208 tcg_target_ulong mask;
209 TCGOpcode new_op;
210
211 if (ts_are_copies(dst_ts, src_ts)) {
5365718a
AJ
212 tcg_op_remove(s, op);
213 return;
214 }
215
6349039d
RH
216 reset_ts(dst_ts);
217 di = ts_info(dst_ts);
218 si = ts_info(src_ts);
170ba88f
RH
219 def = &tcg_op_defs[op->opc];
220 if (def->flags & TCG_OPF_VECTOR) {
221 new_op = INDEX_op_mov_vec;
222 } else if (def->flags & TCG_OPF_64BIT) {
223 new_op = INDEX_op_mov_i64;
224 } else {
225 new_op = INDEX_op_mov_i32;
226 }
c45cb8bb 227 op->opc = new_op;
170ba88f 228 /* TCGOP_VECL and TCGOP_VECE remain unchanged. */
6349039d
RH
229 op->args[0] = dst;
230 op->args[1] = src;
a62f6f56 231
6349039d 232 mask = si->mask;
24666baf
RH
233 if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) {
234 /* High bits of the destination are now garbage. */
235 mask |= ~0xffffffffull;
236 }
6349039d 237 di->mask = mask;
e590d4e6 238
6349039d
RH
239 if (src_ts->type == dst_ts->type) {
240 struct tcg_temp_info *ni = ts_info(si->next_copy);
241
242 di->next_copy = si->next_copy;
243 di->prev_copy = src_ts;
244 ni->prev_copy = dst_ts;
245 si->next_copy = dst_ts;
246 di->is_const = si->is_const;
247 di->val = si->val;
248 }
22613af4
KB
249}
250
fe0de7aa 251static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y)
53108fb5 252{
03271524
RH
253 uint64_t l64, h64;
254
53108fb5
KB
255 switch (op) {
256 CASE_OP_32_64(add):
257 return x + y;
258
259 CASE_OP_32_64(sub):
260 return x - y;
261
262 CASE_OP_32_64(mul):
263 return x * y;
264
9a81090b
KB
265 CASE_OP_32_64(and):
266 return x & y;
267
268 CASE_OP_32_64(or):
269 return x | y;
270
271 CASE_OP_32_64(xor):
272 return x ^ y;
273
55c0975c 274 case INDEX_op_shl_i32:
50c5c4d1 275 return (uint32_t)x << (y & 31);
55c0975c 276
55c0975c 277 case INDEX_op_shl_i64:
50c5c4d1 278 return (uint64_t)x << (y & 63);
55c0975c
KB
279
280 case INDEX_op_shr_i32:
50c5c4d1 281 return (uint32_t)x >> (y & 31);
55c0975c 282
55c0975c 283 case INDEX_op_shr_i64:
50c5c4d1 284 return (uint64_t)x >> (y & 63);
55c0975c
KB
285
286 case INDEX_op_sar_i32:
50c5c4d1 287 return (int32_t)x >> (y & 31);
55c0975c 288
55c0975c 289 case INDEX_op_sar_i64:
50c5c4d1 290 return (int64_t)x >> (y & 63);
55c0975c
KB
291
292 case INDEX_op_rotr_i32:
50c5c4d1 293 return ror32(x, y & 31);
55c0975c 294
55c0975c 295 case INDEX_op_rotr_i64:
50c5c4d1 296 return ror64(x, y & 63);
55c0975c
KB
297
298 case INDEX_op_rotl_i32:
50c5c4d1 299 return rol32(x, y & 31);
55c0975c 300
55c0975c 301 case INDEX_op_rotl_i64:
50c5c4d1 302 return rol64(x, y & 63);
25c4d9cc
RH
303
304 CASE_OP_32_64(not):
a640f031 305 return ~x;
25c4d9cc 306
cb25c80a
RH
307 CASE_OP_32_64(neg):
308 return -x;
309
310 CASE_OP_32_64(andc):
311 return x & ~y;
312
313 CASE_OP_32_64(orc):
314 return x | ~y;
315
316 CASE_OP_32_64(eqv):
317 return ~(x ^ y);
318
319 CASE_OP_32_64(nand):
320 return ~(x & y);
321
322 CASE_OP_32_64(nor):
323 return ~(x | y);
324
0e28d006
RH
325 case INDEX_op_clz_i32:
326 return (uint32_t)x ? clz32(x) : y;
327
328 case INDEX_op_clz_i64:
329 return x ? clz64(x) : y;
330
331 case INDEX_op_ctz_i32:
332 return (uint32_t)x ? ctz32(x) : y;
333
334 case INDEX_op_ctz_i64:
335 return x ? ctz64(x) : y;
336
a768e4e9
RH
337 case INDEX_op_ctpop_i32:
338 return ctpop32(x);
339
340 case INDEX_op_ctpop_i64:
341 return ctpop64(x);
342
25c4d9cc 343 CASE_OP_32_64(ext8s):
a640f031 344 return (int8_t)x;
25c4d9cc
RH
345
346 CASE_OP_32_64(ext16s):
a640f031 347 return (int16_t)x;
25c4d9cc
RH
348
349 CASE_OP_32_64(ext8u):
a640f031 350 return (uint8_t)x;
25c4d9cc
RH
351
352 CASE_OP_32_64(ext16u):
a640f031
KB
353 return (uint16_t)x;
354
6498594c
RH
355 CASE_OP_32_64(bswap16):
356 return bswap16(x);
357
358 CASE_OP_32_64(bswap32):
359 return bswap32(x);
360
361 case INDEX_op_bswap64_i64:
362 return bswap64(x);
363
8bcb5c8f 364 case INDEX_op_ext_i32_i64:
a640f031
KB
365 case INDEX_op_ext32s_i64:
366 return (int32_t)x;
367
8bcb5c8f 368 case INDEX_op_extu_i32_i64:
609ad705 369 case INDEX_op_extrl_i64_i32:
a640f031
KB
370 case INDEX_op_ext32u_i64:
371 return (uint32_t)x;
a640f031 372
609ad705
RH
373 case INDEX_op_extrh_i64_i32:
374 return (uint64_t)x >> 32;
375
03271524
RH
376 case INDEX_op_muluh_i32:
377 return ((uint64_t)(uint32_t)x * (uint32_t)y) >> 32;
378 case INDEX_op_mulsh_i32:
379 return ((int64_t)(int32_t)x * (int32_t)y) >> 32;
380
381 case INDEX_op_muluh_i64:
382 mulu64(&l64, &h64, x, y);
383 return h64;
384 case INDEX_op_mulsh_i64:
385 muls64(&l64, &h64, x, y);
386 return h64;
387
01547f7f
RH
388 case INDEX_op_div_i32:
389 /* Avoid crashing on divide by zero, otherwise undefined. */
390 return (int32_t)x / ((int32_t)y ? : 1);
391 case INDEX_op_divu_i32:
392 return (uint32_t)x / ((uint32_t)y ? : 1);
393 case INDEX_op_div_i64:
394 return (int64_t)x / ((int64_t)y ? : 1);
395 case INDEX_op_divu_i64:
396 return (uint64_t)x / ((uint64_t)y ? : 1);
397
398 case INDEX_op_rem_i32:
399 return (int32_t)x % ((int32_t)y ? : 1);
400 case INDEX_op_remu_i32:
401 return (uint32_t)x % ((uint32_t)y ? : 1);
402 case INDEX_op_rem_i64:
403 return (int64_t)x % ((int64_t)y ? : 1);
404 case INDEX_op_remu_i64:
405 return (uint64_t)x % ((uint64_t)y ? : 1);
406
53108fb5
KB
407 default:
408 fprintf(stderr,
409 "Unrecognized operation %d in do_constant_folding.\n", op);
410 tcg_abort();
411 }
412}
413
fe0de7aa 414static TCGArg do_constant_folding(TCGOpcode op, TCGArg x, TCGArg y)
53108fb5 415{
170ba88f 416 const TCGOpDef *def = &tcg_op_defs[op];
53108fb5 417 TCGArg res = do_constant_folding_2(op, x, y);
170ba88f 418 if (!(def->flags & TCG_OPF_64BIT)) {
29f3ff8d 419 res = (int32_t)res;
53108fb5 420 }
53108fb5
KB
421 return res;
422}
423
9519da7e
RH
424static bool do_constant_folding_cond_32(uint32_t x, uint32_t y, TCGCond c)
425{
426 switch (c) {
427 case TCG_COND_EQ:
428 return x == y;
429 case TCG_COND_NE:
430 return x != y;
431 case TCG_COND_LT:
432 return (int32_t)x < (int32_t)y;
433 case TCG_COND_GE:
434 return (int32_t)x >= (int32_t)y;
435 case TCG_COND_LE:
436 return (int32_t)x <= (int32_t)y;
437 case TCG_COND_GT:
438 return (int32_t)x > (int32_t)y;
439 case TCG_COND_LTU:
440 return x < y;
441 case TCG_COND_GEU:
442 return x >= y;
443 case TCG_COND_LEU:
444 return x <= y;
445 case TCG_COND_GTU:
446 return x > y;
447 default:
448 tcg_abort();
449 }
450}
451
452static bool do_constant_folding_cond_64(uint64_t x, uint64_t y, TCGCond c)
453{
454 switch (c) {
455 case TCG_COND_EQ:
456 return x == y;
457 case TCG_COND_NE:
458 return x != y;
459 case TCG_COND_LT:
460 return (int64_t)x < (int64_t)y;
461 case TCG_COND_GE:
462 return (int64_t)x >= (int64_t)y;
463 case TCG_COND_LE:
464 return (int64_t)x <= (int64_t)y;
465 case TCG_COND_GT:
466 return (int64_t)x > (int64_t)y;
467 case TCG_COND_LTU:
468 return x < y;
469 case TCG_COND_GEU:
470 return x >= y;
471 case TCG_COND_LEU:
472 return x <= y;
473 case TCG_COND_GTU:
474 return x > y;
475 default:
476 tcg_abort();
477 }
478}
479
480static bool do_constant_folding_cond_eq(TCGCond c)
481{
482 switch (c) {
483 case TCG_COND_GT:
484 case TCG_COND_LTU:
485 case TCG_COND_LT:
486 case TCG_COND_GTU:
487 case TCG_COND_NE:
488 return 0;
489 case TCG_COND_GE:
490 case TCG_COND_GEU:
491 case TCG_COND_LE:
492 case TCG_COND_LEU:
493 case TCG_COND_EQ:
494 return 1;
495 default:
496 tcg_abort();
497 }
498}
499
b336ceb6
AJ
500/* Return 2 if the condition can't be simplified, and the result
501 of the condition (0 or 1) if it can */
f8dd19e5
AJ
502static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x,
503 TCGArg y, TCGCond c)
504{
6349039d
RH
505 tcg_target_ulong xv = arg_info(x)->val;
506 tcg_target_ulong yv = arg_info(y)->val;
507 if (arg_is_const(x) && arg_is_const(y)) {
170ba88f
RH
508 const TCGOpDef *def = &tcg_op_defs[op];
509 tcg_debug_assert(!(def->flags & TCG_OPF_VECTOR));
510 if (def->flags & TCG_OPF_64BIT) {
6349039d 511 return do_constant_folding_cond_64(xv, yv, c);
170ba88f
RH
512 } else {
513 return do_constant_folding_cond_32(xv, yv, c);
b336ceb6 514 }
6349039d 515 } else if (args_are_copies(x, y)) {
9519da7e 516 return do_constant_folding_cond_eq(c);
6349039d 517 } else if (arg_is_const(y) && yv == 0) {
b336ceb6 518 switch (c) {
f8dd19e5 519 case TCG_COND_LTU:
b336ceb6 520 return 0;
f8dd19e5 521 case TCG_COND_GEU:
b336ceb6
AJ
522 return 1;
523 default:
524 return 2;
f8dd19e5 525 }
f8dd19e5 526 }
550276ae 527 return 2;
f8dd19e5
AJ
528}
529
6c4382f8
RH
530/* Return 2 if the condition can't be simplified, and the result
531 of the condition (0 or 1) if it can */
532static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c)
533{
534 TCGArg al = p1[0], ah = p1[1];
535 TCGArg bl = p2[0], bh = p2[1];
536
6349039d
RH
537 if (arg_is_const(bl) && arg_is_const(bh)) {
538 tcg_target_ulong blv = arg_info(bl)->val;
539 tcg_target_ulong bhv = arg_info(bh)->val;
540 uint64_t b = deposit64(blv, 32, 32, bhv);
6c4382f8 541
6349039d
RH
542 if (arg_is_const(al) && arg_is_const(ah)) {
543 tcg_target_ulong alv = arg_info(al)->val;
544 tcg_target_ulong ahv = arg_info(ah)->val;
545 uint64_t a = deposit64(alv, 32, 32, ahv);
6c4382f8
RH
546 return do_constant_folding_cond_64(a, b, c);
547 }
548 if (b == 0) {
549 switch (c) {
550 case TCG_COND_LTU:
551 return 0;
552 case TCG_COND_GEU:
553 return 1;
554 default:
555 break;
556 }
557 }
558 }
6349039d 559 if (args_are_copies(al, bl) && args_are_copies(ah, bh)) {
6c4382f8
RH
560 return do_constant_folding_cond_eq(c);
561 }
562 return 2;
563}
564
24c9ae4e
RH
565static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2)
566{
567 TCGArg a1 = *p1, a2 = *p2;
568 int sum = 0;
6349039d
RH
569 sum += arg_is_const(a1);
570 sum -= arg_is_const(a2);
24c9ae4e
RH
571
572 /* Prefer the constant in second argument, and then the form
573 op a, a, b, which is better handled on non-RISC hosts. */
574 if (sum > 0 || (sum == 0 && dest == a2)) {
575 *p1 = a2;
576 *p2 = a1;
577 return true;
578 }
579 return false;
580}
581
0bfcb865
RH
582static bool swap_commutative2(TCGArg *p1, TCGArg *p2)
583{
584 int sum = 0;
6349039d
RH
585 sum += arg_is_const(p1[0]);
586 sum += arg_is_const(p1[1]);
587 sum -= arg_is_const(p2[0]);
588 sum -= arg_is_const(p2[1]);
0bfcb865
RH
589 if (sum > 0) {
590 TCGArg t;
591 t = p1[0], p1[0] = p2[0], p2[0] = t;
592 t = p1[1], p1[1] = p2[1], p2[1] = t;
593 return true;
594 }
595 return false;
596}
597
22613af4 598/* Propagate constants and copies, fold constant expressions. */
36e60ef6 599void tcg_optimize(TCGContext *s)
8f2e8c07 600{
15fa08f8
RH
601 int nb_temps, nb_globals;
602 TCGOp *op, *op_next, *prev_mb = NULL;
34184b07
EC
603 struct tcg_temp_info *infos;
604 TCGTempSet temps_used;
5d8f5363 605
22613af4
KB
606 /* Array VALS has an element for each temp.
607 If this temp holds a constant then its value is kept in VALS' element.
e590d4e6
AJ
608 If this temp is a copy of other ones then the other copies are
609 available through the doubly linked circular list. */
8f2e8c07
KB
610
611 nb_temps = s->nb_temps;
612 nb_globals = s->nb_globals;
34184b07
EC
613 bitmap_zero(temps_used.l, nb_temps);
614 infos = tcg_malloc(sizeof(struct tcg_temp_info) * nb_temps);
8f2e8c07 615
15fa08f8 616 QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
24666baf 617 tcg_target_ulong mask, partmask, affected;
c45cb8bb 618 int nb_oargs, nb_iargs, i;
cf066674 619 TCGArg tmp;
c45cb8bb
RH
620 TCGOpcode opc = op->opc;
621 const TCGOpDef *def = &tcg_op_defs[opc];
622
1208d7dd
AJ
623 /* Count the arguments, and initialize the temps that are
624 going to be used */
c45cb8bb 625 if (opc == INDEX_op_call) {
cd9090aa
RH
626 nb_oargs = TCGOP_CALLO(op);
627 nb_iargs = TCGOP_CALLI(op);
1208d7dd 628 for (i = 0; i < nb_oargs + nb_iargs; i++) {
6349039d
RH
629 TCGTemp *ts = arg_temp(op->args[i]);
630 if (ts) {
34184b07 631 init_ts_info(infos, &temps_used, ts);
1208d7dd
AJ
632 }
633 }
1ff8c541 634 } else {
cf066674
RH
635 nb_oargs = def->nb_oargs;
636 nb_iargs = def->nb_iargs;
1208d7dd 637 for (i = 0; i < nb_oargs + nb_iargs; i++) {
34184b07 638 init_arg_info(infos, &temps_used, op->args[i]);
1208d7dd 639 }
cf066674
RH
640 }
641
642 /* Do copy propagation */
643 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
6349039d
RH
644 TCGTemp *ts = arg_temp(op->args[i]);
645 if (ts && ts_is_copy(ts)) {
646 op->args[i] = temp_arg(find_better_copy(s, ts));
22613af4
KB
647 }
648 }
649
53108fb5 650 /* For commutative operations make constant second argument */
c45cb8bb 651 switch (opc) {
170ba88f
RH
652 CASE_OP_32_64_VEC(add):
653 CASE_OP_32_64_VEC(mul):
654 CASE_OP_32_64_VEC(and):
655 CASE_OP_32_64_VEC(or):
656 CASE_OP_32_64_VEC(xor):
cb25c80a
RH
657 CASE_OP_32_64(eqv):
658 CASE_OP_32_64(nand):
659 CASE_OP_32_64(nor):
03271524
RH
660 CASE_OP_32_64(muluh):
661 CASE_OP_32_64(mulsh):
acd93701 662 swap_commutative(op->args[0], &op->args[1], &op->args[2]);
53108fb5 663 break;
65a7cce1 664 CASE_OP_32_64(brcond):
acd93701
RH
665 if (swap_commutative(-1, &op->args[0], &op->args[1])) {
666 op->args[2] = tcg_swap_cond(op->args[2]);
65a7cce1
AJ
667 }
668 break;
669 CASE_OP_32_64(setcond):
acd93701
RH
670 if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) {
671 op->args[3] = tcg_swap_cond(op->args[3]);
65a7cce1
AJ
672 }
673 break;
fa01a208 674 CASE_OP_32_64(movcond):
acd93701
RH
675 if (swap_commutative(-1, &op->args[1], &op->args[2])) {
676 op->args[5] = tcg_swap_cond(op->args[5]);
5d8f5363
RH
677 }
678 /* For movcond, we canonicalize the "false" input reg to match
679 the destination reg so that the tcg backend can implement
680 a "move if true" operation. */
acd93701
RH
681 if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) {
682 op->args[5] = tcg_invert_cond(op->args[5]);
fa01a208 683 }
1e484e61 684 break;
d7156f7c 685 CASE_OP_32_64(add2):
acd93701
RH
686 swap_commutative(op->args[0], &op->args[2], &op->args[4]);
687 swap_commutative(op->args[1], &op->args[3], &op->args[5]);
1e484e61 688 break;
d7156f7c 689 CASE_OP_32_64(mulu2):
4d3203fd 690 CASE_OP_32_64(muls2):
acd93701 691 swap_commutative(op->args[0], &op->args[2], &op->args[3]);
1414968a 692 break;
0bfcb865 693 case INDEX_op_brcond2_i32:
acd93701
RH
694 if (swap_commutative2(&op->args[0], &op->args[2])) {
695 op->args[4] = tcg_swap_cond(op->args[4]);
0bfcb865
RH
696 }
697 break;
698 case INDEX_op_setcond2_i32:
acd93701
RH
699 if (swap_commutative2(&op->args[1], &op->args[3])) {
700 op->args[5] = tcg_swap_cond(op->args[5]);
0bfcb865
RH
701 }
702 break;
53108fb5
KB
703 default:
704 break;
705 }
706
2d497542
RH
707 /* Simplify expressions for "shift/rot r, 0, a => movi r, 0",
708 and "sub r, 0, a => neg r, a" case. */
c45cb8bb 709 switch (opc) {
01ee5282
AJ
710 CASE_OP_32_64(shl):
711 CASE_OP_32_64(shr):
712 CASE_OP_32_64(sar):
713 CASE_OP_32_64(rotl):
714 CASE_OP_32_64(rotr):
6349039d
RH
715 if (arg_is_const(op->args[1])
716 && arg_info(op->args[1])->val == 0) {
acd93701 717 tcg_opt_gen_movi(s, op, op->args[0], 0);
01ee5282
AJ
718 continue;
719 }
720 break;
170ba88f 721 CASE_OP_32_64_VEC(sub):
2d497542
RH
722 {
723 TCGOpcode neg_op;
724 bool have_neg;
725
6349039d 726 if (arg_is_const(op->args[2])) {
2d497542
RH
727 /* Proceed with possible constant folding. */
728 break;
729 }
c45cb8bb 730 if (opc == INDEX_op_sub_i32) {
2d497542
RH
731 neg_op = INDEX_op_neg_i32;
732 have_neg = TCG_TARGET_HAS_neg_i32;
170ba88f 733 } else if (opc == INDEX_op_sub_i64) {
2d497542
RH
734 neg_op = INDEX_op_neg_i64;
735 have_neg = TCG_TARGET_HAS_neg_i64;
ac383dde
RH
736 } else if (TCG_TARGET_HAS_neg_vec) {
737 TCGType type = TCGOP_VECL(op) + TCG_TYPE_V64;
738 unsigned vece = TCGOP_VECE(op);
170ba88f 739 neg_op = INDEX_op_neg_vec;
ac383dde
RH
740 have_neg = tcg_can_emit_vec_op(neg_op, type, vece) > 0;
741 } else {
742 break;
2d497542
RH
743 }
744 if (!have_neg) {
745 break;
746 }
6349039d
RH
747 if (arg_is_const(op->args[1])
748 && arg_info(op->args[1])->val == 0) {
c45cb8bb 749 op->opc = neg_op;
acd93701
RH
750 reset_temp(op->args[0]);
751 op->args[1] = op->args[2];
2d497542
RH
752 continue;
753 }
754 }
755 break;
170ba88f 756 CASE_OP_32_64_VEC(xor):
e201b564 757 CASE_OP_32_64(nand):
6349039d
RH
758 if (!arg_is_const(op->args[1])
759 && arg_is_const(op->args[2])
760 && arg_info(op->args[2])->val == -1) {
e201b564
RH
761 i = 1;
762 goto try_not;
763 }
764 break;
765 CASE_OP_32_64(nor):
6349039d
RH
766 if (!arg_is_const(op->args[1])
767 && arg_is_const(op->args[2])
768 && arg_info(op->args[2])->val == 0) {
e201b564
RH
769 i = 1;
770 goto try_not;
771 }
772 break;
170ba88f 773 CASE_OP_32_64_VEC(andc):
6349039d
RH
774 if (!arg_is_const(op->args[2])
775 && arg_is_const(op->args[1])
776 && arg_info(op->args[1])->val == -1) {
e201b564
RH
777 i = 2;
778 goto try_not;
779 }
780 break;
170ba88f 781 CASE_OP_32_64_VEC(orc):
e201b564 782 CASE_OP_32_64(eqv):
6349039d
RH
783 if (!arg_is_const(op->args[2])
784 && arg_is_const(op->args[1])
785 && arg_info(op->args[1])->val == 0) {
e201b564
RH
786 i = 2;
787 goto try_not;
788 }
789 break;
790 try_not:
791 {
792 TCGOpcode not_op;
793 bool have_not;
794
170ba88f
RH
795 if (def->flags & TCG_OPF_VECTOR) {
796 not_op = INDEX_op_not_vec;
797 have_not = TCG_TARGET_HAS_not_vec;
798 } else if (def->flags & TCG_OPF_64BIT) {
e201b564
RH
799 not_op = INDEX_op_not_i64;
800 have_not = TCG_TARGET_HAS_not_i64;
801 } else {
802 not_op = INDEX_op_not_i32;
803 have_not = TCG_TARGET_HAS_not_i32;
804 }
805 if (!have_not) {
806 break;
807 }
c45cb8bb 808 op->opc = not_op;
acd93701
RH
809 reset_temp(op->args[0]);
810 op->args[1] = op->args[i];
e201b564
RH
811 continue;
812 }
01ee5282
AJ
813 default:
814 break;
815 }
816
464a1441 817 /* Simplify expression for "op r, a, const => mov r, a" cases */
c45cb8bb 818 switch (opc) {
170ba88f
RH
819 CASE_OP_32_64_VEC(add):
820 CASE_OP_32_64_VEC(sub):
821 CASE_OP_32_64_VEC(or):
822 CASE_OP_32_64_VEC(xor):
823 CASE_OP_32_64_VEC(andc):
55c0975c
KB
824 CASE_OP_32_64(shl):
825 CASE_OP_32_64(shr):
826 CASE_OP_32_64(sar):
25c4d9cc
RH
827 CASE_OP_32_64(rotl):
828 CASE_OP_32_64(rotr):
6349039d
RH
829 if (!arg_is_const(op->args[1])
830 && arg_is_const(op->args[2])
831 && arg_info(op->args[2])->val == 0) {
acd93701 832 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
97a79eb7 833 continue;
53108fb5
KB
834 }
835 break;
170ba88f
RH
836 CASE_OP_32_64_VEC(and):
837 CASE_OP_32_64_VEC(orc):
464a1441 838 CASE_OP_32_64(eqv):
6349039d
RH
839 if (!arg_is_const(op->args[1])
840 && arg_is_const(op->args[2])
841 && arg_info(op->args[2])->val == -1) {
acd93701 842 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
97a79eb7 843 continue;
464a1441
RH
844 }
845 break;
56e49438
AJ
846 default:
847 break;
848 }
849
3031244b
AJ
850 /* Simplify using known-zero bits. Currently only ops with a single
851 output argument is supported. */
3a9d8b17 852 mask = -1;
633f6502 853 affected = -1;
c45cb8bb 854 switch (opc) {
3a9d8b17 855 CASE_OP_32_64(ext8s):
6349039d 856 if ((arg_info(op->args[1])->mask & 0x80) != 0) {
3a9d8b17
PB
857 break;
858 }
859 CASE_OP_32_64(ext8u):
860 mask = 0xff;
861 goto and_const;
862 CASE_OP_32_64(ext16s):
6349039d 863 if ((arg_info(op->args[1])->mask & 0x8000) != 0) {
3a9d8b17
PB
864 break;
865 }
866 CASE_OP_32_64(ext16u):
867 mask = 0xffff;
868 goto and_const;
869 case INDEX_op_ext32s_i64:
6349039d 870 if ((arg_info(op->args[1])->mask & 0x80000000) != 0) {
3a9d8b17
PB
871 break;
872 }
873 case INDEX_op_ext32u_i64:
874 mask = 0xffffffffU;
875 goto and_const;
876
877 CASE_OP_32_64(and):
6349039d
RH
878 mask = arg_info(op->args[2])->mask;
879 if (arg_is_const(op->args[2])) {
3a9d8b17 880 and_const:
6349039d 881 affected = arg_info(op->args[1])->mask & ~mask;
3a9d8b17 882 }
6349039d 883 mask = arg_info(op->args[1])->mask & mask;
3a9d8b17
PB
884 break;
885
8bcb5c8f 886 case INDEX_op_ext_i32_i64:
6349039d 887 if ((arg_info(op->args[1])->mask & 0x80000000) != 0) {
8bcb5c8f
AJ
888 break;
889 }
890 case INDEX_op_extu_i32_i64:
891 /* We do not compute affected as it is a size changing op. */
6349039d 892 mask = (uint32_t)arg_info(op->args[1])->mask;
8bcb5c8f
AJ
893 break;
894
23ec69ed
RH
895 CASE_OP_32_64(andc):
896 /* Known-zeros does not imply known-ones. Therefore unless
acd93701 897 op->args[2] is constant, we can't infer anything from it. */
6349039d
RH
898 if (arg_is_const(op->args[2])) {
899 mask = ~arg_info(op->args[2])->mask;
23ec69ed
RH
900 goto and_const;
901 }
6349039d
RH
902 /* But we certainly know nothing outside args[1] may be set. */
903 mask = arg_info(op->args[1])->mask;
23ec69ed
RH
904 break;
905
e46b225a 906 case INDEX_op_sar_i32:
6349039d
RH
907 if (arg_is_const(op->args[2])) {
908 tmp = arg_info(op->args[2])->val & 31;
909 mask = (int32_t)arg_info(op->args[1])->mask >> tmp;
e46b225a
AJ
910 }
911 break;
912 case INDEX_op_sar_i64:
6349039d
RH
913 if (arg_is_const(op->args[2])) {
914 tmp = arg_info(op->args[2])->val & 63;
915 mask = (int64_t)arg_info(op->args[1])->mask >> tmp;
3a9d8b17
PB
916 }
917 break;
918
e46b225a 919 case INDEX_op_shr_i32:
6349039d
RH
920 if (arg_is_const(op->args[2])) {
921 tmp = arg_info(op->args[2])->val & 31;
922 mask = (uint32_t)arg_info(op->args[1])->mask >> tmp;
e46b225a
AJ
923 }
924 break;
925 case INDEX_op_shr_i64:
6349039d
RH
926 if (arg_is_const(op->args[2])) {
927 tmp = arg_info(op->args[2])->val & 63;
928 mask = (uint64_t)arg_info(op->args[1])->mask >> tmp;
3a9d8b17
PB
929 }
930 break;
931
609ad705 932 case INDEX_op_extrl_i64_i32:
6349039d 933 mask = (uint32_t)arg_info(op->args[1])->mask;
609ad705
RH
934 break;
935 case INDEX_op_extrh_i64_i32:
6349039d 936 mask = (uint64_t)arg_info(op->args[1])->mask >> 32;
4bb7a41e
RH
937 break;
938
3a9d8b17 939 CASE_OP_32_64(shl):
6349039d
RH
940 if (arg_is_const(op->args[2])) {
941 tmp = arg_info(op->args[2])->val & (TCG_TARGET_REG_BITS - 1);
942 mask = arg_info(op->args[1])->mask << tmp;
3a9d8b17
PB
943 }
944 break;
945
946 CASE_OP_32_64(neg):
947 /* Set to 1 all bits to the left of the rightmost. */
6349039d
RH
948 mask = -(arg_info(op->args[1])->mask
949 & -arg_info(op->args[1])->mask);
3a9d8b17
PB
950 break;
951
952 CASE_OP_32_64(deposit):
6349039d
RH
953 mask = deposit64(arg_info(op->args[1])->mask,
954 op->args[3], op->args[4],
955 arg_info(op->args[2])->mask);
3a9d8b17
PB
956 break;
957
7ec8bab3 958 CASE_OP_32_64(extract):
6349039d
RH
959 mask = extract64(arg_info(op->args[1])->mask,
960 op->args[2], op->args[3]);
acd93701 961 if (op->args[2] == 0) {
6349039d 962 affected = arg_info(op->args[1])->mask & ~mask;
7ec8bab3
RH
963 }
964 break;
965 CASE_OP_32_64(sextract):
6349039d 966 mask = sextract64(arg_info(op->args[1])->mask,
acd93701
RH
967 op->args[2], op->args[3]);
968 if (op->args[2] == 0 && (tcg_target_long)mask >= 0) {
6349039d 969 affected = arg_info(op->args[1])->mask & ~mask;
7ec8bab3
RH
970 }
971 break;
972
3a9d8b17
PB
973 CASE_OP_32_64(or):
974 CASE_OP_32_64(xor):
6349039d 975 mask = arg_info(op->args[1])->mask | arg_info(op->args[2])->mask;
3a9d8b17
PB
976 break;
977
0e28d006
RH
978 case INDEX_op_clz_i32:
979 case INDEX_op_ctz_i32:
6349039d 980 mask = arg_info(op->args[2])->mask | 31;
0e28d006
RH
981 break;
982
983 case INDEX_op_clz_i64:
984 case INDEX_op_ctz_i64:
6349039d 985 mask = arg_info(op->args[2])->mask | 63;
0e28d006
RH
986 break;
987
a768e4e9
RH
988 case INDEX_op_ctpop_i32:
989 mask = 32 | 31;
990 break;
991 case INDEX_op_ctpop_i64:
992 mask = 64 | 63;
993 break;
994
3a9d8b17 995 CASE_OP_32_64(setcond):
a763551a 996 case INDEX_op_setcond2_i32:
3a9d8b17
PB
997 mask = 1;
998 break;
999
1000 CASE_OP_32_64(movcond):
6349039d 1001 mask = arg_info(op->args[3])->mask | arg_info(op->args[4])->mask;
3a9d8b17
PB
1002 break;
1003
c8d70272 1004 CASE_OP_32_64(ld8u):
c8d70272
AJ
1005 mask = 0xff;
1006 break;
1007 CASE_OP_32_64(ld16u):
c8d70272
AJ
1008 mask = 0xffff;
1009 break;
1010 case INDEX_op_ld32u_i64:
c8d70272
AJ
1011 mask = 0xffffffffu;
1012 break;
1013
1014 CASE_OP_32_64(qemu_ld):
1015 {
acd93701 1016 TCGMemOpIdx oi = op->args[nb_oargs + nb_iargs];
59227d5d 1017 TCGMemOp mop = get_memop(oi);
c8d70272
AJ
1018 if (!(mop & MO_SIGN)) {
1019 mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
1020 }
1021 }
1022 break;
1023
3a9d8b17
PB
1024 default:
1025 break;
1026 }
1027
bc8d688f
RH
1028 /* 32-bit ops generate 32-bit results. For the result is zero test
1029 below, we can ignore high bits, but for further optimizations we
1030 need to record that the high bits contain garbage. */
24666baf 1031 partmask = mask;
bc8d688f 1032 if (!(def->flags & TCG_OPF_64BIT)) {
24666baf
RH
1033 mask |= ~(tcg_target_ulong)0xffffffffu;
1034 partmask &= 0xffffffffu;
1035 affected &= 0xffffffffu;
f096dc96
AJ
1036 }
1037
24666baf 1038 if (partmask == 0) {
eabb7b91 1039 tcg_debug_assert(nb_oargs == 1);
acd93701 1040 tcg_opt_gen_movi(s, op, op->args[0], 0);
633f6502
PB
1041 continue;
1042 }
1043 if (affected == 0) {
eabb7b91 1044 tcg_debug_assert(nb_oargs == 1);
acd93701 1045 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
633f6502
PB
1046 continue;
1047 }
1048
56e49438 1049 /* Simplify expression for "op r, a, 0 => movi r, 0" cases */
c45cb8bb 1050 switch (opc) {
170ba88f
RH
1051 CASE_OP_32_64_VEC(and):
1052 CASE_OP_32_64_VEC(mul):
03271524
RH
1053 CASE_OP_32_64(muluh):
1054 CASE_OP_32_64(mulsh):
6349039d
RH
1055 if (arg_is_const(op->args[2])
1056 && arg_info(op->args[2])->val == 0) {
acd93701 1057 tcg_opt_gen_movi(s, op, op->args[0], 0);
53108fb5
KB
1058 continue;
1059 }
1060 break;
56e49438
AJ
1061 default:
1062 break;
1063 }
1064
1065 /* Simplify expression for "op r, a, a => mov r, a" cases */
c45cb8bb 1066 switch (opc) {
170ba88f
RH
1067 CASE_OP_32_64_VEC(or):
1068 CASE_OP_32_64_VEC(and):
6349039d 1069 if (args_are_copies(op->args[1], op->args[2])) {
acd93701 1070 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
9a81090b
KB
1071 continue;
1072 }
1073 break;
fe0de7aa
BS
1074 default:
1075 break;
53108fb5
KB
1076 }
1077
3c94193e 1078 /* Simplify expression for "op r, a, a => movi r, 0" cases */
c45cb8bb 1079 switch (opc) {
170ba88f
RH
1080 CASE_OP_32_64_VEC(andc):
1081 CASE_OP_32_64_VEC(sub):
1082 CASE_OP_32_64_VEC(xor):
6349039d 1083 if (args_are_copies(op->args[1], op->args[2])) {
acd93701 1084 tcg_opt_gen_movi(s, op, op->args[0], 0);
3c94193e
AJ
1085 continue;
1086 }
1087 break;
1088 default:
1089 break;
1090 }
1091
22613af4
KB
1092 /* Propagate constants through copy operations and do constant
1093 folding. Constants will be substituted to arguments by register
1094 allocator where needed and possible. Also detect copies. */
c45cb8bb 1095 switch (opc) {
170ba88f 1096 CASE_OP_32_64_VEC(mov):
acd93701 1097 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
97a79eb7 1098 break;
22613af4 1099 CASE_OP_32_64(movi):
170ba88f 1100 case INDEX_op_dupi_vec:
acd93701 1101 tcg_opt_gen_movi(s, op, op->args[0], op->args[1]);
22613af4 1102 break;
6e14e91b 1103
170ba88f
RH
1104 case INDEX_op_dup_vec:
1105 if (arg_is_const(op->args[1])) {
1106 tmp = arg_info(op->args[1])->val;
1107 tmp = dup_const(TCGOP_VECE(op), tmp);
1108 tcg_opt_gen_movi(s, op, op->args[0], tmp);
1fb57da7 1109 break;
170ba88f 1110 }
1fb57da7 1111 goto do_default;
170ba88f 1112
a640f031 1113 CASE_OP_32_64(not):
cb25c80a 1114 CASE_OP_32_64(neg):
25c4d9cc
RH
1115 CASE_OP_32_64(ext8s):
1116 CASE_OP_32_64(ext8u):
1117 CASE_OP_32_64(ext16s):
1118 CASE_OP_32_64(ext16u):
a768e4e9 1119 CASE_OP_32_64(ctpop):
6498594c
RH
1120 CASE_OP_32_64(bswap16):
1121 CASE_OP_32_64(bswap32):
1122 case INDEX_op_bswap64_i64:
a640f031
KB
1123 case INDEX_op_ext32s_i64:
1124 case INDEX_op_ext32u_i64:
8bcb5c8f
AJ
1125 case INDEX_op_ext_i32_i64:
1126 case INDEX_op_extu_i32_i64:
609ad705
RH
1127 case INDEX_op_extrl_i64_i32:
1128 case INDEX_op_extrh_i64_i32:
6349039d
RH
1129 if (arg_is_const(op->args[1])) {
1130 tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0);
acd93701 1131 tcg_opt_gen_movi(s, op, op->args[0], tmp);
6e14e91b 1132 break;
a640f031 1133 }
6e14e91b
RH
1134 goto do_default;
1135
53108fb5
KB
1136 CASE_OP_32_64(add):
1137 CASE_OP_32_64(sub):
1138 CASE_OP_32_64(mul):
9a81090b
KB
1139 CASE_OP_32_64(or):
1140 CASE_OP_32_64(and):
1141 CASE_OP_32_64(xor):
55c0975c
KB
1142 CASE_OP_32_64(shl):
1143 CASE_OP_32_64(shr):
1144 CASE_OP_32_64(sar):
25c4d9cc
RH
1145 CASE_OP_32_64(rotl):
1146 CASE_OP_32_64(rotr):
cb25c80a
RH
1147 CASE_OP_32_64(andc):
1148 CASE_OP_32_64(orc):
1149 CASE_OP_32_64(eqv):
1150 CASE_OP_32_64(nand):
1151 CASE_OP_32_64(nor):
03271524
RH
1152 CASE_OP_32_64(muluh):
1153 CASE_OP_32_64(mulsh):
01547f7f
RH
1154 CASE_OP_32_64(div):
1155 CASE_OP_32_64(divu):
1156 CASE_OP_32_64(rem):
1157 CASE_OP_32_64(remu):
6349039d
RH
1158 if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
1159 tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
1160 arg_info(op->args[2])->val);
acd93701 1161 tcg_opt_gen_movi(s, op, op->args[0], tmp);
6e14e91b 1162 break;
53108fb5 1163 }
6e14e91b
RH
1164 goto do_default;
1165
0e28d006
RH
1166 CASE_OP_32_64(clz):
1167 CASE_OP_32_64(ctz):
6349039d
RH
1168 if (arg_is_const(op->args[1])) {
1169 TCGArg v = arg_info(op->args[1])->val;
0e28d006
RH
1170 if (v != 0) {
1171 tmp = do_constant_folding(opc, v, 0);
acd93701 1172 tcg_opt_gen_movi(s, op, op->args[0], tmp);
0e28d006 1173 } else {
acd93701 1174 tcg_opt_gen_mov(s, op, op->args[0], op->args[2]);
0e28d006
RH
1175 }
1176 break;
1177 }
1178 goto do_default;
1179
7ef55fc9 1180 CASE_OP_32_64(deposit):
6349039d
RH
1181 if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
1182 tmp = deposit64(arg_info(op->args[1])->val,
1183 op->args[3], op->args[4],
1184 arg_info(op->args[2])->val);
acd93701 1185 tcg_opt_gen_movi(s, op, op->args[0], tmp);
6e14e91b 1186 break;
7ef55fc9 1187 }
6e14e91b
RH
1188 goto do_default;
1189
7ec8bab3 1190 CASE_OP_32_64(extract):
6349039d
RH
1191 if (arg_is_const(op->args[1])) {
1192 tmp = extract64(arg_info(op->args[1])->val,
acd93701
RH
1193 op->args[2], op->args[3]);
1194 tcg_opt_gen_movi(s, op, op->args[0], tmp);
7ec8bab3
RH
1195 break;
1196 }
1197 goto do_default;
1198
1199 CASE_OP_32_64(sextract):
6349039d
RH
1200 if (arg_is_const(op->args[1])) {
1201 tmp = sextract64(arg_info(op->args[1])->val,
acd93701
RH
1202 op->args[2], op->args[3]);
1203 tcg_opt_gen_movi(s, op, op->args[0], tmp);
7ec8bab3
RH
1204 break;
1205 }
1206 goto do_default;
1207
fce1296f
RH
1208 CASE_OP_32_64(extract2):
1209 if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
1210 TCGArg v1 = arg_info(op->args[1])->val;
1211 TCGArg v2 = arg_info(op->args[2])->val;
1212
1213 if (opc == INDEX_op_extract2_i64) {
1214 tmp = (v1 >> op->args[3]) | (v2 << (64 - op->args[3]));
1215 } else {
1216 tmp = (v1 >> op->args[3]) | (v2 << (32 - op->args[3]));
1217 tmp = (int32_t)tmp;
1218 }
1219 tcg_opt_gen_movi(s, op, op->args[0], tmp);
1220 break;
1221 }
1222 goto do_default;
1223
f8dd19e5 1224 CASE_OP_32_64(setcond):
acd93701
RH
1225 tmp = do_constant_folding_cond(opc, op->args[1],
1226 op->args[2], op->args[3]);
b336ceb6 1227 if (tmp != 2) {
acd93701 1228 tcg_opt_gen_movi(s, op, op->args[0], tmp);
6e14e91b 1229 break;
f8dd19e5 1230 }
6e14e91b
RH
1231 goto do_default;
1232
fbeaa26c 1233 CASE_OP_32_64(brcond):
acd93701
RH
1234 tmp = do_constant_folding_cond(opc, op->args[0],
1235 op->args[1], op->args[2]);
b336ceb6
AJ
1236 if (tmp != 2) {
1237 if (tmp) {
34184b07 1238 bitmap_zero(temps_used.l, nb_temps);
c45cb8bb 1239 op->opc = INDEX_op_br;
acd93701 1240 op->args[0] = op->args[3];
fbeaa26c 1241 } else {
0c627cdc 1242 tcg_op_remove(s, op);
fbeaa26c 1243 }
6e14e91b 1244 break;
fbeaa26c 1245 }
6e14e91b
RH
1246 goto do_default;
1247
fa01a208 1248 CASE_OP_32_64(movcond):
acd93701
RH
1249 tmp = do_constant_folding_cond(opc, op->args[1],
1250 op->args[2], op->args[5]);
b336ceb6 1251 if (tmp != 2) {
acd93701 1252 tcg_opt_gen_mov(s, op, op->args[0], op->args[4-tmp]);
6e14e91b 1253 break;
fa01a208 1254 }
6349039d
RH
1255 if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
1256 tcg_target_ulong tv = arg_info(op->args[3])->val;
1257 tcg_target_ulong fv = arg_info(op->args[4])->val;
acd93701 1258 TCGCond cond = op->args[5];
333b21b8
RH
1259 if (fv == 1 && tv == 0) {
1260 cond = tcg_invert_cond(cond);
1261 } else if (!(tv == 1 && fv == 0)) {
1262 goto do_default;
1263 }
acd93701 1264 op->args[3] = cond;
333b21b8
RH
1265 op->opc = opc = (opc == INDEX_op_movcond_i32
1266 ? INDEX_op_setcond_i32
1267 : INDEX_op_setcond_i64);
1268 nb_iargs = 2;
1269 }
6e14e91b 1270 goto do_default;
212c328d
RH
1271
1272 case INDEX_op_add2_i32:
1273 case INDEX_op_sub2_i32:
6349039d
RH
1274 if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])
1275 && arg_is_const(op->args[4]) && arg_is_const(op->args[5])) {
1276 uint32_t al = arg_info(op->args[2])->val;
1277 uint32_t ah = arg_info(op->args[3])->val;
1278 uint32_t bl = arg_info(op->args[4])->val;
1279 uint32_t bh = arg_info(op->args[5])->val;
212c328d
RH
1280 uint64_t a = ((uint64_t)ah << 32) | al;
1281 uint64_t b = ((uint64_t)bh << 32) | bl;
1282 TCGArg rl, rh;
ac1043f6 1283 TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32);
212c328d 1284
c45cb8bb 1285 if (opc == INDEX_op_add2_i32) {
212c328d
RH
1286 a += b;
1287 } else {
1288 a -= b;
1289 }
1290
acd93701
RH
1291 rl = op->args[0];
1292 rh = op->args[1];
1293 tcg_opt_gen_movi(s, op, rl, (int32_t)a);
1294 tcg_opt_gen_movi(s, op2, rh, (int32_t)(a >> 32));
212c328d
RH
1295 break;
1296 }
1297 goto do_default;
1414968a
RH
1298
1299 case INDEX_op_mulu2_i32:
6349039d
RH
1300 if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) {
1301 uint32_t a = arg_info(op->args[2])->val;
1302 uint32_t b = arg_info(op->args[3])->val;
1414968a
RH
1303 uint64_t r = (uint64_t)a * b;
1304 TCGArg rl, rh;
ac1043f6 1305 TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32);
1414968a 1306
acd93701
RH
1307 rl = op->args[0];
1308 rh = op->args[1];
1309 tcg_opt_gen_movi(s, op, rl, (int32_t)r);
1310 tcg_opt_gen_movi(s, op2, rh, (int32_t)(r >> 32));
1414968a
RH
1311 break;
1312 }
1313 goto do_default;
6e14e91b 1314
bc1473ef 1315 case INDEX_op_brcond2_i32:
acd93701
RH
1316 tmp = do_constant_folding_cond2(&op->args[0], &op->args[2],
1317 op->args[4]);
6c4382f8
RH
1318 if (tmp != 2) {
1319 if (tmp) {
a763551a 1320 do_brcond_true:
34184b07 1321 bitmap_zero(temps_used.l, nb_temps);
c45cb8bb 1322 op->opc = INDEX_op_br;
acd93701 1323 op->args[0] = op->args[5];
6c4382f8 1324 } else {
a763551a 1325 do_brcond_false:
0c627cdc 1326 tcg_op_remove(s, op);
6c4382f8 1327 }
acd93701
RH
1328 } else if ((op->args[4] == TCG_COND_LT
1329 || op->args[4] == TCG_COND_GE)
6349039d
RH
1330 && arg_is_const(op->args[2])
1331 && arg_info(op->args[2])->val == 0
1332 && arg_is_const(op->args[3])
1333 && arg_info(op->args[3])->val == 0) {
6c4382f8
RH
1334 /* Simplify LT/GE comparisons vs zero to a single compare
1335 vs the high word of the input. */
a763551a 1336 do_brcond_high:
34184b07 1337 bitmap_zero(temps_used.l, nb_temps);
c45cb8bb 1338 op->opc = INDEX_op_brcond_i32;
acd93701
RH
1339 op->args[0] = op->args[1];
1340 op->args[1] = op->args[3];
1341 op->args[2] = op->args[4];
1342 op->args[3] = op->args[5];
1343 } else if (op->args[4] == TCG_COND_EQ) {
a763551a
RH
1344 /* Simplify EQ comparisons where one of the pairs
1345 can be simplified. */
1346 tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
acd93701
RH
1347 op->args[0], op->args[2],
1348 TCG_COND_EQ);
a763551a
RH
1349 if (tmp == 0) {
1350 goto do_brcond_false;
1351 } else if (tmp == 1) {
1352 goto do_brcond_high;
1353 }
1354 tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
acd93701
RH
1355 op->args[1], op->args[3],
1356 TCG_COND_EQ);
a763551a
RH
1357 if (tmp == 0) {
1358 goto do_brcond_false;
1359 } else if (tmp != 1) {
1360 goto do_default;
1361 }
1362 do_brcond_low:
34184b07 1363 bitmap_zero(temps_used.l, nb_temps);
c45cb8bb 1364 op->opc = INDEX_op_brcond_i32;
acd93701
RH
1365 op->args[1] = op->args[2];
1366 op->args[2] = op->args[4];
1367 op->args[3] = op->args[5];
1368 } else if (op->args[4] == TCG_COND_NE) {
a763551a
RH
1369 /* Simplify NE comparisons where one of the pairs
1370 can be simplified. */
1371 tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
acd93701
RH
1372 op->args[0], op->args[2],
1373 TCG_COND_NE);
a763551a
RH
1374 if (tmp == 0) {
1375 goto do_brcond_high;
1376 } else if (tmp == 1) {
1377 goto do_brcond_true;
1378 }
1379 tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
acd93701
RH
1380 op->args[1], op->args[3],
1381 TCG_COND_NE);
a763551a
RH
1382 if (tmp == 0) {
1383 goto do_brcond_low;
1384 } else if (tmp == 1) {
1385 goto do_brcond_true;
1386 }
1387 goto do_default;
6c4382f8
RH
1388 } else {
1389 goto do_default;
bc1473ef 1390 }
6c4382f8 1391 break;
bc1473ef
RH
1392
1393 case INDEX_op_setcond2_i32:
acd93701
RH
1394 tmp = do_constant_folding_cond2(&op->args[1], &op->args[3],
1395 op->args[5]);
6c4382f8 1396 if (tmp != 2) {
a763551a 1397 do_setcond_const:
acd93701
RH
1398 tcg_opt_gen_movi(s, op, op->args[0], tmp);
1399 } else if ((op->args[5] == TCG_COND_LT
1400 || op->args[5] == TCG_COND_GE)
6349039d
RH
1401 && arg_is_const(op->args[3])
1402 && arg_info(op->args[3])->val == 0
1403 && arg_is_const(op->args[4])
1404 && arg_info(op->args[4])->val == 0) {
6c4382f8
RH
1405 /* Simplify LT/GE comparisons vs zero to a single compare
1406 vs the high word of the input. */
a763551a 1407 do_setcond_high:
acd93701 1408 reset_temp(op->args[0]);
6349039d 1409 arg_info(op->args[0])->mask = 1;
c45cb8bb 1410 op->opc = INDEX_op_setcond_i32;
acd93701
RH
1411 op->args[1] = op->args[2];
1412 op->args[2] = op->args[4];
1413 op->args[3] = op->args[5];
1414 } else if (op->args[5] == TCG_COND_EQ) {
a763551a
RH
1415 /* Simplify EQ comparisons where one of the pairs
1416 can be simplified. */
1417 tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
acd93701
RH
1418 op->args[1], op->args[3],
1419 TCG_COND_EQ);
a763551a
RH
1420 if (tmp == 0) {
1421 goto do_setcond_const;
1422 } else if (tmp == 1) {
1423 goto do_setcond_high;
1424 }
1425 tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
acd93701
RH
1426 op->args[2], op->args[4],
1427 TCG_COND_EQ);
a763551a
RH
1428 if (tmp == 0) {
1429 goto do_setcond_high;
1430 } else if (tmp != 1) {
1431 goto do_default;
1432 }
1433 do_setcond_low:
acd93701 1434 reset_temp(op->args[0]);
6349039d 1435 arg_info(op->args[0])->mask = 1;
c45cb8bb 1436 op->opc = INDEX_op_setcond_i32;
acd93701
RH
1437 op->args[2] = op->args[3];
1438 op->args[3] = op->args[5];
1439 } else if (op->args[5] == TCG_COND_NE) {
a763551a
RH
1440 /* Simplify NE comparisons where one of the pairs
1441 can be simplified. */
1442 tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
acd93701
RH
1443 op->args[1], op->args[3],
1444 TCG_COND_NE);
a763551a
RH
1445 if (tmp == 0) {
1446 goto do_setcond_high;
1447 } else if (tmp == 1) {
1448 goto do_setcond_const;
1449 }
1450 tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
acd93701
RH
1451 op->args[2], op->args[4],
1452 TCG_COND_NE);
a763551a
RH
1453 if (tmp == 0) {
1454 goto do_setcond_low;
1455 } else if (tmp == 1) {
1456 goto do_setcond_const;
1457 }
1458 goto do_default;
6c4382f8
RH
1459 } else {
1460 goto do_default;
bc1473ef 1461 }
6c4382f8 1462 break;
bc1473ef 1463
8f2e8c07 1464 case INDEX_op_call:
acd93701 1465 if (!(op->args[nb_oargs + nb_iargs + 1]
cf066674 1466 & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) {
22613af4 1467 for (i = 0; i < nb_globals; i++) {
1208d7dd 1468 if (test_bit(i, temps_used.l)) {
6349039d 1469 reset_ts(&s->temps[i]);
1208d7dd 1470 }
22613af4
KB
1471 }
1472 }
cf066674 1473 goto do_reset_output;
6e14e91b 1474
8f2e8c07 1475 default:
6e14e91b
RH
1476 do_default:
1477 /* Default case: we know nothing about operation (or were unable
1478 to compute the operation result) so no propagation is done.
1479 We trash everything if the operation is the end of a basic
3a9d8b17
PB
1480 block, otherwise we only trash the output args. "mask" is
1481 the non-zero bits mask for the first output arg. */
a2550660 1482 if (def->flags & TCG_OPF_BB_END) {
34184b07 1483 bitmap_zero(temps_used.l, nb_temps);
a2550660 1484 } else {
cf066674
RH
1485 do_reset_output:
1486 for (i = 0; i < nb_oargs; i++) {
acd93701 1487 reset_temp(op->args[i]);
3031244b
AJ
1488 /* Save the corresponding known-zero bits mask for the
1489 first output argument (only one supported so far). */
1490 if (i == 0) {
6349039d 1491 arg_info(op->args[i])->mask = mask;
3031244b 1492 }
a2550660 1493 }
22613af4 1494 }
8f2e8c07
KB
1495 break;
1496 }
34f93921
PK
1497
1498 /* Eliminate duplicate and redundant fence instructions. */
acd93701 1499 if (prev_mb) {
34f93921
PK
1500 switch (opc) {
1501 case INDEX_op_mb:
1502 /* Merge two barriers of the same type into one,
1503 * or a weaker barrier into a stronger one,
1504 * or two weaker barriers into a stronger one.
1505 * mb X; mb Y => mb X|Y
1506 * mb; strl => mb; st
1507 * ldaq; mb => ld; mb
1508 * ldaq; strl => ld; mb; st
1509 * Other combinations are also merged into a strong
1510 * barrier. This is stricter than specified but for
1511 * the purposes of TCG is better than not optimizing.
1512 */
acd93701 1513 prev_mb->args[0] |= op->args[0];
34f93921
PK
1514 tcg_op_remove(s, op);
1515 break;
1516
1517 default:
1518 /* Opcodes that end the block stop the optimization. */
1519 if ((def->flags & TCG_OPF_BB_END) == 0) {
1520 break;
1521 }
1522 /* fallthru */
1523 case INDEX_op_qemu_ld_i32:
1524 case INDEX_op_qemu_ld_i64:
1525 case INDEX_op_qemu_st_i32:
1526 case INDEX_op_qemu_st_i64:
1527 case INDEX_op_call:
1528 /* Opcodes that touch guest memory stop the optimization. */
acd93701 1529 prev_mb = NULL;
34f93921
PK
1530 break;
1531 }
1532 } else if (opc == INDEX_op_mb) {
acd93701 1533 prev_mb = op;
34f93921 1534 }
8f2e8c07 1535 }
8f2e8c07 1536}