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tcg: Standardize on TCGReg as the enum for hard registers
[mirror_qemu.git] / tcg / sparc / tcg-target.c
CommitLineData
8289b279
BS		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
d4a9eb1f 25#ifndef NDEBUG
8289b279
BS		 26static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
27 "%g0",
28 "%g1",
29 "%g2",
30 "%g3",
31 "%g4",
32 "%g5",
33 "%g6",
34 "%g7",
35 "%o0",
36 "%o1",
37 "%o2",
38 "%o3",
39 "%o4",
40 "%o5",
41 "%o6",
42 "%o7",
43 "%l0",
44 "%l1",
45 "%l2",
46 "%l3",
47 "%l4",
48 "%l5",
49 "%l6",
50 "%l7",
51 "%i0",
52 "%i1",
53 "%i2",
54 "%i3",
55 "%i4",
56 "%i5",
57 "%i6",
58 "%i7",
59};
d4a9eb1f 60#endif
8289b279 61
0954d0d9 62static const int tcg_target_reg_alloc_order[] = {
8289b279
BS		 63 TCG_REG_L0,
64 TCG_REG_L1,
65 TCG_REG_L2,
66 TCG_REG_L3,
67 TCG_REG_L4,
68 TCG_REG_L5,
69 TCG_REG_L6,
70 TCG_REG_L7,
71 TCG_REG_I0,
72 TCG_REG_I1,
73 TCG_REG_I2,
74 TCG_REG_I3,
75 TCG_REG_I4,
8289b279
BS		 76};
77
78static const int tcg_target_call_iarg_regs[6] = {
79 TCG_REG_O0,
80 TCG_REG_O1,
81 TCG_REG_O2,
82 TCG_REG_O3,
83 TCG_REG_O4,
84 TCG_REG_O5,
85};
86
26a74ae3 87static const int tcg_target_call_oarg_regs[] = {
8289b279 88 TCG_REG_O0,
26a74ae3
SW		 89#if TCG_TARGET_REG_BITS == 32
90 TCG_REG_O1
91#endif
8289b279
BS		 92};
93
57e49b40 94static inline int check_fit_tl(tcg_target_long val, unsigned int bits)
f5ef6aac 95{
57e49b40
BS		 96 return (val << ((sizeof(tcg_target_long) * 8 - bits))
97 >> (sizeof(tcg_target_long) * 8 - bits)) == val;
98}
99
100static inline int check_fit_i32(uint32_t val, unsigned int bits)
101{
102 return ((val << (32 - bits)) >> (32 - bits)) == val;
f5ef6aac
BS		 103}
104
8289b279 105static void patch_reloc(uint8_t *code_ptr, int type,
f54b3f92 106 tcg_target_long value, tcg_target_long addend)
8289b279 107{
f54b3f92 108 value += addend;
8289b279
BS		 109 switch (type) {
110 case R_SPARC_32:
111 if (value != (uint32_t)value)
112 tcg_abort();
113 *(uint32_t *)code_ptr = value;
114 break;
f5ef6aac
BS		 115 case R_SPARC_WDISP22:
116 value -= (long)code_ptr;
117 value >>= 2;
57e49b40 118 if (!check_fit_tl(value, 22))
f5ef6aac
BS		 119 tcg_abort();
120 *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
121 break;
1da92db2
BS		 122 case R_SPARC_WDISP19:
123 value -= (long)code_ptr;
124 value >>= 2;
125 if (!check_fit_tl(value, 19))
126 tcg_abort();
127 *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x7ffff) | value;
128 break;
8289b279
BS		 129 default:
130 tcg_abort();
131 }
132}
133
134/* maximum number of register used for input function arguments */
135static inline int tcg_target_get_call_iarg_regs_count(int flags)
136{
137 return 6;
138}
139
140/* parse target specific constraints */
141static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
142{
143 const char *ct_str;
144
145 ct_str = *pct_str;
146 switch (ct_str[0]) {
147 case 'r':
5e143c43
RH		 148 ct->ct |= TCG_CT_REG;
149 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
150 break;
8289b279
BS		 151 case 'L': /* qemu_ld/st constraint */
152 ct->ct |= TCG_CT_REG;
153 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
53c37487
BS		 154 // Helper args
155 tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
156 tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
157 tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
8289b279
BS		 158 break;
159 case 'I':
160 ct->ct |= TCG_CT_CONST_S11;
161 break;
162 case 'J':
163 ct->ct |= TCG_CT_CONST_S13;
164 break;
165 default:
166 return -1;
167 }
168 ct_str++;
169 *pct_str = ct_str;
170 return 0;
171}
172
8289b279
BS		 173/* test if a constant matches the constraint */
174static inline int tcg_target_const_match(tcg_target_long val,
175 const TCGArgConstraint *arg_ct)
176{
177 int ct;
178
179 ct = arg_ct->ct;
180 if (ct & TCG_CT_CONST)
181 return 1;
57e49b40 182 else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
8289b279 183 return 1;
57e49b40 184 else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
8289b279
BS		 185 return 1;
186 else
187 return 0;
188}
189
190#define INSN_OP(x) ((x) << 30)
191#define INSN_OP2(x) ((x) << 22)
192#define INSN_OP3(x) ((x) << 19)
193#define INSN_OPF(x) ((x) << 5)
194#define INSN_RD(x) ((x) << 25)
195#define INSN_RS1(x) ((x) << 14)
196#define INSN_RS2(x) (x)
8384dd67 197#define INSN_ASI(x) ((x) << 5)
8289b279 198
dbfe80e1 199#define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff))
8289b279 200#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
1da92db2 201#define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
b3db8758 202#define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
8289b279 203
b3db8758 204#define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
cf7c2ca5
BS		 205#define COND_N 0x0
206#define COND_E 0x1
207#define COND_LE 0x2
208#define COND_L 0x3
209#define COND_LEU 0x4
210#define COND_CS 0x5
211#define COND_NEG 0x6
212#define COND_VS 0x7
b3db8758 213#define COND_A 0x8
cf7c2ca5
BS		 214#define COND_NE 0x9
215#define COND_G 0xa
216#define COND_GE 0xb
217#define COND_GU 0xc
218#define COND_CC 0xd
219#define COND_POS 0xe
220#define COND_VC 0xf
b3db8758 221#define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
8289b279 222
dbfe80e1
RH		 223#define MOVCC_ICC (1 << 18)
224#define MOVCC_XCC (1 << 18 | 1 << 12)
225
8289b279 226#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
7a3766f3 227#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
8289b279 228#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
dc69960d 229#define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05))
8289b279 230#define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02))
9a7f3228 231#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
be6551b1 232#define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06))
8289b279 233#define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03))
f5ef6aac
BS		 234#define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04))
235#define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
8289b279
BS		 236#define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10))
237#define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
238#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
239#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
240#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
241#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
242#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
243#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
dbfe80e1 244#define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c))
8289b279
BS		 245
246#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
247#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
248#define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27))
249
250#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
251#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
252#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
253
7a3766f3 254#define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0))
583d1215 255#define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0))
8289b279
BS		 256#define JMPL (INSN_OP(2) | INSN_OP3(0x38))
257#define SAVE (INSN_OP(2) | INSN_OP3(0x3c))
258#define RESTORE (INSN_OP(2) | INSN_OP3(0x3d))
259#define SETHI (INSN_OP(0) | INSN_OP2(0x4))
260#define CALL INSN_OP(1)
261#define LDUB (INSN_OP(3) | INSN_OP3(0x01))
262#define LDSB (INSN_OP(3) | INSN_OP3(0x09))
263#define LDUH (INSN_OP(3) | INSN_OP3(0x02))
264#define LDSH (INSN_OP(3) | INSN_OP3(0x0a))
265#define LDUW (INSN_OP(3) | INSN_OP3(0x00))
266#define LDSW (INSN_OP(3) | INSN_OP3(0x08))
267#define LDX (INSN_OP(3) | INSN_OP3(0x0b))
268#define STB (INSN_OP(3) | INSN_OP3(0x05))
269#define STH (INSN_OP(3) | INSN_OP3(0x06))
270#define STW (INSN_OP(3) | INSN_OP3(0x04))
271#define STX (INSN_OP(3) | INSN_OP3(0x0e))
8384dd67
BS		 272#define LDUBA (INSN_OP(3) | INSN_OP3(0x11))
273#define LDSBA (INSN_OP(3) | INSN_OP3(0x19))
274#define LDUHA (INSN_OP(3) | INSN_OP3(0x12))
275#define LDSHA (INSN_OP(3) | INSN_OP3(0x1a))
276#define LDUWA (INSN_OP(3) | INSN_OP3(0x10))
277#define LDSWA (INSN_OP(3) | INSN_OP3(0x18))
278#define LDXA (INSN_OP(3) | INSN_OP3(0x1b))
279#define STBA (INSN_OP(3) | INSN_OP3(0x15))
280#define STHA (INSN_OP(3) | INSN_OP3(0x16))
281#define STWA (INSN_OP(3) | INSN_OP3(0x14))
282#define STXA (INSN_OP(3) | INSN_OP3(0x1e))
283
284#ifndef ASI_PRIMARY_LITTLE
285#define ASI_PRIMARY_LITTLE 0x88
286#endif
8289b279 287
26cc915c
BS		 288static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2,
289 int op)
290{
291 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
292 INSN_RS2(rs2));
293}
294
6f41b777
BS		 295static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1,
296 uint32_t offset, int op)
26cc915c
BS		 297{
298 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
299 INSN_IMM13(offset));
300}
301
ba225198
RH		 302static void tcg_out_arithc(TCGContext *s, int rd, int rs1,
303 int val2, int val2const, int op)
304{
305 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)
306 | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2)));
307}
308
3b6dac34 309static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg)
8289b279 310{
26cc915c
BS		 311 tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
312}
313
314static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg)
315{
316 tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
8289b279
BS		 317}
318
b101234a
BS		 319static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg)
320{
321 tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
322}
323
324static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg)
8289b279 325{
4a09aa89 326 if (check_fit_tl(arg, 13))
b101234a 327 tcg_out_movi_imm13(s, ret, arg);
8289b279 328 else {
26cc915c 329 tcg_out_sethi(s, ret, arg);
8289b279 330 if (arg & 0x3ff)
b101234a 331 tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
8289b279
BS		 332 }
333}
334
b101234a
BS		 335static inline void tcg_out_movi(TCGContext *s, TCGType type,
336 int ret, tcg_target_long arg)
337{
43172207
RH		 338 /* All 32-bit constants, as well as 64-bit constants with
339 no high bits set go through movi_imm32. */
340 if (TCG_TARGET_REG_BITS == 32
341 || type == TCG_TYPE_I32
342 || (arg & ~(tcg_target_long)0xffffffff) == 0) {
343 tcg_out_movi_imm32(s, ret, arg);
344 } else if (check_fit_tl(arg, 13)) {
345 /* A 13-bit constant sign-extended to 64-bits. */
346 tcg_out_movi_imm13(s, ret, arg);
347 } else if (check_fit_tl(arg, 32)) {
348 /* A 32-bit constant sign-extended to 64-bits. */
349 tcg_out_sethi(s, ret, ~arg);
350 tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR);
351 } else {
352 tcg_out_movi_imm32(s, TCG_REG_I4, arg >> (TCG_TARGET_REG_BITS / 2));
d795eb86 353 tcg_out_arithi(s, TCG_REG_I4, TCG_REG_I4, 32, SHIFT_SLLX);
b101234a 354 tcg_out_movi_imm32(s, ret, arg);
d795eb86 355 tcg_out_arith(s, ret, ret, TCG_REG_I4, ARITH_OR);
6f41b777 356 }
b101234a
BS		 357}
358
8289b279
BS		 359static inline void tcg_out_ld_raw(TCGContext *s, int ret,
360 tcg_target_long arg)
361{
26cc915c 362 tcg_out_sethi(s, ret, arg);
8289b279
BS		 363 tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
364 INSN_IMM13(arg & 0x3ff));
365}
366
b3db8758
BS		 367static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
368 tcg_target_long arg)
369{
b101234a
BS		 370 if (!check_fit_tl(arg, 10))
371 tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
a212ea75
RH		 372 if (TCG_TARGET_REG_BITS == 64) {
373 tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
374 INSN_IMM13(arg & 0x3ff));
375 } else {
376 tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
377 INSN_IMM13(arg & 0x3ff));
378 }
b3db8758
BS		 379}
380
8289b279
BS		 381static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
382{
57e49b40 383 if (check_fit_tl(offset, 13))
8289b279
BS		 384 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
385 INSN_IMM13(offset));
cf7c2ca5
BS		 386 else {
387 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
388 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
389 INSN_RS2(addr));
390 }
8289b279
BS		 391}
392
8384dd67
BS		 393static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr,
394 int offset, int op, int asi)
395{
396 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
397 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
398 INSN_ASI(asi) | INSN_RS2(addr));
399}
400
e4d5434c 401static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
8289b279
BS		 402 int arg1, tcg_target_long arg2)
403{
7d551702
BS		 404 if (type == TCG_TYPE_I32)
405 tcg_out_ldst(s, ret, arg1, arg2, LDUW);
406 else
407 tcg_out_ldst(s, ret, arg1, arg2, LDX);
8289b279
BS		 408}
409
e4d5434c 410static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
8289b279
BS		 411 int arg1, tcg_target_long arg2)
412{
7d551702
BS		 413 if (type == TCG_TYPE_I32)
414 tcg_out_ldst(s, arg, arg1, arg2, STW);
415 else
416 tcg_out_ldst(s, arg, arg1, arg2, STX);
8289b279
BS		 417}
418
583d1215 419static inline void tcg_out_sety(TCGContext *s, int rs)
8289b279 420{
583d1215 421 tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs));
8289b279
BS		 422}
423
7a3766f3
RH		 424static inline void tcg_out_rdy(TCGContext *s, int rd)
425{
426 tcg_out32(s, RDY | INSN_RD(rd));
427}
428
8289b279
BS		 429static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
430{
431 if (val != 0) {
57e49b40 432 if (check_fit_tl(val, 13))
8289b279 433 tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
f5ef6aac
BS		 434 else {
435 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val);
436 tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD);
437 }
8289b279
BS		 438 }
439}
440
53c37487
BS		 441static inline void tcg_out_andi(TCGContext *s, int reg, tcg_target_long val)
442{
443 if (val != 0) {
444 if (check_fit_tl(val, 13))
445 tcg_out_arithi(s, reg, reg, val, ARITH_AND);
446 else {
447 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, val);
448 tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_AND);
449 }
450 }
451}
452
583d1215
RH		 453static void tcg_out_div32(TCGContext *s, int rd, int rs1,
454 int val2, int val2const, int uns)
455{
456 /* Load Y with the sign/zero extension of RS1 to 64-bits. */
457 if (uns) {
458 tcg_out_sety(s, TCG_REG_G0);
459 } else {
460 tcg_out_arithi(s, TCG_REG_I5, rs1, 31, SHIFT_SRA);
461 tcg_out_sety(s, TCG_REG_I5);
462 }
463
464 tcg_out_arithc(s, rd, rs1, val2, val2const,
465 uns ? ARITH_UDIV : ARITH_SDIV);
466}
467
8289b279
BS		 468static inline void tcg_out_nop(TCGContext *s)
469{
26cc915c 470 tcg_out_sethi(s, TCG_REG_G0, 0);
8289b279
BS		 471}
472
1da92db2 473static void tcg_out_branch_i32(TCGContext *s, int opc, int label_index)
cf7c2ca5
BS		 474{
475 int32_t val;
476 TCGLabel *l = &s->labels[label_index];
477
478 if (l->has_value) {
479 val = l->u.value - (tcg_target_long)s->code_ptr;
f5ef6aac 480 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2)
cf7c2ca5 481 | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr)));
f5ef6aac
BS		 482 } else {
483 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
484 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0));
485 }
cf7c2ca5
BS		 486}
487
a212ea75 488#if TCG_TARGET_REG_BITS == 64
1da92db2
BS		 489static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index)
490{
491 int32_t val;
492 TCGLabel *l = &s->labels[label_index];
493
494 if (l->has_value) {
495 val = l->u.value - (tcg_target_long)s->code_ptr;
496 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
497 (0x5 << 19) |
498 INSN_OFF19(l->u.value - (unsigned long)s->code_ptr)));
499 } else {
500 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, label_index, 0);
501 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
502 (0x5 << 19) | 0));
503 }
504}
505#endif
506
cf7c2ca5
BS		 507static const uint8_t tcg_cond_to_bcond[10] = {
508 [TCG_COND_EQ] = COND_E,
509 [TCG_COND_NE] = COND_NE,
510 [TCG_COND_LT] = COND_L,
511 [TCG_COND_GE] = COND_GE,
512 [TCG_COND_LE] = COND_LE,
513 [TCG_COND_GT] = COND_G,
514 [TCG_COND_LTU] = COND_CS,
515 [TCG_COND_GEU] = COND_CC,
516 [TCG_COND_LEU] = COND_LEU,
517 [TCG_COND_GTU] = COND_GU,
518};
519
56f4927e
RH		 520static void tcg_out_cmp(TCGContext *s, TCGArg c1, TCGArg c2, int c2const)
521{
ba225198 522 tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
56f4927e
RH		 523}
524
8a56e840 525static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond,
1da92db2
BS		 526 TCGArg arg1, TCGArg arg2, int const_arg2,
527 int label_index)
cf7c2ca5 528{
56f4927e 529 tcg_out_cmp(s, arg1, arg2, const_arg2);
1da92db2 530 tcg_out_branch_i32(s, tcg_cond_to_bcond[cond], label_index);
cf7c2ca5
BS		 531 tcg_out_nop(s);
532}
533
a212ea75 534#if TCG_TARGET_REG_BITS == 64
8a56e840 535static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond,
1da92db2
BS		 536 TCGArg arg1, TCGArg arg2, int const_arg2,
537 int label_index)
538{
56f4927e 539 tcg_out_cmp(s, arg1, arg2, const_arg2);
1da92db2
BS		 540 tcg_out_branch_i64(s, tcg_cond_to_bcond[cond], label_index);
541 tcg_out_nop(s);
542}
56f4927e 543#else
8a56e840 544static void tcg_out_brcond2_i32(TCGContext *s, TCGCond cond,
56f4927e
RH		 545 TCGArg al, TCGArg ah,
546 TCGArg bl, int blconst,
547 TCGArg bh, int bhconst, int label_dest)
548{
549 int cc, label_next = gen_new_label();
550
551 tcg_out_cmp(s, ah, bh, bhconst);
552
553 /* Note that we fill one of the delay slots with the second compare. */
554 switch (cond) {
555 case TCG_COND_EQ:
556 cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
557 tcg_out_branch_i32(s, cc, label_next);
558 tcg_out_cmp(s, al, bl, blconst);
559 cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_EQ], 0);
560 tcg_out_branch_i32(s, cc, label_dest);
561 break;
562
563 case TCG_COND_NE:
564 cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
565 tcg_out_branch_i32(s, cc, label_dest);
566 tcg_out_cmp(s, al, bl, blconst);
567 tcg_out_branch_i32(s, cc, label_dest);
568 break;
569
570 default:
571 /* ??? One could fairly easily special-case 64-bit unsigned
572 compares against 32-bit zero-extended constants. For instance,
573 we know that (unsigned)AH < 0 is false and need not emit it.
574 Similarly, (unsigned)AH > 0 being true implies AH != 0, so the
575 second branch will never be taken. */
576 cc = INSN_COND(tcg_cond_to_bcond[cond], 0);
577 tcg_out_branch_i32(s, cc, label_dest);
578 tcg_out_nop(s);
579 cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
580 tcg_out_branch_i32(s, cc, label_next);
581 tcg_out_cmp(s, al, bl, blconst);
582 cc = INSN_COND(tcg_cond_to_bcond[tcg_unsigned_cond(cond)], 0);
583 tcg_out_branch_i32(s, cc, label_dest);
584 break;
585 }
586 tcg_out_nop(s);
587
588 tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
589}
1da92db2
BS		 590#endif
591
8a56e840 592static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
dbfe80e1
RH		 593 TCGArg c1, TCGArg c2, int c2const)
594{
595 TCGArg t;
596
597 /* For 32-bit comparisons, we can play games with ADDX/SUBX. */
598 switch (cond) {
599 case TCG_COND_EQ:
600 case TCG_COND_NE:
601 if (c2 != 0) {
602 tcg_out_arithc(s, ret, c1, c2, c2const, ARITH_XOR);
603 }
604 c1 = TCG_REG_G0, c2 = ret, c2const = 0;
605 cond = (cond == TCG_COND_EQ ? TCG_COND_LEU : TCG_COND_LTU);
606 break;
607
608 case TCG_COND_GTU:
609 case TCG_COND_GEU:
610 if (c2const && c2 != 0) {
611 tcg_out_movi_imm13(s, TCG_REG_I5, c2);
612 c2 = TCG_REG_I5;
613 }
614 t = c1, c1 = c2, c2 = t, c2const = 0;
615 cond = tcg_swap_cond(cond);
616 break;
617
618 case TCG_COND_LTU:
619 case TCG_COND_LEU:
620 break;
621
622 default:
623 tcg_out_cmp(s, c1, c2, c2const);
624#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
625 tcg_out_movi_imm13(s, ret, 0);
626 tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
627 | INSN_RS1(tcg_cond_to_bcond[cond])
628 | MOVCC_ICC | INSN_IMM11(1));
629#else
630 t = gen_new_label();
631 tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), t);
632 tcg_out_movi_imm13(s, ret, 1);
633 tcg_out_movi_imm13(s, ret, 0);
634 tcg_out_label(s, t, (tcg_target_long)s->code_ptr);
635#endif
636 return;
637 }
638
639 tcg_out_cmp(s, c1, c2, c2const);
640 if (cond == TCG_COND_LTU) {
641 tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDX);
642 } else {
643 tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBX);
644 }
645}
646
647#if TCG_TARGET_REG_BITS == 64
8a56e840 648static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGArg ret,
dbfe80e1
RH		 649 TCGArg c1, TCGArg c2, int c2const)
650{
651 tcg_out_cmp(s, c1, c2, c2const);
652 tcg_out_movi_imm13(s, ret, 0);
653 tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
654 | INSN_RS1(tcg_cond_to_bcond[cond])
655 | MOVCC_XCC | INSN_IMM11(1));
656}
657#else
8a56e840 658static void tcg_out_setcond2_i32(TCGContext *s, TCGCond cond, TCGArg ret,
dbfe80e1
RH		 659 TCGArg al, TCGArg ah,
660 TCGArg bl, int blconst,
661 TCGArg bh, int bhconst)
662{
663 int lab;
664
665 switch (cond) {
666 case TCG_COND_EQ:
667 tcg_out_setcond_i32(s, TCG_COND_EQ, TCG_REG_I5, al, bl, blconst);
668 tcg_out_setcond_i32(s, TCG_COND_EQ, ret, ah, bh, bhconst);
669 tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_AND);
670 break;
671
672 case TCG_COND_NE:
673 tcg_out_setcond_i32(s, TCG_COND_NE, TCG_REG_I5, al, al, blconst);
674 tcg_out_setcond_i32(s, TCG_COND_NE, ret, ah, bh, bhconst);
675 tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_OR);
676 break;
677
678 default:
679 lab = gen_new_label();
680
681 tcg_out_cmp(s, ah, bh, bhconst);
682 tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), lab);
683 tcg_out_movi_imm13(s, ret, 1);
684 tcg_out_branch_i32(s, INSN_COND(COND_NE, 1), lab);
685 tcg_out_movi_imm13(s, ret, 0);
686
687 tcg_out_setcond_i32(s, tcg_unsigned_cond(cond), ret, al, bl, blconst);
688
689 tcg_out_label(s, lab, (tcg_target_long)s->code_ptr);
690 break;
691 }
692}
693#endif
694
7d551702 695/* Generate global QEMU prologue and epilogue code */
e4d58b41 696static void tcg_target_qemu_prologue(TCGContext *s)
b3db8758 697{
f44c9960
BS		 698 tcg_set_frame(s, TCG_REG_I6, TCG_TARGET_CALL_STACK_OFFSET,
699 CPU_TEMP_BUF_NLONGS * (int)sizeof(long));
b3db8758 700 tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
f44c9960
BS		 701 INSN_IMM13(-(TCG_TARGET_STACK_MINFRAME +
702 CPU_TEMP_BUF_NLONGS * (int)sizeof(long))));
cea5f9a2 703 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I1) |
7d551702 704 INSN_RS2(TCG_REG_G0));
cea5f9a2 705 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_I0);
b3db8758
BS		 706}
707
f5ef6aac 708#if defined(CONFIG_SOFTMMU)
f5ef6aac 709
79383c9c 710#include "../../softmmu_defs.h"
f5ef6aac 711
9a7f3228 712static const void * const qemu_ld_helpers[4] = {
f5ef6aac
BS		 713 __ldb_mmu,
714 __ldw_mmu,
715 __ldl_mmu,
716 __ldq_mmu,
717};
718
9a7f3228 719static const void * const qemu_st_helpers[4] = {
f5ef6aac
BS		 720 __stb_mmu,
721 __stw_mmu,
722 __stl_mmu,
723 __stq_mmu,
724};
725#endif
726
bffe1431
BS		 727#if TARGET_LONG_BITS == 32
728#define TARGET_LD_OP LDUW
729#else
730#define TARGET_LD_OP LDX
731#endif
732
65850a02 733#if defined(CONFIG_SOFTMMU)
355b1943 734#if HOST_LONG_BITS == 32
65850a02
BS		 735#define TARGET_ADDEND_LD_OP LDUW
736#else
737#define TARGET_ADDEND_LD_OP LDX
738#endif
739#endif
9d0efc88 740
bffe1431
BS		 741#ifdef __arch64__
742#define HOST_LD_OP LDX
743#define HOST_ST_OP STX
744#define HOST_SLL_OP SHIFT_SLLX
745#define HOST_SRA_OP SHIFT_SRAX
746#else
747#define HOST_LD_OP LDUW
748#define HOST_ST_OP STW
749#define HOST_SLL_OP SHIFT_SLL
750#define HOST_SRA_OP SHIFT_SRA
751#endif
752
f5ef6aac
BS		 753static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
754 int opc)
755{
56fc64df 756 int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
f5ef6aac 757#if defined(CONFIG_SOFTMMU)
53c37487 758 uint32_t *label1_ptr, *label2_ptr;
f5ef6aac
BS		 759#endif
760
761 data_reg = *args++;
762 addr_reg = *args++;
763 mem_index = *args;
764 s_bits = opc & 3;
765
53c37487
BS		 766 arg0 = TCG_REG_O0;
767 arg1 = TCG_REG_O1;
56fc64df 768 arg2 = TCG_REG_O2;
f5ef6aac 769
f5ef6aac 770#if defined(CONFIG_SOFTMMU)
56fc64df
BS		 771 /* srl addr_reg, x, arg1 */
772 tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
f5ef6aac 773 SHIFT_SRL);
56fc64df
BS		 774 /* and addr_reg, x, arg0 */
775 tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
f5ef6aac
BS		 776 ARITH_AND);
777
56fc64df
BS		 778 /* and arg1, x, arg1 */
779 tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
f5ef6aac 780
56fc64df
BS		 781 /* add arg1, x, arg1 */
782 tcg_out_addi(s, arg1, offsetof(CPUState,
783 tlb_table[mem_index][0].addr_read));
53c37487 784
56fc64df
BS		 785 /* add env, arg1, arg1 */
786 tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
f5ef6aac 787
56fc64df 788 /* ld [arg1], arg2 */
bffe1431 789 tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
56fc64df 790 INSN_RS2(TCG_REG_G0));
f5ef6aac 791
56fc64df
BS		 792 /* subcc arg0, arg2, %g0 */
793 tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
f5ef6aac
BS		 794
795 /* will become:
1da92db2
BS		 796 be label1
797 or
798 be,pt %xcc label1 */
53c37487 799 label1_ptr = (uint32_t *)s->code_ptr;
f5ef6aac
BS		 800 tcg_out32(s, 0);
801
53c37487 802 /* mov (delay slot) */
3b6dac34 803 tcg_out_mov(s, TCG_TYPE_PTR, arg0, addr_reg);
f5ef6aac 804
bffe1431
BS		 805 /* mov */
806 tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
807
f5ef6aac 808 /* XXX: move that code at the end of the TB */
53c37487 809 /* qemu_ld_helper[s_bits](arg0, arg1) */
f5ef6aac
BS		 810 tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits]
811 - (tcg_target_ulong)s->code_ptr) >> 2)
812 & 0x3fffffff));
bffe1431
BS		 813 /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
814 global registers */
815 // delay slot
816 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
f843e528
BS		 817 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
818 sizeof(long), HOST_ST_OP);
bffe1431 819 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
f843e528
BS		 820 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
821 sizeof(long), HOST_LD_OP);
f5ef6aac 822
53c37487 823 /* data_reg = sign_extend(arg0) */
f5ef6aac
BS		 824 switch(opc) {
825 case 0 | 4:
53c37487 826 /* sll arg0, 24/56, data_reg */
56fc64df 827 tcg_out_arithi(s, data_reg, arg0, (int)sizeof(tcg_target_long) * 8 - 8,
bffe1431 828 HOST_SLL_OP);
53c37487 829 /* sra data_reg, 24/56, data_reg */
56fc64df 830 tcg_out_arithi(s, data_reg, data_reg,
bffe1431 831 (int)sizeof(tcg_target_long) * 8 - 8, HOST_SRA_OP);
f5ef6aac
BS		 832 break;
833 case 1 | 4:
53c37487 834 /* sll arg0, 16/48, data_reg */
56fc64df 835 tcg_out_arithi(s, data_reg, arg0,
bffe1431 836 (int)sizeof(tcg_target_long) * 8 - 16, HOST_SLL_OP);
53c37487 837 /* sra data_reg, 16/48, data_reg */
56fc64df 838 tcg_out_arithi(s, data_reg, data_reg,
bffe1431 839 (int)sizeof(tcg_target_long) * 8 - 16, HOST_SRA_OP);
f5ef6aac
BS		 840 break;
841 case 2 | 4:
53c37487 842 /* sll arg0, 32, data_reg */
bffe1431 843 tcg_out_arithi(s, data_reg, arg0, 32, HOST_SLL_OP);
53c37487 844 /* sra data_reg, 32, data_reg */
bffe1431 845 tcg_out_arithi(s, data_reg, data_reg, 32, HOST_SRA_OP);
f5ef6aac
BS		 846 break;
847 case 0:
848 case 1:
849 case 2:
850 case 3:
851 default:
852 /* mov */
3b6dac34 853 tcg_out_mov(s, TCG_TYPE_REG, data_reg, arg0);
f5ef6aac
BS		 854 break;
855 }
856
857 /* will become:
858 ba label2 */
53c37487 859 label2_ptr = (uint32_t *)s->code_ptr;
f5ef6aac
BS		 860 tcg_out32(s, 0);
861
53c37487
BS		 862 /* nop (delay slot */
863 tcg_out_nop(s);
864
f5ef6aac 865 /* label1: */
1da92db2
BS		 866#if TARGET_LONG_BITS == 32
867 /* be label1 */
53c37487
BS		 868 *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
869 INSN_OFF22((unsigned long)s->code_ptr -
870 (unsigned long)label1_ptr));
1da92db2
BS		 871#else
872 /* be,pt %xcc label1 */
873 *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) |
874 (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr -
875 (unsigned long)label1_ptr));
876#endif
f5ef6aac 877
56fc64df
BS		 878 /* ld [arg1 + x], arg1 */
879 tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
9d0efc88 880 offsetof(CPUTLBEntry, addr_read), TARGET_ADDEND_LD_OP);
90cbed46
BS		 881
882#if TARGET_LONG_BITS == 32
883 /* and addr_reg, x, arg0 */
884 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
885 tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
886 /* add arg0, arg1, arg0 */
887 tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
888#else
56fc64df
BS		 889 /* add addr_reg, arg1, arg0 */
890 tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
90cbed46
BS		 891#endif
892
f5ef6aac 893#else
56fc64df 894 arg0 = addr_reg;
f5ef6aac
BS		 895#endif
896
f5ef6aac
BS		 897 switch(opc) {
898 case 0:
56fc64df
BS		 899 /* ldub [arg0], data_reg */
900 tcg_out_ldst(s, data_reg, arg0, 0, LDUB);
f5ef6aac
BS		 901 break;
902 case 0 | 4:
56fc64df
BS		 903 /* ldsb [arg0], data_reg */
904 tcg_out_ldst(s, data_reg, arg0, 0, LDSB);
f5ef6aac
BS		 905 break;
906 case 1:
8384dd67 907#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 908 /* lduh [arg0], data_reg */
909 tcg_out_ldst(s, data_reg, arg0, 0, LDUH);
8384dd67 910#else
56fc64df
BS		 911 /* lduha [arg0] ASI_PRIMARY_LITTLE, data_reg */
912 tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUHA, ASI_PRIMARY_LITTLE);
8384dd67 913#endif
f5ef6aac
BS		 914 break;
915 case 1 | 4:
8384dd67 916#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 917 /* ldsh [arg0], data_reg */
918 tcg_out_ldst(s, data_reg, arg0, 0, LDSH);
8384dd67 919#else
56fc64df
BS		 920 /* ldsha [arg0] ASI_PRIMARY_LITTLE, data_reg */
921 tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSHA, ASI_PRIMARY_LITTLE);
8384dd67 922#endif
f5ef6aac
BS		 923 break;
924 case 2:
8384dd67 925#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 926 /* lduw [arg0], data_reg */
927 tcg_out_ldst(s, data_reg, arg0, 0, LDUW);
8384dd67 928#else
56fc64df
BS		 929 /* lduwa [arg0] ASI_PRIMARY_LITTLE, data_reg */
930 tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUWA, ASI_PRIMARY_LITTLE);
8384dd67 931#endif
f5ef6aac
BS		 932 break;
933 case 2 | 4:
8384dd67 934#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 935 /* ldsw [arg0], data_reg */
936 tcg_out_ldst(s, data_reg, arg0, 0, LDSW);
8384dd67 937#else
56fc64df
BS		 938 /* ldswa [arg0] ASI_PRIMARY_LITTLE, data_reg */
939 tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSWA, ASI_PRIMARY_LITTLE);
8384dd67 940#endif
f5ef6aac
BS		 941 break;
942 case 3:
8384dd67 943#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 944 /* ldx [arg0], data_reg */
945 tcg_out_ldst(s, data_reg, arg0, 0, LDX);
8384dd67 946#else
56fc64df
BS		 947 /* ldxa [arg0] ASI_PRIMARY_LITTLE, data_reg */
948 tcg_out_ldst_asi(s, data_reg, arg0, 0, LDXA, ASI_PRIMARY_LITTLE);
8384dd67 949#endif
f5ef6aac
BS		 950 break;
951 default:
952 tcg_abort();
953 }
954
955#if defined(CONFIG_SOFTMMU)
956 /* label2: */
9a7f3228 957 *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
53c37487
BS		 958 INSN_OFF22((unsigned long)s->code_ptr -
959 (unsigned long)label2_ptr));
f5ef6aac
BS		 960#endif
961}
962
963static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
964 int opc)
965{
56fc64df 966 int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
f5ef6aac 967#if defined(CONFIG_SOFTMMU)
53c37487 968 uint32_t *label1_ptr, *label2_ptr;
f5ef6aac
BS		 969#endif
970
971 data_reg = *args++;
972 addr_reg = *args++;
973 mem_index = *args;
974
975 s_bits = opc;
976
53c37487
BS		 977 arg0 = TCG_REG_O0;
978 arg1 = TCG_REG_O1;
979 arg2 = TCG_REG_O2;
f5ef6aac 980
f5ef6aac 981#if defined(CONFIG_SOFTMMU)
56fc64df
BS		 982 /* srl addr_reg, x, arg1 */
983 tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
f5ef6aac 984 SHIFT_SRL);
53c37487 985
56fc64df
BS		 986 /* and addr_reg, x, arg0 */
987 tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
f5ef6aac
BS		 988 ARITH_AND);
989
56fc64df
BS		 990 /* and arg1, x, arg1 */
991 tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
f5ef6aac 992
56fc64df
BS		 993 /* add arg1, x, arg1 */
994 tcg_out_addi(s, arg1, offsetof(CPUState,
995 tlb_table[mem_index][0].addr_write));
f5ef6aac 996
56fc64df
BS		 997 /* add env, arg1, arg1 */
998 tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
f5ef6aac 999
56fc64df 1000 /* ld [arg1], arg2 */
bffe1431 1001 tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
56fc64df 1002 INSN_RS2(TCG_REG_G0));
53c37487 1003
56fc64df
BS		 1004 /* subcc arg0, arg2, %g0 */
1005 tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
f5ef6aac
BS		 1006
1007 /* will become:
1da92db2
BS		 1008 be label1
1009 or
1010 be,pt %xcc label1 */
53c37487 1011 label1_ptr = (uint32_t *)s->code_ptr;
f5ef6aac 1012 tcg_out32(s, 0);
f5ef6aac 1013
53c37487 1014 /* mov (delay slot) */
3b6dac34 1015 tcg_out_mov(s, TCG_TYPE_PTR, arg0, addr_reg);
53c37487 1016
53c37487 1017 /* mov */
3b6dac34 1018 tcg_out_mov(s, TCG_TYPE_REG, arg1, data_reg);
53c37487 1019
bffe1431
BS		 1020 /* mov */
1021 tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index);
1022
53c37487
BS		 1023 /* XXX: move that code at the end of the TB */
1024 /* qemu_st_helper[s_bits](arg0, arg1, arg2) */
f5ef6aac
BS		 1025 tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
1026 - (tcg_target_ulong)s->code_ptr) >> 2)
1027 & 0x3fffffff));
bffe1431
BS		 1028 /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
1029 global registers */
1030 // delay slot
1031 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
f843e528
BS		 1032 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1033 sizeof(long), HOST_ST_OP);
bffe1431 1034 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
f843e528
BS		 1035 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1036 sizeof(long), HOST_LD_OP);
f5ef6aac
BS		 1037
1038 /* will become:
1039 ba label2 */
53c37487 1040 label2_ptr = (uint32_t *)s->code_ptr;
f5ef6aac
BS		 1041 tcg_out32(s, 0);
1042
53c37487
BS		 1043 /* nop (delay slot) */
1044 tcg_out_nop(s);
1045
1da92db2
BS		 1046#if TARGET_LONG_BITS == 32
1047 /* be label1 */
53c37487
BS		 1048 *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
1049 INSN_OFF22((unsigned long)s->code_ptr -
1050 (unsigned long)label1_ptr));
1da92db2
BS		 1051#else
1052 /* be,pt %xcc label1 */
1053 *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) |
1054 (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr -
1055 (unsigned long)label1_ptr));
1056#endif
f5ef6aac 1057
56fc64df
BS		 1058 /* ld [arg1 + x], arg1 */
1059 tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
9d0efc88 1060 offsetof(CPUTLBEntry, addr_write), TARGET_ADDEND_LD_OP);
53c37487 1061
90cbed46
BS		 1062#if TARGET_LONG_BITS == 32
1063 /* and addr_reg, x, arg0 */
1064 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
1065 tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
1066 /* add arg0, arg1, arg0 */
1067 tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
1068#else
56fc64df
BS		 1069 /* add addr_reg, arg1, arg0 */
1070 tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
90cbed46
BS		 1071#endif
1072
f5ef6aac 1073#else
56fc64df 1074 arg0 = addr_reg;
f5ef6aac
BS		 1075#endif
1076
f5ef6aac
BS		 1077 switch(opc) {
1078 case 0:
56fc64df
BS		 1079 /* stb data_reg, [arg0] */
1080 tcg_out_ldst(s, data_reg, arg0, 0, STB);
f5ef6aac
BS		 1081 break;
1082 case 1:
8384dd67 1083#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 1084 /* sth data_reg, [arg0] */
1085 tcg_out_ldst(s, data_reg, arg0, 0, STH);
8384dd67 1086#else
56fc64df
BS		 1087 /* stha data_reg, [arg0] ASI_PRIMARY_LITTLE */
1088 tcg_out_ldst_asi(s, data_reg, arg0, 0, STHA, ASI_PRIMARY_LITTLE);
8384dd67 1089#endif
f5ef6aac
BS		 1090 break;
1091 case 2:
8384dd67 1092#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 1093 /* stw data_reg, [arg0] */
1094 tcg_out_ldst(s, data_reg, arg0, 0, STW);
8384dd67 1095#else
56fc64df
BS		 1096 /* stwa data_reg, [arg0] ASI_PRIMARY_LITTLE */
1097 tcg_out_ldst_asi(s, data_reg, arg0, 0, STWA, ASI_PRIMARY_LITTLE);
8384dd67 1098#endif
f5ef6aac
BS		 1099 break;
1100 case 3:
8384dd67 1101#ifdef TARGET_WORDS_BIGENDIAN
56fc64df
BS		 1102 /* stx data_reg, [arg0] */
1103 tcg_out_ldst(s, data_reg, arg0, 0, STX);
8384dd67 1104#else
56fc64df
BS		 1105 /* stxa data_reg, [arg0] ASI_PRIMARY_LITTLE */
1106 tcg_out_ldst_asi(s, data_reg, arg0, 0, STXA, ASI_PRIMARY_LITTLE);
8384dd67 1107#endif
f5ef6aac
BS		 1108 break;
1109 default:
1110 tcg_abort();
1111 }
1112
1113#if defined(CONFIG_SOFTMMU)
1114 /* label2: */
9a7f3228 1115 *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
53c37487
BS		 1116 INSN_OFF22((unsigned long)s->code_ptr -
1117 (unsigned long)label2_ptr));
f5ef6aac
BS		 1118#endif
1119}
1120
a9751609 1121static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
8289b279
BS		 1122 const int *const_args)
1123{
1124 int c;
1125
1126 switch (opc) {
1127 case INDEX_op_exit_tb:
b3db8758
BS		 1128 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
1129 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) |
8289b279 1130 INSN_IMM13(8));
b3db8758
BS		 1131 tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) |
1132 INSN_RS2(TCG_REG_G0));
8289b279
BS		 1133 break;
1134 case INDEX_op_goto_tb:
1135 if (s->tb_jmp_offset) {
1136 /* direct jump method */
26cc915c 1137 tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000);
cf7c2ca5
BS		 1138 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
1139 INSN_IMM13((args[0] & 0x1fff)));
8289b279 1140 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
8289b279
BS		 1141 } else {
1142 /* indirect jump method */
b3db8758
BS		 1143 tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
1144 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
1145 INSN_RS2(TCG_REG_G0));
8289b279 1146 }
53cd9273 1147 tcg_out_nop(s);
8289b279
BS		 1148 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1149 break;
1150 case INDEX_op_call:
bffe1431
BS		 1151 if (const_args[0])
1152 tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
1153 - (tcg_target_ulong)s->code_ptr) >> 2)
1154 & 0x3fffffff));
1155 else {
1156 tcg_out_ld_ptr(s, TCG_REG_I5,
1157 (tcg_target_long)(s->tb_next + args[0]));
1158 tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |
1159 INSN_RS2(TCG_REG_G0));
8289b279 1160 }
bffe1431
BS		 1161 /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
1162 global registers */
1163 // delay slot
1164 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
f843e528
BS		 1165 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1166 sizeof(long), HOST_ST_OP);
bffe1431 1167 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
f843e528
BS		 1168 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1169 sizeof(long), HOST_LD_OP);
8289b279
BS		 1170 break;
1171 case INDEX_op_jmp:
8289b279 1172 case INDEX_op_br:
1da92db2 1173 tcg_out_branch_i32(s, COND_A, args[0]);
f5ef6aac 1174 tcg_out_nop(s);
8289b279
BS		 1175 break;
1176 case INDEX_op_movi_i32:
1177 tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
1178 break;
1179
a212ea75 1180#if TCG_TARGET_REG_BITS == 64
8289b279 1181#define OP_32_64(x) \
ba225198
RH		 1182 glue(glue(case INDEX_op_, x), _i32): \
1183 glue(glue(case INDEX_op_, x), _i64)
8289b279
BS		 1184#else
1185#define OP_32_64(x) \
ba225198 1186 glue(glue(case INDEX_op_, x), _i32)
8289b279 1187#endif
ba225198 1188 OP_32_64(ld8u):
8289b279
BS		 1189 tcg_out_ldst(s, args[0], args[1], args[2], LDUB);
1190 break;
ba225198 1191 OP_32_64(ld8s):
8289b279
BS		 1192 tcg_out_ldst(s, args[0], args[1], args[2], LDSB);
1193 break;
ba225198 1194 OP_32_64(ld16u):
8289b279
BS		 1195 tcg_out_ldst(s, args[0], args[1], args[2], LDUH);
1196 break;
ba225198 1197 OP_32_64(ld16s):
8289b279
BS		 1198 tcg_out_ldst(s, args[0], args[1], args[2], LDSH);
1199 break;
1200 case INDEX_op_ld_i32:
a212ea75 1201#if TCG_TARGET_REG_BITS == 64
53cd9273 1202 case INDEX_op_ld32u_i64:
8289b279
BS		 1203#endif
1204 tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
1205 break;
ba225198 1206 OP_32_64(st8):
8289b279
BS		 1207 tcg_out_ldst(s, args[0], args[1], args[2], STB);
1208 break;
ba225198 1209 OP_32_64(st16):
8289b279
BS		 1210 tcg_out_ldst(s, args[0], args[1], args[2], STH);
1211 break;
1212 case INDEX_op_st_i32:
a212ea75 1213#if TCG_TARGET_REG_BITS == 64
53cd9273 1214 case INDEX_op_st32_i64:
8289b279
BS		 1215#endif
1216 tcg_out_ldst(s, args[0], args[1], args[2], STW);
1217 break;
ba225198 1218 OP_32_64(add):
53cd9273 1219 c = ARITH_ADD;
ba225198
RH		 1220 goto gen_arith;
1221 OP_32_64(sub):
8289b279 1222 c = ARITH_SUB;
ba225198
RH		 1223 goto gen_arith;
1224 OP_32_64(and):
8289b279 1225 c = ARITH_AND;
ba225198 1226 goto gen_arith;
dc69960d
RH		 1227 OP_32_64(andc):
1228 c = ARITH_ANDN;
1229 goto gen_arith;
ba225198 1230 OP_32_64(or):
8289b279 1231 c = ARITH_OR;
ba225198 1232 goto gen_arith;
18c8f7a3
RH		 1233 OP_32_64(orc):
1234 c = ARITH_ORN;
1235 goto gen_arith;
ba225198 1236 OP_32_64(xor):
8289b279 1237 c = ARITH_XOR;
ba225198 1238 goto gen_arith;
8289b279
BS		 1239 case INDEX_op_shl_i32:
1240 c = SHIFT_SLL;
ba225198 1241 goto gen_arith;
8289b279
BS		 1242 case INDEX_op_shr_i32:
1243 c = SHIFT_SRL;
ba225198 1244 goto gen_arith;
8289b279
BS		 1245 case INDEX_op_sar_i32:
1246 c = SHIFT_SRA;
ba225198 1247 goto gen_arith;
8289b279
BS		 1248 case INDEX_op_mul_i32:
1249 c = ARITH_UMUL;
ba225198 1250 goto gen_arith;
583d1215 1251
4b5a85c1
RH		 1252 OP_32_64(neg):
1253 c = ARITH_SUB;
1254 goto gen_arith1;
be6551b1
RH		 1255 OP_32_64(not):
1256 c = ARITH_ORN;
1257 goto gen_arith1;
4b5a85c1 1258
583d1215
RH		 1259 case INDEX_op_div_i32:
1260 tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 0);
1261 break;
1262 case INDEX_op_divu_i32:
1263 tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 1);
1264 break;
1265
1266 case INDEX_op_rem_i32:
1267 case INDEX_op_remu_i32:
1268 tcg_out_div32(s, TCG_REG_I5, args[1], args[2], const_args[2],
1269 opc == INDEX_op_remu_i32);
1270 tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2],
1271 ARITH_UMUL);
1272 tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB);
1273 break;
8289b279
BS		 1274
1275 case INDEX_op_brcond_i32:
1da92db2
BS		 1276 tcg_out_brcond_i32(s, args[2], args[0], args[1], const_args[1],
1277 args[3]);
8289b279 1278 break;
dbfe80e1
RH		 1279 case INDEX_op_setcond_i32:
1280 tcg_out_setcond_i32(s, args[3], args[0], args[1],
1281 args[2], const_args[2]);
1282 break;
1283
56f4927e
RH		 1284#if TCG_TARGET_REG_BITS == 32
1285 case INDEX_op_brcond2_i32:
1286 tcg_out_brcond2_i32(s, args[4], args[0], args[1],
1287 args[2], const_args[2],
1288 args[3], const_args[3], args[5]);
1289 break;
dbfe80e1
RH		 1290 case INDEX_op_setcond2_i32:
1291 tcg_out_setcond2_i32(s, args[5], args[0], args[1], args[2],
1292 args[3], const_args[3],
1293 args[4], const_args[4]);
1294 break;
7a3766f3
RH		 1295 case INDEX_op_add2_i32:
1296 tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
1297 ARITH_ADDCC);
1298 tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
1299 ARITH_ADDX);
1300 break;
1301 case INDEX_op_sub2_i32:
1302 tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
1303 ARITH_SUBCC);
1304 tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
1305 ARITH_SUBX);
1306 break;
1307 case INDEX_op_mulu2_i32:
1308 tcg_out_arithc(s, args[0], args[2], args[3], const_args[3],
1309 ARITH_UMUL);
1310 tcg_out_rdy(s, args[1]);
1311 break;
56f4927e 1312#endif
8289b279
BS		 1313
1314 case INDEX_op_qemu_ld8u:
f5ef6aac 1315 tcg_out_qemu_ld(s, args, 0);
8289b279
BS		 1316 break;
1317 case INDEX_op_qemu_ld8s:
f5ef6aac 1318 tcg_out_qemu_ld(s, args, 0 | 4);
8289b279
BS		 1319 break;
1320 case INDEX_op_qemu_ld16u:
f5ef6aac 1321 tcg_out_qemu_ld(s, args, 1);
8289b279
BS		 1322 break;
1323 case INDEX_op_qemu_ld16s:
f5ef6aac 1324 tcg_out_qemu_ld(s, args, 1 | 4);
8289b279 1325 break;
86feb1c8
RH		 1326 case INDEX_op_qemu_ld32:
1327#if TCG_TARGET_REG_BITS == 64
8289b279 1328 case INDEX_op_qemu_ld32u:
86feb1c8 1329#endif
f5ef6aac 1330 tcg_out_qemu_ld(s, args, 2);
8289b279 1331 break;
30c0c76c 1332#if TCG_TARGET_REG_BITS == 64
8289b279 1333 case INDEX_op_qemu_ld32s:
f5ef6aac 1334 tcg_out_qemu_ld(s, args, 2 | 4);
8289b279 1335 break;
30c0c76c 1336#endif
8289b279 1337 case INDEX_op_qemu_st8:
f5ef6aac 1338 tcg_out_qemu_st(s, args, 0);
8289b279
BS		 1339 break;
1340 case INDEX_op_qemu_st16:
f5ef6aac 1341 tcg_out_qemu_st(s, args, 1);
8289b279
BS		 1342 break;
1343 case INDEX_op_qemu_st32:
f5ef6aac 1344 tcg_out_qemu_st(s, args, 2);
8289b279
BS		 1345 break;
1346
a212ea75 1347#if TCG_TARGET_REG_BITS == 64
8289b279
BS		 1348 case INDEX_op_movi_i64:
1349 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1350 break;
53cd9273
BS		 1351 case INDEX_op_ld32s_i64:
1352 tcg_out_ldst(s, args[0], args[1], args[2], LDSW);
1353 break;
8289b279
BS		 1354 case INDEX_op_ld_i64:
1355 tcg_out_ldst(s, args[0], args[1], args[2], LDX);
1356 break;
1357 case INDEX_op_st_i64:
1358 tcg_out_ldst(s, args[0], args[1], args[2], STX);
1359 break;
1360 case INDEX_op_shl_i64:
1361 c = SHIFT_SLLX;
ba225198 1362 goto gen_arith;
8289b279
BS		 1363 case INDEX_op_shr_i64:
1364 c = SHIFT_SRLX;
ba225198 1365 goto gen_arith;
8289b279
BS		 1366 case INDEX_op_sar_i64:
1367 c = SHIFT_SRAX;
ba225198 1368 goto gen_arith;
8289b279
BS		 1369 case INDEX_op_mul_i64:
1370 c = ARITH_MULX;
ba225198 1371 goto gen_arith;
583d1215 1372 case INDEX_op_div_i64:
53cd9273 1373 c = ARITH_SDIVX;
ba225198 1374 goto gen_arith;
583d1215 1375 case INDEX_op_divu_i64:
8289b279 1376 c = ARITH_UDIVX;
ba225198 1377 goto gen_arith;
583d1215
RH		 1378 case INDEX_op_rem_i64:
1379 case INDEX_op_remu_i64:
1380 tcg_out_arithc(s, TCG_REG_I5, args[1], args[2], const_args[2],
1381 opc == INDEX_op_rem_i64 ? ARITH_SDIVX : ARITH_UDIVX);
1382 tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2],
1383 ARITH_MULX);
1384 tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB);
1385 break;
cc6dfecf
RH		 1386 case INDEX_op_ext32s_i64:
1387 if (const_args[1]) {
1388 tcg_out_movi(s, TCG_TYPE_I64, args[0], (int32_t)args[1]);
1389 } else {
1390 tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRA);
1391 }
1392 break;
1393 case INDEX_op_ext32u_i64:
1394 if (const_args[1]) {
1395 tcg_out_movi_imm32(s, args[0], args[1]);
1396 } else {
1397 tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRL);
1398 }
1399 break;
8289b279
BS		 1400
1401 case INDEX_op_brcond_i64:
1da92db2
BS		 1402 tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1],
1403 args[3]);
8289b279 1404 break;
dbfe80e1
RH		 1405 case INDEX_op_setcond_i64:
1406 tcg_out_setcond_i64(s, args[3], args[0], args[1],
1407 args[2], const_args[2]);
1408 break;
1409
8289b279 1410 case INDEX_op_qemu_ld64:
f5ef6aac 1411 tcg_out_qemu_ld(s, args, 3);
8289b279
BS		 1412 break;
1413 case INDEX_op_qemu_st64:
f5ef6aac 1414 tcg_out_qemu_st(s, args, 3);
8289b279
BS		 1415 break;
1416
1417#endif
ba225198
RH		 1418 gen_arith:
1419 tcg_out_arithc(s, args[0], args[1], args[2], const_args[2], c);
53cd9273
BS		 1420 break;
1421
4b5a85c1
RH		 1422 gen_arith1:
1423 tcg_out_arithc(s, args[0], TCG_REG_G0, args[1], const_args[1], c);
1424 break;
1425
8289b279
BS		 1426 default:
1427 fprintf(stderr, "unknown opcode 0x%x\n", opc);
1428 tcg_abort();
1429 }
1430}
1431
1432static const TCGTargetOpDef sparc_op_defs[] = {
1433 { INDEX_op_exit_tb, { } },
b3db8758 1434 { INDEX_op_goto_tb, { } },
8289b279
BS		 1435 { INDEX_op_call, { "ri" } },
1436 { INDEX_op_jmp, { "ri" } },
1437 { INDEX_op_br, { } },
1438
1439 { INDEX_op_mov_i32, { "r", "r" } },
1440 { INDEX_op_movi_i32, { "r" } },
1441 { INDEX_op_ld8u_i32, { "r", "r" } },
1442 { INDEX_op_ld8s_i32, { "r", "r" } },
1443 { INDEX_op_ld16u_i32, { "r", "r" } },
1444 { INDEX_op_ld16s_i32, { "r", "r" } },
1445 { INDEX_op_ld_i32, { "r", "r" } },
1446 { INDEX_op_st8_i32, { "r", "r" } },
1447 { INDEX_op_st16_i32, { "r", "r" } },
1448 { INDEX_op_st_i32, { "r", "r" } },
1449
53cd9273
BS		 1450 { INDEX_op_add_i32, { "r", "r", "rJ" } },
1451 { INDEX_op_mul_i32, { "r", "r", "rJ" } },
583d1215
RH		 1452 { INDEX_op_div_i32, { "r", "r", "rJ" } },
1453 { INDEX_op_divu_i32, { "r", "r", "rJ" } },
1454 { INDEX_op_rem_i32, { "r", "r", "rJ" } },
1455 { INDEX_op_remu_i32, { "r", "r", "rJ" } },
53cd9273
BS		 1456 { INDEX_op_sub_i32, { "r", "r", "rJ" } },
1457 { INDEX_op_and_i32, { "r", "r", "rJ" } },
dc69960d 1458 { INDEX_op_andc_i32, { "r", "r", "rJ" } },
53cd9273 1459 { INDEX_op_or_i32, { "r", "r", "rJ" } },
18c8f7a3 1460 { INDEX_op_orc_i32, { "r", "r", "rJ" } },
53cd9273 1461 { INDEX_op_xor_i32, { "r", "r", "rJ" } },
8289b279 1462
53cd9273
BS		 1463 { INDEX_op_shl_i32, { "r", "r", "rJ" } },
1464 { INDEX_op_shr_i32, { "r", "r", "rJ" } },
1465 { INDEX_op_sar_i32, { "r", "r", "rJ" } },
8289b279 1466
4b5a85c1 1467 { INDEX_op_neg_i32, { "r", "rJ" } },
be6551b1 1468 { INDEX_op_not_i32, { "r", "rJ" } },
4b5a85c1 1469
56f4927e 1470 { INDEX_op_brcond_i32, { "r", "rJ" } },
dbfe80e1
RH		 1471 { INDEX_op_setcond_i32, { "r", "r", "rJ" } },
1472
56f4927e
RH		 1473#if TCG_TARGET_REG_BITS == 32
1474 { INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } },
dbfe80e1 1475 { INDEX_op_setcond2_i32, { "r", "r", "r", "rJ", "rJ" } },
7a3766f3
RH		 1476 { INDEX_op_add2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
1477 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
1478 { INDEX_op_mulu2_i32, { "r", "r", "r", "rJ" } },
56f4927e 1479#endif
8289b279
BS		 1480
1481 { INDEX_op_qemu_ld8u, { "r", "L" } },
1482 { INDEX_op_qemu_ld8s, { "r", "L" } },
1483 { INDEX_op_qemu_ld16u, { "r", "L" } },
1484 { INDEX_op_qemu_ld16s, { "r", "L" } },
86feb1c8 1485 { INDEX_op_qemu_ld32, { "r", "L" } },
30c0c76c 1486#if TCG_TARGET_REG_BITS == 64
86feb1c8 1487 { INDEX_op_qemu_ld32u, { "r", "L" } },
8289b279 1488 { INDEX_op_qemu_ld32s, { "r", "L" } },
30c0c76c 1489#endif
8289b279
BS		 1490
1491 { INDEX_op_qemu_st8, { "L", "L" } },
1492 { INDEX_op_qemu_st16, { "L", "L" } },
1493 { INDEX_op_qemu_st32, { "L", "L" } },
1494
a212ea75 1495#if TCG_TARGET_REG_BITS == 64
8289b279
BS		 1496 { INDEX_op_mov_i64, { "r", "r" } },
1497 { INDEX_op_movi_i64, { "r" } },
1498 { INDEX_op_ld8u_i64, { "r", "r" } },
1499 { INDEX_op_ld8s_i64, { "r", "r" } },
1500 { INDEX_op_ld16u_i64, { "r", "r" } },
1501 { INDEX_op_ld16s_i64, { "r", "r" } },
1502 { INDEX_op_ld32u_i64, { "r", "r" } },
1503 { INDEX_op_ld32s_i64, { "r", "r" } },
1504 { INDEX_op_ld_i64, { "r", "r" } },
1505 { INDEX_op_st8_i64, { "r", "r" } },
1506 { INDEX_op_st16_i64, { "r", "r" } },
1507 { INDEX_op_st32_i64, { "r", "r" } },
1508 { INDEX_op_st_i64, { "r", "r" } },
56fc64df
BS		 1509 { INDEX_op_qemu_ld64, { "L", "L" } },
1510 { INDEX_op_qemu_st64, { "L", "L" } },
8289b279 1511
53cd9273
BS		 1512 { INDEX_op_add_i64, { "r", "r", "rJ" } },
1513 { INDEX_op_mul_i64, { "r", "r", "rJ" } },
583d1215
RH		 1514 { INDEX_op_div_i64, { "r", "r", "rJ" } },
1515 { INDEX_op_divu_i64, { "r", "r", "rJ" } },
1516 { INDEX_op_rem_i64, { "r", "r", "rJ" } },
1517 { INDEX_op_remu_i64, { "r", "r", "rJ" } },
53cd9273
BS		 1518 { INDEX_op_sub_i64, { "r", "r", "rJ" } },
1519 { INDEX_op_and_i64, { "r", "r", "rJ" } },
dc69960d 1520 { INDEX_op_andc_i64, { "r", "r", "rJ" } },
53cd9273 1521 { INDEX_op_or_i64, { "r", "r", "rJ" } },
18c8f7a3 1522 { INDEX_op_orc_i64, { "r", "r", "rJ" } },
53cd9273 1523 { INDEX_op_xor_i64, { "r", "r", "rJ" } },
8289b279 1524
53cd9273
BS		 1525 { INDEX_op_shl_i64, { "r", "r", "rJ" } },
1526 { INDEX_op_shr_i64, { "r", "r", "rJ" } },
1527 { INDEX_op_sar_i64, { "r", "r", "rJ" } },
4b5a85c1
RH		 1528
1529 { INDEX_op_neg_i64, { "r", "rJ" } },
be6551b1 1530 { INDEX_op_not_i64, { "r", "rJ" } },
4b5a85c1 1531
cc6dfecf
RH		 1532 { INDEX_op_ext32s_i64, { "r", "ri" } },
1533 { INDEX_op_ext32u_i64, { "r", "ri" } },
8289b279 1534
56f4927e 1535 { INDEX_op_brcond_i64, { "r", "rJ" } },
dbfe80e1 1536 { INDEX_op_setcond_i64, { "r", "r", "rJ" } },
8289b279
BS		 1537#endif
1538 { -1 },
1539};
1540
e4d58b41 1541static void tcg_target_init(TCGContext *s)
8289b279
BS		 1542{
1543 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
a212ea75 1544#if TCG_TARGET_REG_BITS == 64
8289b279
BS		 1545 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1546#endif
1547 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
b3db8758
BS		 1548 (1 << TCG_REG_G1) |
1549 (1 << TCG_REG_G2) |
1550 (1 << TCG_REG_G3) |
1551 (1 << TCG_REG_G4) |
1552 (1 << TCG_REG_G5) |
1553 (1 << TCG_REG_G6) |
1554 (1 << TCG_REG_G7) |
8289b279
BS		 1555 (1 << TCG_REG_O0) |
1556 (1 << TCG_REG_O1) |
1557 (1 << TCG_REG_O2) |
1558 (1 << TCG_REG_O3) |
1559 (1 << TCG_REG_O4) |
1560 (1 << TCG_REG_O5) |
8289b279
BS		 1561 (1 << TCG_REG_O7));
1562
1563 tcg_regset_clear(s->reserved_regs);
1564 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
a212ea75 1565#if TCG_TARGET_REG_BITS == 64
d795eb86
BS		 1566 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
1567#endif
53cd9273 1568 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
8289b279
BS		 1569 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6);
1570 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7);
1571 tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
1572 tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7);
1573 tcg_add_target_add_op_defs(sparc_op_defs);
1574}
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