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tcg: Promote tcg_out_{dup,dupi}_vec to backend interface
[mirror_qemu.git] / tcg / tcg-op-gvec.c
CommitLineData
db432672
RH		 1/*
2 * Generic vector operation expansion
3 *
4 * Copyright (c) 2018 Linaro
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
fb0343d5 9 * version 2.1 of the License, or (at your option) any later version.
db432672
RH		 10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
21#include "qemu-common.h"
22#include "tcg.h"
23#include "tcg-op.h"
24#include "tcg-op-gvec.h"
25#include "tcg-gvec-desc.h"
26
27#define MAX_UNROLL 4
28
53229a77
RH		 29#ifdef CONFIG_DEBUG_TCG
30static const TCGOpcode vecop_list_empty[1] = { 0 };
31#else
32#define vecop_list_empty NULL
33#endif
34
35
db432672
RH		 36/* Verify vector size and alignment rules. OFS should be the OR of all
37 of the operand offsets so that we can check them all at once. */
38static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs)
39{
40 uint32_t opr_align = oprsz >= 16 ? 15 : 7;
41 uint32_t max_align = maxsz >= 16 || oprsz >= 16 ? 15 : 7;
42 tcg_debug_assert(oprsz > 0);
43 tcg_debug_assert(oprsz <= maxsz);
44 tcg_debug_assert((oprsz & opr_align) == 0);
45 tcg_debug_assert((maxsz & max_align) == 0);
46 tcg_debug_assert((ofs & max_align) == 0);
47}
48
49/* Verify vector overlap rules for two operands. */
50static void check_overlap_2(uint32_t d, uint32_t a, uint32_t s)
51{
52 tcg_debug_assert(d == a || d + s <= a || a + s <= d);
53}
54
55/* Verify vector overlap rules for three operands. */
56static void check_overlap_3(uint32_t d, uint32_t a, uint32_t b, uint32_t s)
57{
58 check_overlap_2(d, a, s);
59 check_overlap_2(d, b, s);
60 check_overlap_2(a, b, s);
61}
62
63/* Verify vector overlap rules for four operands. */
64static void check_overlap_4(uint32_t d, uint32_t a, uint32_t b,
65 uint32_t c, uint32_t s)
66{
67 check_overlap_2(d, a, s);
68 check_overlap_2(d, b, s);
69 check_overlap_2(d, c, s);
70 check_overlap_2(a, b, s);
71 check_overlap_2(a, c, s);
72 check_overlap_2(b, c, s);
73}
74
75/* Create a descriptor from components. */
76uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data)
77{
78 uint32_t desc = 0;
79
80 assert(oprsz % 8 == 0 && oprsz <= (8 << SIMD_OPRSZ_BITS));
81 assert(maxsz % 8 == 0 && maxsz <= (8 << SIMD_MAXSZ_BITS));
82 assert(data == sextract32(data, 0, SIMD_DATA_BITS));
83
84 oprsz = (oprsz / 8) - 1;
85 maxsz = (maxsz / 8) - 1;
86 desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz);
87 desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz);
88 desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data);
89
90 return desc;
91}
92
93/* Generate a call to a gvec-style helper with two vector operands. */
94void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs,
95 uint32_t oprsz, uint32_t maxsz, int32_t data,
96 gen_helper_gvec_2 *fn)
97{
98 TCGv_ptr a0, a1;
99 TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
100
101 a0 = tcg_temp_new_ptr();
102 a1 = tcg_temp_new_ptr();
103
104 tcg_gen_addi_ptr(a0, cpu_env, dofs);
105 tcg_gen_addi_ptr(a1, cpu_env, aofs);
106
107 fn(a0, a1, desc);
108
109 tcg_temp_free_ptr(a0);
110 tcg_temp_free_ptr(a1);
111 tcg_temp_free_i32(desc);
112}
113
22fc3527
RH		 114/* Generate a call to a gvec-style helper with two vector operands
115 and one scalar operand. */
116void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c,
117 uint32_t oprsz, uint32_t maxsz, int32_t data,
118 gen_helper_gvec_2i *fn)
119{
120 TCGv_ptr a0, a1;
121 TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
122
123 a0 = tcg_temp_new_ptr();
124 a1 = tcg_temp_new_ptr();
125
126 tcg_gen_addi_ptr(a0, cpu_env, dofs);
127 tcg_gen_addi_ptr(a1, cpu_env, aofs);
128
129 fn(a0, a1, c, desc);
130
131 tcg_temp_free_ptr(a0);
132 tcg_temp_free_ptr(a1);
133 tcg_temp_free_i32(desc);
134}
135
db432672
RH		 136/* Generate a call to a gvec-style helper with three vector operands. */
137void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
138 uint32_t oprsz, uint32_t maxsz, int32_t data,
139 gen_helper_gvec_3 *fn)
140{
141 TCGv_ptr a0, a1, a2;
142 TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
143
144 a0 = tcg_temp_new_ptr();
145 a1 = tcg_temp_new_ptr();
146 a2 = tcg_temp_new_ptr();
147
148 tcg_gen_addi_ptr(a0, cpu_env, dofs);
149 tcg_gen_addi_ptr(a1, cpu_env, aofs);
150 tcg_gen_addi_ptr(a2, cpu_env, bofs);
151
152 fn(a0, a1, a2, desc);
153
154 tcg_temp_free_ptr(a0);
155 tcg_temp_free_ptr(a1);
156 tcg_temp_free_ptr(a2);
157 tcg_temp_free_i32(desc);
158}
159
160/* Generate a call to a gvec-style helper with four vector operands. */
161void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
162 uint32_t cofs, uint32_t oprsz, uint32_t maxsz,
163 int32_t data, gen_helper_gvec_4 *fn)
164{
165 TCGv_ptr a0, a1, a2, a3;
166 TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
167
168 a0 = tcg_temp_new_ptr();
169 a1 = tcg_temp_new_ptr();
170 a2 = tcg_temp_new_ptr();
171 a3 = tcg_temp_new_ptr();
172
173 tcg_gen_addi_ptr(a0, cpu_env, dofs);
174 tcg_gen_addi_ptr(a1, cpu_env, aofs);
175 tcg_gen_addi_ptr(a2, cpu_env, bofs);
176 tcg_gen_addi_ptr(a3, cpu_env, cofs);
177
178 fn(a0, a1, a2, a3, desc);
179
180 tcg_temp_free_ptr(a0);
181 tcg_temp_free_ptr(a1);
182 tcg_temp_free_ptr(a2);
183 tcg_temp_free_ptr(a3);
184 tcg_temp_free_i32(desc);
185}
186
187/* Generate a call to a gvec-style helper with five vector operands. */
188void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
189 uint32_t cofs, uint32_t xofs, uint32_t oprsz,
190 uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn)
191{
192 TCGv_ptr a0, a1, a2, a3, a4;
193 TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
194
195 a0 = tcg_temp_new_ptr();
196 a1 = tcg_temp_new_ptr();
197 a2 = tcg_temp_new_ptr();
198 a3 = tcg_temp_new_ptr();
199 a4 = tcg_temp_new_ptr();
200
201 tcg_gen_addi_ptr(a0, cpu_env, dofs);
202 tcg_gen_addi_ptr(a1, cpu_env, aofs);
203 tcg_gen_addi_ptr(a2, cpu_env, bofs);
204 tcg_gen_addi_ptr(a3, cpu_env, cofs);
205 tcg_gen_addi_ptr(a4, cpu_env, xofs);
206
207 fn(a0, a1, a2, a3, a4, desc);
208
209 tcg_temp_free_ptr(a0);
210 tcg_temp_free_ptr(a1);
211 tcg_temp_free_ptr(a2);
212 tcg_temp_free_ptr(a3);
213 tcg_temp_free_ptr(a4);
214 tcg_temp_free_i32(desc);
215}
216
217/* Generate a call to a gvec-style helper with three vector operands
218 and an extra pointer operand. */
219void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs,
220 TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
221 int32_t data, gen_helper_gvec_2_ptr *fn)
222{
223 TCGv_ptr a0, a1;
224 TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
225
226 a0 = tcg_temp_new_ptr();
227 a1 = tcg_temp_new_ptr();
228
229 tcg_gen_addi_ptr(a0, cpu_env, dofs);
230 tcg_gen_addi_ptr(a1, cpu_env, aofs);
231
232 fn(a0, a1, ptr, desc);
233
234 tcg_temp_free_ptr(a0);
235 tcg_temp_free_ptr(a1);
236 tcg_temp_free_i32(desc);
237}
238
239/* Generate a call to a gvec-style helper with three vector operands
240 and an extra pointer operand. */
241void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
242 TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
243 int32_t data, gen_helper_gvec_3_ptr *fn)
244{
245 TCGv_ptr a0, a1, a2;
246 TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
247
248 a0 = tcg_temp_new_ptr();
249 a1 = tcg_temp_new_ptr();
250 a2 = tcg_temp_new_ptr();
251
252 tcg_gen_addi_ptr(a0, cpu_env, dofs);
253 tcg_gen_addi_ptr(a1, cpu_env, aofs);
254 tcg_gen_addi_ptr(a2, cpu_env, bofs);
255
256 fn(a0, a1, a2, ptr, desc);
257
258 tcg_temp_free_ptr(a0);
259 tcg_temp_free_ptr(a1);
260 tcg_temp_free_ptr(a2);
261 tcg_temp_free_i32(desc);
262}
263
264/* Generate a call to a gvec-style helper with four vector operands
265 and an extra pointer operand. */
266void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
267 uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz,
268 uint32_t maxsz, int32_t data,
269 gen_helper_gvec_4_ptr *fn)
270{
271 TCGv_ptr a0, a1, a2, a3;
272 TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
273
274 a0 = tcg_temp_new_ptr();
275 a1 = tcg_temp_new_ptr();
276 a2 = tcg_temp_new_ptr();
277 a3 = tcg_temp_new_ptr();
278
279 tcg_gen_addi_ptr(a0, cpu_env, dofs);
280 tcg_gen_addi_ptr(a1, cpu_env, aofs);
281 tcg_gen_addi_ptr(a2, cpu_env, bofs);
282 tcg_gen_addi_ptr(a3, cpu_env, cofs);
283
284 fn(a0, a1, a2, a3, ptr, desc);
285
286 tcg_temp_free_ptr(a0);
287 tcg_temp_free_ptr(a1);
288 tcg_temp_free_ptr(a2);
289 tcg_temp_free_ptr(a3);
290 tcg_temp_free_i32(desc);
291}
292
293/* Return true if we want to implement something of OPRSZ bytes
294 in units of LNSZ. This limits the expansion of inline code. */
295static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
296{
499748d7
RH		 297 if (oprsz % lnsz == 0) {
298 uint32_t lnct = oprsz / lnsz;
299 return lnct >= 1 && lnct <= MAX_UNROLL;
300 }
301 return false;
db432672
RH		 302}
303
304static void expand_clr(uint32_t dofs, uint32_t maxsz);
305
306/* Duplicate C as per VECE. */
307uint64_t (dup_const)(unsigned vece, uint64_t c)
308{
309 switch (vece) {
310 case MO_8:
311 return 0x0101010101010101ull * (uint8_t)c;
312 case MO_16:
313 return 0x0001000100010001ull * (uint16_t)c;
314 case MO_32:
315 return 0x0000000100000001ull * (uint32_t)c;
316 case MO_64:
317 return c;
318 default:
319 g_assert_not_reached();
320 }
321}
322
323/* Duplicate IN into OUT as per VECE. */
324static void gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in)
325{
326 switch (vece) {
327 case MO_8:
328 tcg_gen_ext8u_i32(out, in);
329 tcg_gen_muli_i32(out, out, 0x01010101);
330 break;
331 case MO_16:
332 tcg_gen_deposit_i32(out, in, in, 16, 16);
333 break;
334 case MO_32:
335 tcg_gen_mov_i32(out, in);
336 break;
337 default:
338 g_assert_not_reached();
339 }
340}
341
342static void gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in)
343{
344 switch (vece) {
345 case MO_8:
346 tcg_gen_ext8u_i64(out, in);
347 tcg_gen_muli_i64(out, out, 0x0101010101010101ull);
348 break;
349 case MO_16:
350 tcg_gen_ext16u_i64(out, in);
351 tcg_gen_muli_i64(out, out, 0x0001000100010001ull);
352 break;
353 case MO_32:
354 tcg_gen_deposit_i64(out, in, in, 32, 32);
355 break;
356 case MO_64:
357 tcg_gen_mov_i64(out, in);
358 break;
359 default:
360 g_assert_not_reached();
361 }
362}
363
adb196cb
RH		 364/* Select a supported vector type for implementing an operation on SIZE
365 * bytes. If OP is 0, assume that the real operation to be performed is
366 * required by all backends. Otherwise, make sure than OP can be performed
367 * on elements of size VECE in the selected type. Do not select V64 if
368 * PREFER_I64 is true. Return 0 if no vector type is selected.
369 */
53229a77
RH		 370static TCGType choose_vector_type(const TCGOpcode *list, unsigned vece,
371 uint32_t size, bool prefer_i64)
adb196cb
RH		 372{
373 if (TCG_TARGET_HAS_v256 && check_size_impl(size, 32)) {
53229a77
RH		 374 /*
375 * Recall that ARM SVE allows vector sizes that are not a
adb196cb
RH		 376 * power of 2, but always a multiple of 16. The intent is
377 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
378 * It is hard to imagine a case in which v256 is supported
379 * but v128 is not, but check anyway.
380 */
53229a77 381 if (tcg_can_emit_vecop_list(list, TCG_TYPE_V256, vece)
adb196cb 382 && (size % 32 == 0
53229a77 383 || tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece))) {
adb196cb
RH		 384 return TCG_TYPE_V256;
385 }
386 }
387 if (TCG_TARGET_HAS_v128 && check_size_impl(size, 16)
53229a77 388 && tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece)) {
adb196cb
RH		 389 return TCG_TYPE_V128;
390 }
391 if (TCG_TARGET_HAS_v64 && !prefer_i64 && check_size_impl(size, 8)
53229a77 392 && tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)) {
adb196cb
RH		 393 return TCG_TYPE_V64;
394 }
395 return 0;
396}
397
db432672
RH		 398/* Set OPRSZ bytes at DOFS to replications of IN_32, IN_64 or IN_C.
399 * Only one of IN_32 or IN_64 may be set;
400 * IN_C is used if IN_32 and IN_64 are unset.
401 */
402static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,
403 uint32_t maxsz, TCGv_i32 in_32, TCGv_i64 in_64,
404 uint64_t in_c)
405{
406 TCGType type;
407 TCGv_i64 t_64;
408 TCGv_i32 t_32, t_desc;
409 TCGv_ptr t_ptr;
410 uint32_t i;
411
412 assert(vece <= (in_32 ? MO_32 : MO_64));
413 assert(in_32 == NULL || in_64 == NULL);
414
415 /* If we're storing 0, expand oprsz to maxsz. */
416 if (in_32 == NULL && in_64 == NULL) {
417 in_c = dup_const(vece, in_c);
418 if (in_c == 0) {
419 oprsz = maxsz;
420 }
421 }
422
adb196cb
RH		 423 /* Implement inline with a vector type, if possible.
424 * Prefer integer when 64-bit host and no variable dup.
425 */
53229a77 426 type = choose_vector_type(NULL, vece, oprsz,
adb196cb
RH		 427 (TCG_TARGET_REG_BITS == 64 && in_32 == NULL
428 && (in_64 == NULL || vece == MO_64)));
db432672
RH		 429 if (type != 0) {
430 TCGv_vec t_vec = tcg_temp_new_vec(type);
431
432 if (in_32) {
433 tcg_gen_dup_i32_vec(vece, t_vec, in_32);
434 } else if (in_64) {
435 tcg_gen_dup_i64_vec(vece, t_vec, in_64);
436 } else {
437 switch (vece) {
438 case MO_8:
439 tcg_gen_dup8i_vec(t_vec, in_c);
440 break;
441 case MO_16:
442 tcg_gen_dup16i_vec(t_vec, in_c);
443 break;
444 case MO_32:
445 tcg_gen_dup32i_vec(t_vec, in_c);
446 break;
447 default:
448 tcg_gen_dup64i_vec(t_vec, in_c);
449 break;
450 }
451 }
452
453 i = 0;
adb196cb
RH		 454 switch (type) {
455 case TCG_TYPE_V256:
456 /* Recall that ARM SVE allows vector sizes that are not a
457 * power of 2, but always a multiple of 16. The intent is
458 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
459 */
db432672
RH		 460 for (; i + 32 <= oprsz; i += 32) {
461 tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256);
462 }
adb196cb
RH		 463 /* fallthru */
464 case TCG_TYPE_V128:
db432672
RH		 465 for (; i + 16 <= oprsz; i += 16) {
466 tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128);
467 }
adb196cb
RH		 468 break;
469 case TCG_TYPE_V64:
db432672
RH		 470 for (; i < oprsz; i += 8) {
471 tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64);
472 }
adb196cb
RH		 473 break;
474 default:
475 g_assert_not_reached();
db432672 476 }
adb196cb 477
db432672
RH		 478 tcg_temp_free_vec(t_vec);
479 goto done;
480 }
481
482 /* Otherwise, inline with an integer type, unless "large". */
483 if (check_size_impl(oprsz, TCG_TARGET_REG_BITS / 8)) {
484 t_64 = NULL;
485 t_32 = NULL;
486
487 if (in_32) {
488 /* We are given a 32-bit variable input. For a 64-bit host,
489 use a 64-bit operation unless the 32-bit operation would
490 be simple enough. */
491 if (TCG_TARGET_REG_BITS == 64
492 && (vece != MO_32 || !check_size_impl(oprsz, 4))) {
493 t_64 = tcg_temp_new_i64();
494 tcg_gen_extu_i32_i64(t_64, in_32);
495 gen_dup_i64(vece, t_64, t_64);
496 } else {
497 t_32 = tcg_temp_new_i32();
498 gen_dup_i32(vece, t_32, in_32);
499 }
500 } else if (in_64) {
501 /* We are given a 64-bit variable input. */
502 t_64 = tcg_temp_new_i64();
503 gen_dup_i64(vece, t_64, in_64);
504 } else {
505 /* We are given a constant input. */
506 /* For 64-bit hosts, use 64-bit constants for "simple" constants
507 or when we'd need too many 32-bit stores, or when a 64-bit
508 constant is really required. */
509 if (vece == MO_64
510 || (TCG_TARGET_REG_BITS == 64
511 && (in_c == 0 || in_c == -1
512 || !check_size_impl(oprsz, 4)))) {
513 t_64 = tcg_const_i64(in_c);
514 } else {
515 t_32 = tcg_const_i32(in_c);
516 }
517 }
518
519 /* Implement inline if we picked an implementation size above. */
520 if (t_32) {
521 for (i = 0; i < oprsz; i += 4) {
522 tcg_gen_st_i32(t_32, cpu_env, dofs + i);
523 }
524 tcg_temp_free_i32(t_32);
525 goto done;
526 }
527 if (t_64) {
528 for (i = 0; i < oprsz; i += 8) {
529 tcg_gen_st_i64(t_64, cpu_env, dofs + i);
530 }
531 tcg_temp_free_i64(t_64);
532 goto done;
adb196cb 533 }
db432672
RH		 534 }
535
536 /* Otherwise implement out of line. */
537 t_ptr = tcg_temp_new_ptr();
538 tcg_gen_addi_ptr(t_ptr, cpu_env, dofs);
539 t_desc = tcg_const_i32(simd_desc(oprsz, maxsz, 0));
540
541 if (vece == MO_64) {
542 if (in_64) {
543 gen_helper_gvec_dup64(t_ptr, t_desc, in_64);
544 } else {
545 t_64 = tcg_const_i64(in_c);
546 gen_helper_gvec_dup64(t_ptr, t_desc, t_64);
547 tcg_temp_free_i64(t_64);
548 }
549 } else {
550 typedef void dup_fn(TCGv_ptr, TCGv_i32, TCGv_i32);
551 static dup_fn * const fns[3] = {
552 gen_helper_gvec_dup8,
553 gen_helper_gvec_dup16,
554 gen_helper_gvec_dup32
555 };
556
557 if (in_32) {
558 fns[vece](t_ptr, t_desc, in_32);
559 } else {
560 t_32 = tcg_temp_new_i32();
561 if (in_64) {
562 tcg_gen_extrl_i64_i32(t_32, in_64);
563 } else if (vece == MO_8) {
564 tcg_gen_movi_i32(t_32, in_c & 0xff);
565 } else if (vece == MO_16) {
566 tcg_gen_movi_i32(t_32, in_c & 0xffff);
567 } else {
568 tcg_gen_movi_i32(t_32, in_c);
569 }
570 fns[vece](t_ptr, t_desc, t_32);
571 tcg_temp_free_i32(t_32);
572 }
573 }
574
575 tcg_temp_free_ptr(t_ptr);
576 tcg_temp_free_i32(t_desc);
577 return;
578
579 done:
580 if (oprsz < maxsz) {
581 expand_clr(dofs + oprsz, maxsz - oprsz);
582 }
583}
584
585/* Likewise, but with zero. */
586static void expand_clr(uint32_t dofs, uint32_t maxsz)
587{
588 do_dup(MO_8, dofs, maxsz, maxsz, NULL, NULL, 0);
589}
590
591/* Expand OPSZ bytes worth of two-operand operations using i32 elements. */
592static void expand_2_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
593 void (*fni)(TCGv_i32, TCGv_i32))
594{
595 TCGv_i32 t0 = tcg_temp_new_i32();
596 uint32_t i;
597
598 for (i = 0; i < oprsz; i += 4) {
599 tcg_gen_ld_i32(t0, cpu_env, aofs + i);
600 fni(t0, t0);
601 tcg_gen_st_i32(t0, cpu_env, dofs + i);
602 }
603 tcg_temp_free_i32(t0);
604}
605
d0ec9796
RH		 606static void expand_2i_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
607 int32_t c, bool load_dest,
608 void (*fni)(TCGv_i32, TCGv_i32, int32_t))
609{
610 TCGv_i32 t0 = tcg_temp_new_i32();
611 TCGv_i32 t1 = tcg_temp_new_i32();
612 uint32_t i;
613
614 for (i = 0; i < oprsz; i += 4) {
615 tcg_gen_ld_i32(t0, cpu_env, aofs + i);
616 if (load_dest) {
617 tcg_gen_ld_i32(t1, cpu_env, dofs + i);
618 }
619 fni(t1, t0, c);
620 tcg_gen_st_i32(t1, cpu_env, dofs + i);
621 }
622 tcg_temp_free_i32(t0);
623 tcg_temp_free_i32(t1);
624}
625
22fc3527
RH		 626static void expand_2s_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
627 TCGv_i32 c, bool scalar_first,
628 void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32))
629{
630 TCGv_i32 t0 = tcg_temp_new_i32();
631 TCGv_i32 t1 = tcg_temp_new_i32();
632 uint32_t i;
633
634 for (i = 0; i < oprsz; i += 4) {
635 tcg_gen_ld_i32(t0, cpu_env, aofs + i);
636 if (scalar_first) {
637 fni(t1, c, t0);
638 } else {
639 fni(t1, t0, c);
640 }
641 tcg_gen_st_i32(t1, cpu_env, dofs + i);
642 }
643 tcg_temp_free_i32(t0);
644 tcg_temp_free_i32(t1);
645}
646
db432672
RH		 647/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
648static void expand_3_i32(uint32_t dofs, uint32_t aofs,
649 uint32_t bofs, uint32_t oprsz, bool load_dest,
650 void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32))
651{
652 TCGv_i32 t0 = tcg_temp_new_i32();
653 TCGv_i32 t1 = tcg_temp_new_i32();
654 TCGv_i32 t2 = tcg_temp_new_i32();
655 uint32_t i;
656
657 for (i = 0; i < oprsz; i += 4) {
658 tcg_gen_ld_i32(t0, cpu_env, aofs + i);
659 tcg_gen_ld_i32(t1, cpu_env, bofs + i);
660 if (load_dest) {
661 tcg_gen_ld_i32(t2, cpu_env, dofs + i);
662 }
663 fni(t2, t0, t1);
664 tcg_gen_st_i32(t2, cpu_env, dofs + i);
665 }
666 tcg_temp_free_i32(t2);
667 tcg_temp_free_i32(t1);
668 tcg_temp_free_i32(t0);
669}
670
e1227bb6
DH		 671static void expand_3i_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
672 uint32_t oprsz, int32_t c, bool load_dest,
673 void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, int32_t))
674{
675 TCGv_i32 t0 = tcg_temp_new_i32();
676 TCGv_i32 t1 = tcg_temp_new_i32();
677 TCGv_i32 t2 = tcg_temp_new_i32();
678 uint32_t i;
679
680 for (i = 0; i < oprsz; i += 4) {
681 tcg_gen_ld_i32(t0, cpu_env, aofs + i);
682 tcg_gen_ld_i32(t1, cpu_env, bofs + i);
683 if (load_dest) {
684 tcg_gen_ld_i32(t2, cpu_env, dofs + i);
685 }
686 fni(t2, t0, t1, c);
687 tcg_gen_st_i32(t2, cpu_env, dofs + i);
688 }
689 tcg_temp_free_i32(t0);
690 tcg_temp_free_i32(t1);
691 tcg_temp_free_i32(t2);
692}
693
db432672
RH		 694/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
695static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
5d6acdd4 696 uint32_t cofs, uint32_t oprsz, bool write_aofs,
db432672
RH		 697 void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32))
698{
699 TCGv_i32 t0 = tcg_temp_new_i32();
700 TCGv_i32 t1 = tcg_temp_new_i32();
701 TCGv_i32 t2 = tcg_temp_new_i32();
702 TCGv_i32 t3 = tcg_temp_new_i32();
703 uint32_t i;
704
705 for (i = 0; i < oprsz; i += 4) {
706 tcg_gen_ld_i32(t1, cpu_env, aofs + i);
707 tcg_gen_ld_i32(t2, cpu_env, bofs + i);
708 tcg_gen_ld_i32(t3, cpu_env, cofs + i);
709 fni(t0, t1, t2, t3);
710 tcg_gen_st_i32(t0, cpu_env, dofs + i);
5d6acdd4
RH		 711 if (write_aofs) {
712 tcg_gen_st_i32(t1, cpu_env, aofs + i);
713 }
db432672
RH		 714 }
715 tcg_temp_free_i32(t3);
716 tcg_temp_free_i32(t2);
717 tcg_temp_free_i32(t1);
718 tcg_temp_free_i32(t0);
719}
720
721/* Expand OPSZ bytes worth of two-operand operations using i64 elements. */
722static void expand_2_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
723 void (*fni)(TCGv_i64, TCGv_i64))
724{
725 TCGv_i64 t0 = tcg_temp_new_i64();
726 uint32_t i;
727
728 for (i = 0; i < oprsz; i += 8) {
729 tcg_gen_ld_i64(t0, cpu_env, aofs + i);
730 fni(t0, t0);
731 tcg_gen_st_i64(t0, cpu_env, dofs + i);
732 }
733 tcg_temp_free_i64(t0);
734}
735
d0ec9796
RH		 736static void expand_2i_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
737 int64_t c, bool load_dest,
738 void (*fni)(TCGv_i64, TCGv_i64, int64_t))
739{
740 TCGv_i64 t0 = tcg_temp_new_i64();
741 TCGv_i64 t1 = tcg_temp_new_i64();
742 uint32_t i;
743
744 for (i = 0; i < oprsz; i += 8) {
745 tcg_gen_ld_i64(t0, cpu_env, aofs + i);
746 if (load_dest) {
747 tcg_gen_ld_i64(t1, cpu_env, dofs + i);
748 }
749 fni(t1, t0, c);
750 tcg_gen_st_i64(t1, cpu_env, dofs + i);
751 }
752 tcg_temp_free_i64(t0);
753 tcg_temp_free_i64(t1);
754}
755
22fc3527
RH		 756static void expand_2s_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
757 TCGv_i64 c, bool scalar_first,
758 void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64))
759{
760 TCGv_i64 t0 = tcg_temp_new_i64();
761 TCGv_i64 t1 = tcg_temp_new_i64();
762 uint32_t i;
763
764 for (i = 0; i < oprsz; i += 8) {
765 tcg_gen_ld_i64(t0, cpu_env, aofs + i);
766 if (scalar_first) {
767 fni(t1, c, t0);
768 } else {
769 fni(t1, t0, c);
770 }
771 tcg_gen_st_i64(t1, cpu_env, dofs + i);
772 }
773 tcg_temp_free_i64(t0);
774 tcg_temp_free_i64(t1);
775}
776
db432672
RH		 777/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
778static void expand_3_i64(uint32_t dofs, uint32_t aofs,
779 uint32_t bofs, uint32_t oprsz, bool load_dest,
780 void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64))
781{
782 TCGv_i64 t0 = tcg_temp_new_i64();
783 TCGv_i64 t1 = tcg_temp_new_i64();
784 TCGv_i64 t2 = tcg_temp_new_i64();
785 uint32_t i;
786
787 for (i = 0; i < oprsz; i += 8) {
788 tcg_gen_ld_i64(t0, cpu_env, aofs + i);
789 tcg_gen_ld_i64(t1, cpu_env, bofs + i);
790 if (load_dest) {
791 tcg_gen_ld_i64(t2, cpu_env, dofs + i);
792 }
793 fni(t2, t0, t1);
794 tcg_gen_st_i64(t2, cpu_env, dofs + i);
795 }
796 tcg_temp_free_i64(t2);
797 tcg_temp_free_i64(t1);
798 tcg_temp_free_i64(t0);
799}
800
e1227bb6
DH		 801static void expand_3i_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
802 uint32_t oprsz, int64_t c, bool load_dest,
803 void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, int64_t))
804{
805 TCGv_i64 t0 = tcg_temp_new_i64();
806 TCGv_i64 t1 = tcg_temp_new_i64();
807 TCGv_i64 t2 = tcg_temp_new_i64();
808 uint32_t i;
809
810 for (i = 0; i < oprsz; i += 8) {
811 tcg_gen_ld_i64(t0, cpu_env, aofs + i);
812 tcg_gen_ld_i64(t1, cpu_env, bofs + i);
813 if (load_dest) {
814 tcg_gen_ld_i64(t2, cpu_env, dofs + i);
815 }
816 fni(t2, t0, t1, c);
817 tcg_gen_st_i64(t2, cpu_env, dofs + i);
818 }
819 tcg_temp_free_i64(t0);
820 tcg_temp_free_i64(t1);
821 tcg_temp_free_i64(t2);
822}
823
db432672
RH		 824/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
825static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
5d6acdd4 826 uint32_t cofs, uint32_t oprsz, bool write_aofs,
db432672
RH		 827 void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
828{
829 TCGv_i64 t0 = tcg_temp_new_i64();
830 TCGv_i64 t1 = tcg_temp_new_i64();
831 TCGv_i64 t2 = tcg_temp_new_i64();
832 TCGv_i64 t3 = tcg_temp_new_i64();
833 uint32_t i;
834
835 for (i = 0; i < oprsz; i += 8) {
836 tcg_gen_ld_i64(t1, cpu_env, aofs + i);
837 tcg_gen_ld_i64(t2, cpu_env, bofs + i);
838 tcg_gen_ld_i64(t3, cpu_env, cofs + i);
839 fni(t0, t1, t2, t3);
840 tcg_gen_st_i64(t0, cpu_env, dofs + i);
5d6acdd4
RH		 841 if (write_aofs) {
842 tcg_gen_st_i64(t1, cpu_env, aofs + i);
843 }
db432672
RH		 844 }
845 tcg_temp_free_i64(t3);
846 tcg_temp_free_i64(t2);
847 tcg_temp_free_i64(t1);
848 tcg_temp_free_i64(t0);
849}
850
851/* Expand OPSZ bytes worth of two-operand operations using host vectors. */
852static void expand_2_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
853 uint32_t oprsz, uint32_t tysz, TCGType type,
854 void (*fni)(unsigned, TCGv_vec, TCGv_vec))
855{
856 TCGv_vec t0 = tcg_temp_new_vec(type);
857 uint32_t i;
858
859 for (i = 0; i < oprsz; i += tysz) {
860 tcg_gen_ld_vec(t0, cpu_env, aofs + i);
861 fni(vece, t0, t0);
862 tcg_gen_st_vec(t0, cpu_env, dofs + i);
863 }
864 tcg_temp_free_vec(t0);
865}
866
d0ec9796
RH		 867/* Expand OPSZ bytes worth of two-vector operands and an immediate operand
868 using host vectors. */
869static void expand_2i_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
870 uint32_t oprsz, uint32_t tysz, TCGType type,
871 int64_t c, bool load_dest,
872 void (*fni)(unsigned, TCGv_vec, TCGv_vec, int64_t))
873{
874 TCGv_vec t0 = tcg_temp_new_vec(type);
875 TCGv_vec t1 = tcg_temp_new_vec(type);
876 uint32_t i;
877
878 for (i = 0; i < oprsz; i += tysz) {
879 tcg_gen_ld_vec(t0, cpu_env, aofs + i);
880 if (load_dest) {
881 tcg_gen_ld_vec(t1, cpu_env, dofs + i);
882 }
883 fni(vece, t1, t0, c);
884 tcg_gen_st_vec(t1, cpu_env, dofs + i);
885 }
886 tcg_temp_free_vec(t0);
887 tcg_temp_free_vec(t1);
888}
889
22fc3527
RH		 890static void expand_2s_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
891 uint32_t oprsz, uint32_t tysz, TCGType type,
892 TCGv_vec c, bool scalar_first,
893 void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec))
894{
895 TCGv_vec t0 = tcg_temp_new_vec(type);
896 TCGv_vec t1 = tcg_temp_new_vec(type);
897 uint32_t i;
898
899 for (i = 0; i < oprsz; i += tysz) {
900 tcg_gen_ld_vec(t0, cpu_env, aofs + i);
901 if (scalar_first) {
902 fni(vece, t1, c, t0);
903 } else {
904 fni(vece, t1, t0, c);
905 }
906 tcg_gen_st_vec(t1, cpu_env, dofs + i);
907 }
908 tcg_temp_free_vec(t0);
909 tcg_temp_free_vec(t1);
910}
911
db432672
RH		 912/* Expand OPSZ bytes worth of three-operand operations using host vectors. */
913static void expand_3_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
914 uint32_t bofs, uint32_t oprsz,
915 uint32_t tysz, TCGType type, bool load_dest,
916 void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec))
917{
918 TCGv_vec t0 = tcg_temp_new_vec(type);
919 TCGv_vec t1 = tcg_temp_new_vec(type);
920 TCGv_vec t2 = tcg_temp_new_vec(type);
921 uint32_t i;
922
923 for (i = 0; i < oprsz; i += tysz) {
924 tcg_gen_ld_vec(t0, cpu_env, aofs + i);
925 tcg_gen_ld_vec(t1, cpu_env, bofs + i);
926 if (load_dest) {
927 tcg_gen_ld_vec(t2, cpu_env, dofs + i);
928 }
929 fni(vece, t2, t0, t1);
930 tcg_gen_st_vec(t2, cpu_env, dofs + i);
931 }
932 tcg_temp_free_vec(t2);
933 tcg_temp_free_vec(t1);
934 tcg_temp_free_vec(t0);
935}
936
e1227bb6
DH		 937/*
938 * Expand OPSZ bytes worth of three-vector operands and an immediate operand
939 * using host vectors.
940 */
941static void expand_3i_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
942 uint32_t bofs, uint32_t oprsz, uint32_t tysz,
943 TCGType type, int64_t c, bool load_dest,
944 void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec,
945 int64_t))
946{
947 TCGv_vec t0 = tcg_temp_new_vec(type);
948 TCGv_vec t1 = tcg_temp_new_vec(type);
949 TCGv_vec t2 = tcg_temp_new_vec(type);
950 uint32_t i;
951
952 for (i = 0; i < oprsz; i += tysz) {
953 tcg_gen_ld_vec(t0, cpu_env, aofs + i);
954 tcg_gen_ld_vec(t1, cpu_env, bofs + i);
955 if (load_dest) {
956 tcg_gen_ld_vec(t2, cpu_env, dofs + i);
957 }
958 fni(vece, t2, t0, t1, c);
959 tcg_gen_st_vec(t2, cpu_env, dofs + i);
960 }
961 tcg_temp_free_vec(t0);
962 tcg_temp_free_vec(t1);
963 tcg_temp_free_vec(t2);
964}
965
db432672
RH		 966/* Expand OPSZ bytes worth of four-operand operations using host vectors. */
967static void expand_4_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
968 uint32_t bofs, uint32_t cofs, uint32_t oprsz,
5d6acdd4 969 uint32_t tysz, TCGType type, bool write_aofs,
db432672
RH		 970 void (*fni)(unsigned, TCGv_vec, TCGv_vec,
971 TCGv_vec, TCGv_vec))
972{
973 TCGv_vec t0 = tcg_temp_new_vec(type);
974 TCGv_vec t1 = tcg_temp_new_vec(type);
975 TCGv_vec t2 = tcg_temp_new_vec(type);
976 TCGv_vec t3 = tcg_temp_new_vec(type);
977 uint32_t i;
978
979 for (i = 0; i < oprsz; i += tysz) {
980 tcg_gen_ld_vec(t1, cpu_env, aofs + i);
981 tcg_gen_ld_vec(t2, cpu_env, bofs + i);
982 tcg_gen_ld_vec(t3, cpu_env, cofs + i);
983 fni(vece, t0, t1, t2, t3);
984 tcg_gen_st_vec(t0, cpu_env, dofs + i);
5d6acdd4
RH		 985 if (write_aofs) {
986 tcg_gen_st_vec(t1, cpu_env, aofs + i);
987 }
db432672
RH		 988 }
989 tcg_temp_free_vec(t3);
990 tcg_temp_free_vec(t2);
991 tcg_temp_free_vec(t1);
992 tcg_temp_free_vec(t0);
993}
994
995/* Expand a vector two-operand operation. */
996void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
997 uint32_t oprsz, uint32_t maxsz, const GVecGen2 *g)
998{
53229a77
RH		 999 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
1000 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
adb196cb
RH		 1001 TCGType type;
1002 uint32_t some;
1003
db432672
RH		 1004 check_size_align(oprsz, maxsz, dofs | aofs);
1005 check_overlap_2(dofs, aofs, maxsz);
1006
adb196cb
RH		 1007 type = 0;
1008 if (g->fniv) {
53229a77 1009 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
adb196cb
RH		 1010 }
1011 switch (type) {
1012 case TCG_TYPE_V256:
1013 /* Recall that ARM SVE allows vector sizes that are not a
1014 * power of 2, but always a multiple of 16. The intent is
1015 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
1016 */
1017 some = QEMU_ALIGN_DOWN(oprsz, 32);
db432672
RH		 1018 expand_2_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, g->fniv);
1019 if (some == oprsz) {
adb196cb 1020 break;
db432672
RH		 1021 }
1022 dofs += some;
1023 aofs += some;
1024 oprsz -= some;
1025 maxsz -= some;
adb196cb
RH		 1026 /* fallthru */
1027 case TCG_TYPE_V128:
db432672 1028 expand_2_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, g->fniv);
adb196cb
RH		 1029 break;
1030 case TCG_TYPE_V64:
db432672 1031 expand_2_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, g->fniv);
adb196cb
RH		 1032 break;
1033
1034 case 0:
1035 if (g->fni8 && check_size_impl(oprsz, 8)) {
1036 expand_2_i64(dofs, aofs, oprsz, g->fni8);
1037 } else if (g->fni4 && check_size_impl(oprsz, 4)) {
1038 expand_2_i32(dofs, aofs, oprsz, g->fni4);
1039 } else {
1040 assert(g->fno != NULL);
1041 tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, g->data, g->fno);
53229a77 1042 oprsz = maxsz;
adb196cb
RH		 1043 }
1044 break;
1045
1046 default:
1047 g_assert_not_reached();
db432672 1048 }
53229a77 1049 tcg_swap_vecop_list(hold_list);
db432672 1050
db432672
RH		 1051 if (oprsz < maxsz) {
1052 expand_clr(dofs + oprsz, maxsz - oprsz);
1053 }
1054}
1055
22fc3527 1056/* Expand a vector operation with two vectors and an immediate. */
d0ec9796
RH		 1057void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
1058 uint32_t maxsz, int64_t c, const GVecGen2i *g)
1059{
53229a77
RH		 1060 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
1061 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
adb196cb
RH		 1062 TCGType type;
1063 uint32_t some;
1064
d0ec9796
RH		 1065 check_size_align(oprsz, maxsz, dofs | aofs);
1066 check_overlap_2(dofs, aofs, maxsz);
1067
adb196cb
RH		 1068 type = 0;
1069 if (g->fniv) {
53229a77 1070 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
adb196cb
RH		 1071 }
1072 switch (type) {
1073 case TCG_TYPE_V256:
1074 /* Recall that ARM SVE allows vector sizes that are not a
1075 * power of 2, but always a multiple of 16. The intent is
1076 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
1077 */
1078 some = QEMU_ALIGN_DOWN(oprsz, 32);
d0ec9796
RH		 1079 expand_2i_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256,
1080 c, g->load_dest, g->fniv);
1081 if (some == oprsz) {
adb196cb 1082 break;
d0ec9796
RH		 1083 }
1084 dofs += some;
1085 aofs += some;
1086 oprsz -= some;
1087 maxsz -= some;
adb196cb
RH		 1088 /* fallthru */
1089 case TCG_TYPE_V128:
d0ec9796
RH		 1090 expand_2i_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128,
1091 c, g->load_dest, g->fniv);
adb196cb
RH		 1092 break;
1093 case TCG_TYPE_V64:
d0ec9796
RH		 1094 expand_2i_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64,
1095 c, g->load_dest, g->fniv);
adb196cb
RH		 1096 break;
1097
1098 case 0:
1099 if (g->fni8 && check_size_impl(oprsz, 8)) {
1100 expand_2i_i64(dofs, aofs, oprsz, c, g->load_dest, g->fni8);
1101 } else if (g->fni4 && check_size_impl(oprsz, 4)) {
1102 expand_2i_i32(dofs, aofs, oprsz, c, g->load_dest, g->fni4);
22fc3527 1103 } else {
adb196cb
RH		 1104 if (g->fno) {
1105 tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, c, g->fno);
1106 } else {
1107 TCGv_i64 tcg_c = tcg_const_i64(c);
1108 tcg_gen_gvec_2i_ool(dofs, aofs, tcg_c, oprsz,
1109 maxsz, c, g->fnoi);
1110 tcg_temp_free_i64(tcg_c);
1111 }
53229a77 1112 oprsz = maxsz;
22fc3527 1113 }
adb196cb
RH		 1114 break;
1115
1116 default:
1117 g_assert_not_reached();
d0ec9796 1118 }
53229a77 1119 tcg_swap_vecop_list(hold_list);
d0ec9796 1120
d0ec9796
RH		 1121 if (oprsz < maxsz) {
1122 expand_clr(dofs + oprsz, maxsz - oprsz);
1123 }
1124}
1125
22fc3527
RH		 1126/* Expand a vector operation with two vectors and a scalar. */
1127void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
1128 uint32_t maxsz, TCGv_i64 c, const GVecGen2s *g)
1129{
1130 TCGType type;
1131
1132 check_size_align(oprsz, maxsz, dofs | aofs);
1133 check_overlap_2(dofs, aofs, maxsz);
1134
1135 type = 0;
1136 if (g->fniv) {
53229a77 1137 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
22fc3527
RH		 1138 }
1139 if (type != 0) {
53229a77
RH		 1140 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
1141 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
22fc3527 1142 TCGv_vec t_vec = tcg_temp_new_vec(type);
adb196cb 1143 uint32_t some;
22fc3527
RH		 1144
1145 tcg_gen_dup_i64_vec(g->vece, t_vec, c);
1146
22fc3527
RH		 1147 switch (type) {
1148 case TCG_TYPE_V256:
adb196cb
RH		 1149 /* Recall that ARM SVE allows vector sizes that are not a
1150 * power of 2, but always a multiple of 16. The intent is
1151 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
1152 */
1153 some = QEMU_ALIGN_DOWN(oprsz, 32);
1154 expand_2s_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256,
1155 t_vec, g->scalar_first, g->fniv);
1156 if (some == oprsz) {
1157 break;
22fc3527 1158 }
adb196cb
RH		 1159 dofs += some;
1160 aofs += some;
1161 oprsz -= some;
1162 maxsz -= some;
22fc3527
RH		 1163 /* fallthru */
1164
1165 case TCG_TYPE_V128:
1166 expand_2s_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128,
1167 t_vec, g->scalar_first, g->fniv);
1168 break;
1169
1170 case TCG_TYPE_V64:
1171 expand_2s_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64,
1172 t_vec, g->scalar_first, g->fniv);
1173 break;
1174
1175 default:
1176 g_assert_not_reached();
1177 }
1178 tcg_temp_free_vec(t_vec);
53229a77 1179 tcg_swap_vecop_list(hold_list);
22fc3527
RH		 1180 } else if (g->fni8 && check_size_impl(oprsz, 8)) {
1181 TCGv_i64 t64 = tcg_temp_new_i64();
1182
1183 gen_dup_i64(g->vece, t64, c);
1184 expand_2s_i64(dofs, aofs, oprsz, t64, g->scalar_first, g->fni8);
1185 tcg_temp_free_i64(t64);
1186 } else if (g->fni4 && check_size_impl(oprsz, 4)) {
1187 TCGv_i32 t32 = tcg_temp_new_i32();
1188
1189 tcg_gen_extrl_i64_i32(t32, c);
1190 gen_dup_i32(g->vece, t32, t32);
1191 expand_2s_i32(dofs, aofs, oprsz, t32, g->scalar_first, g->fni4);
1192 tcg_temp_free_i32(t32);
1193 } else {
1194 tcg_gen_gvec_2i_ool(dofs, aofs, c, oprsz, maxsz, 0, g->fno);
1195 return;
1196 }
1197
1198 if (oprsz < maxsz) {
1199 expand_clr(dofs + oprsz, maxsz - oprsz);
1200 }
1201}
1202
db432672
RH		 1203/* Expand a vector three-operand operation. */
1204void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
1205 uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g)
1206{
53229a77
RH		 1207 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
1208 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
adb196cb
RH		 1209 TCGType type;
1210 uint32_t some;
1211
db432672
RH		 1212 check_size_align(oprsz, maxsz, dofs | aofs | bofs);
1213 check_overlap_3(dofs, aofs, bofs, maxsz);
1214
adb196cb
RH		 1215 type = 0;
1216 if (g->fniv) {
53229a77 1217 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
adb196cb
RH		 1218 }
1219 switch (type) {
1220 case TCG_TYPE_V256:
1221 /* Recall that ARM SVE allows vector sizes that are not a
1222 * power of 2, but always a multiple of 16. The intent is
1223 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
1224 */
1225 some = QEMU_ALIGN_DOWN(oprsz, 32);
db432672
RH		 1226 expand_3_vec(g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256,
1227 g->load_dest, g->fniv);
1228 if (some == oprsz) {
adb196cb 1229 break;
db432672
RH		 1230 }
1231 dofs += some;
1232 aofs += some;
1233 bofs += some;
1234 oprsz -= some;
1235 maxsz -= some;
adb196cb
RH		 1236 /* fallthru */
1237 case TCG_TYPE_V128:
db432672
RH		 1238 expand_3_vec(g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128,
1239 g->load_dest, g->fniv);
adb196cb
RH		 1240 break;
1241 case TCG_TYPE_V64:
db432672
RH		 1242 expand_3_vec(g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64,
1243 g->load_dest, g->fniv);
adb196cb
RH		 1244 break;
1245
1246 case 0:
1247 if (g->fni8 && check_size_impl(oprsz, 8)) {
1248 expand_3_i64(dofs, aofs, bofs, oprsz, g->load_dest, g->fni8);
1249 } else if (g->fni4 && check_size_impl(oprsz, 4)) {
1250 expand_3_i32(dofs, aofs, bofs, oprsz, g->load_dest, g->fni4);
1251 } else {
1252 assert(g->fno != NULL);
1253 tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz,
1254 maxsz, g->data, g->fno);
53229a77 1255 oprsz = maxsz;
adb196cb
RH		 1256 }
1257 break;
1258
1259 default:
1260 g_assert_not_reached();
db432672 1261 }
53229a77 1262 tcg_swap_vecop_list(hold_list);
db432672 1263
db432672
RH		 1264 if (oprsz < maxsz) {
1265 expand_clr(dofs + oprsz, maxsz - oprsz);
1266 }
1267}
1268
e1227bb6
DH		 1269/* Expand a vector operation with three vectors and an immediate. */
1270void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs,
1271 uint32_t oprsz, uint32_t maxsz, int64_t c,
1272 const GVecGen3i *g)
1273{
53229a77
RH		 1274 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
1275 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
e1227bb6
DH		 1276 TCGType type;
1277 uint32_t some;
1278
1279 check_size_align(oprsz, maxsz, dofs | aofs | bofs);
1280 check_overlap_3(dofs, aofs, bofs, maxsz);
1281
1282 type = 0;
1283 if (g->fniv) {
53229a77 1284 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
e1227bb6
DH		 1285 }
1286 switch (type) {
1287 case TCG_TYPE_V256:
1288 /*
1289 * Recall that ARM SVE allows vector sizes that are not a
1290 * power of 2, but always a multiple of 16. The intent is
1291 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
1292 */
1293 some = QEMU_ALIGN_DOWN(oprsz, 32);
1294 expand_3i_vec(g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256,
1295 c, g->load_dest, g->fniv);
1296 if (some == oprsz) {
1297 break;
1298 }
1299 dofs += some;
1300 aofs += some;
1301 bofs += some;
1302 oprsz -= some;
1303 maxsz -= some;
1304 /* fallthru */
1305 case TCG_TYPE_V128:
1306 expand_3i_vec(g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128,
1307 c, g->load_dest, g->fniv);
1308 break;
1309 case TCG_TYPE_V64:
1310 expand_3i_vec(g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64,
1311 c, g->load_dest, g->fniv);
1312 break;
1313
1314 case 0:
1315 if (g->fni8 && check_size_impl(oprsz, 8)) {
1316 expand_3i_i64(dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni8);
1317 } else if (g->fni4 && check_size_impl(oprsz, 4)) {
1318 expand_3i_i32(dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni4);
1319 } else {
1320 assert(g->fno != NULL);
1321 tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, c, g->fno);
53229a77 1322 oprsz = maxsz;
e1227bb6
DH		 1323 }
1324 break;
1325
1326 default:
1327 g_assert_not_reached();
1328 }
53229a77 1329 tcg_swap_vecop_list(hold_list);
e1227bb6
DH		 1330
1331 if (oprsz < maxsz) {
1332 expand_clr(dofs + oprsz, maxsz - oprsz);
1333 }
1334}
1335
db432672
RH		 1336/* Expand a vector four-operand operation. */
1337void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
1338 uint32_t oprsz, uint32_t maxsz, const GVecGen4 *g)
1339{
53229a77
RH		 1340 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
1341 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
adb196cb
RH		 1342 TCGType type;
1343 uint32_t some;
1344
db432672
RH		 1345 check_size_align(oprsz, maxsz, dofs | aofs | bofs | cofs);
1346 check_overlap_4(dofs, aofs, bofs, cofs, maxsz);
1347
adb196cb
RH		 1348 type = 0;
1349 if (g->fniv) {
53229a77 1350 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
adb196cb
RH		 1351 }
1352 switch (type) {
1353 case TCG_TYPE_V256:
1354 /* Recall that ARM SVE allows vector sizes that are not a
1355 * power of 2, but always a multiple of 16. The intent is
1356 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
1357 */
1358 some = QEMU_ALIGN_DOWN(oprsz, 32);
db432672 1359 expand_4_vec(g->vece, dofs, aofs, bofs, cofs, some,
5d6acdd4 1360 32, TCG_TYPE_V256, g->write_aofs, g->fniv);
db432672 1361 if (some == oprsz) {
adb196cb 1362 break;
db432672
RH		 1363 }
1364 dofs += some;
1365 aofs += some;
1366 bofs += some;
1367 cofs += some;
1368 oprsz -= some;
1369 maxsz -= some;
adb196cb
RH		 1370 /* fallthru */
1371 case TCG_TYPE_V128:
db432672 1372 expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz,
5d6acdd4 1373 16, TCG_TYPE_V128, g->write_aofs, g->fniv);
adb196cb
RH		 1374 break;
1375 case TCG_TYPE_V64:
db432672 1376 expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz,
5d6acdd4 1377 8, TCG_TYPE_V64, g->write_aofs, g->fniv);
adb196cb
RH		 1378 break;
1379
1380 case 0:
1381 if (g->fni8 && check_size_impl(oprsz, 8)) {
5d6acdd4
RH		 1382 expand_4_i64(dofs, aofs, bofs, cofs, oprsz,
1383 g->write_aofs, g->fni8);
adb196cb 1384 } else if (g->fni4 && check_size_impl(oprsz, 4)) {
5d6acdd4
RH		 1385 expand_4_i32(dofs, aofs, bofs, cofs, oprsz,
1386 g->write_aofs, g->fni4);
adb196cb
RH		 1387 } else {
1388 assert(g->fno != NULL);
1389 tcg_gen_gvec_4_ool(dofs, aofs, bofs, cofs,
1390 oprsz, maxsz, g->data, g->fno);
53229a77 1391 oprsz = maxsz;
adb196cb
RH		 1392 }
1393 break;
1394
1395 default:
1396 g_assert_not_reached();
db432672 1397 }
53229a77 1398 tcg_swap_vecop_list(hold_list);
db432672 1399
db432672
RH		 1400 if (oprsz < maxsz) {
1401 expand_clr(dofs + oprsz, maxsz - oprsz);
1402 }
1403}
1404
1405/*
1406 * Expand specific vector operations.
1407 */
1408
1409static void vec_mov2(unsigned vece, TCGv_vec a, TCGv_vec b)
1410{
1411 tcg_gen_mov_vec(a, b);
1412}
1413
1414void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs, uint32_t aofs,
1415 uint32_t oprsz, uint32_t maxsz)
1416{
1417 static const GVecGen2 g = {
1418 .fni8 = tcg_gen_mov_i64,
1419 .fniv = vec_mov2,
1420 .fno = gen_helper_gvec_mov,
1421 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
1422 };
1423 if (dofs != aofs) {
1424 tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g);
1425 } else {
1426 check_size_align(oprsz, maxsz, dofs);
1427 if (oprsz < maxsz) {
1428 expand_clr(dofs + oprsz, maxsz - oprsz);
1429 }
1430 }
1431}
1432
1433void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t oprsz,
1434 uint32_t maxsz, TCGv_i32 in)
1435{
1436 check_size_align(oprsz, maxsz, dofs);
1437 tcg_debug_assert(vece <= MO_32);
1438 do_dup(vece, dofs, oprsz, maxsz, in, NULL, 0);
1439}
1440
1441void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t oprsz,
1442 uint32_t maxsz, TCGv_i64 in)
1443{
1444 check_size_align(oprsz, maxsz, dofs);
1445 tcg_debug_assert(vece <= MO_64);
1446 do_dup(vece, dofs, oprsz, maxsz, NULL, in, 0);
1447}
1448
1449void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
1450 uint32_t oprsz, uint32_t maxsz)
1451{
1452 if (vece <= MO_32) {
1453 TCGv_i32 in = tcg_temp_new_i32();
1454 switch (vece) {
1455 case MO_8:
1456 tcg_gen_ld8u_i32(in, cpu_env, aofs);
1457 break;
1458 case MO_16:
1459 tcg_gen_ld16u_i32(in, cpu_env, aofs);
1460 break;
1461 case MO_32:
1462 tcg_gen_ld_i32(in, cpu_env, aofs);
1463 break;
1464 }
1465 tcg_gen_gvec_dup_i32(vece, dofs, oprsz, maxsz, in);
1466 tcg_temp_free_i32(in);
1467 } else if (vece == MO_64) {
1468 TCGv_i64 in = tcg_temp_new_i64();
1469 tcg_gen_ld_i64(in, cpu_env, aofs);
1470 tcg_gen_gvec_dup_i64(MO_64, dofs, oprsz, maxsz, in);
1471 tcg_temp_free_i64(in);
1472 } else {
1473 /* 128-bit duplicate. */
1474 /* ??? Dup to 256-bit vector. */
1475 int i;
1476
1477 tcg_debug_assert(vece == 4);
1478 tcg_debug_assert(oprsz >= 16);
1479 if (TCG_TARGET_HAS_v128) {
1480 TCGv_vec in = tcg_temp_new_vec(TCG_TYPE_V128);
1481
1482 tcg_gen_ld_vec(in, cpu_env, aofs);
1483 for (i = 0; i < oprsz; i += 16) {
1484 tcg_gen_st_vec(in, cpu_env, dofs + i);
1485 }
1486 tcg_temp_free_vec(in);
1487 } else {
1488 TCGv_i64 in0 = tcg_temp_new_i64();
1489 TCGv_i64 in1 = tcg_temp_new_i64();
1490
1491 tcg_gen_ld_i64(in0, cpu_env, aofs);
1492 tcg_gen_ld_i64(in1, cpu_env, aofs + 8);
1493 for (i = 0; i < oprsz; i += 16) {
1494 tcg_gen_st_i64(in0, cpu_env, dofs + i);
1495 tcg_gen_st_i64(in1, cpu_env, dofs + i + 8);
1496 }
1497 tcg_temp_free_i64(in0);
1498 tcg_temp_free_i64(in1);
1499 }
1500 }
1501}
1502
1503void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t oprsz,
1504 uint32_t maxsz, uint64_t x)
1505{
1506 check_size_align(oprsz, maxsz, dofs);
1507 do_dup(MO_64, dofs, oprsz, maxsz, NULL, NULL, x);
1508}
1509
1510void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t oprsz,
1511 uint32_t maxsz, uint32_t x)
1512{
1513 check_size_align(oprsz, maxsz, dofs);
1514 do_dup(MO_32, dofs, oprsz, maxsz, NULL, NULL, x);
1515}
1516
1517void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t oprsz,
1518 uint32_t maxsz, uint16_t x)
1519{
1520 check_size_align(oprsz, maxsz, dofs);
1521 do_dup(MO_16, dofs, oprsz, maxsz, NULL, NULL, x);
1522}
1523
1524void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz,
1525 uint32_t maxsz, uint8_t x)
1526{
1527 check_size_align(oprsz, maxsz, dofs);
1528 do_dup(MO_8, dofs, oprsz, maxsz, NULL, NULL, x);
1529}
1530
1531void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs,
1532 uint32_t oprsz, uint32_t maxsz)
1533{
1534 static const GVecGen2 g = {
1535 .fni8 = tcg_gen_not_i64,
1536 .fniv = tcg_gen_not_vec,
1537 .fno = gen_helper_gvec_not,
1538 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
1539 };
1540 tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g);
1541}
1542
1543/* Perform a vector addition using normal addition and a mask. The mask
1544 should be the sign bit of each lane. This 6-operation form is more
1545 efficient than separate additions when there are 4 or more lanes in
1546 the 64-bit operation. */
1547static void gen_addv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)
1548{
1549 TCGv_i64 t1 = tcg_temp_new_i64();
1550 TCGv_i64 t2 = tcg_temp_new_i64();
1551 TCGv_i64 t3 = tcg_temp_new_i64();
1552
1553 tcg_gen_andc_i64(t1, a, m);
1554 tcg_gen_andc_i64(t2, b, m);
1555 tcg_gen_xor_i64(t3, a, b);
1556 tcg_gen_add_i64(d, t1, t2);
1557 tcg_gen_and_i64(t3, t3, m);
1558 tcg_gen_xor_i64(d, d, t3);
1559
1560 tcg_temp_free_i64(t1);
1561 tcg_temp_free_i64(t2);
1562 tcg_temp_free_i64(t3);
1563}
1564
1565void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
1566{
1567 TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80));
1568 gen_addv_mask(d, a, b, m);
1569 tcg_temp_free_i64(m);
1570}
1571
1572void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
1573{
1574 TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000));
1575 gen_addv_mask(d, a, b, m);
1576 tcg_temp_free_i64(m);
1577}
1578
1579void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
1580{
1581 TCGv_i64 t1 = tcg_temp_new_i64();
1582 TCGv_i64 t2 = tcg_temp_new_i64();
1583
1584 tcg_gen_andi_i64(t1, a, ~0xffffffffull);
1585 tcg_gen_add_i64(t2, a, b);
1586 tcg_gen_add_i64(t1, t1, b);
1587 tcg_gen_deposit_i64(d, t1, t2, 0, 32);
1588
1589 tcg_temp_free_i64(t1);
1590 tcg_temp_free_i64(t2);
1591}
1592
53229a77
RH		 1593static const TCGOpcode vecop_list_add[] = { INDEX_op_add_vec, 0 };
1594
db432672
RH		 1595void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,
1596 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
1597{
1598 static const GVecGen3 g[4] = {
1599 { .fni8 = tcg_gen_vec_add8_i64,
1600 .fniv = tcg_gen_add_vec,
1601 .fno = gen_helper_gvec_add8,
53229a77 1602 .opt_opc = vecop_list_add,
db432672
RH		 1603 .vece = MO_8 },
1604 { .fni8 = tcg_gen_vec_add16_i64,
1605 .fniv = tcg_gen_add_vec,
1606 .fno = gen_helper_gvec_add16,
53229a77 1607 .opt_opc = vecop_list_add,
db432672
RH		 1608 .vece = MO_16 },
1609 { .fni4 = tcg_gen_add_i32,
1610 .fniv = tcg_gen_add_vec,
1611 .fno = gen_helper_gvec_add32,
53229a77 1612 .opt_opc = vecop_list_add,
db432672
RH		 1613 .vece = MO_32 },
1614 { .fni8 = tcg_gen_add_i64,
1615 .fniv = tcg_gen_add_vec,
1616 .fno = gen_helper_gvec_add64,
53229a77 1617 .opt_opc = vecop_list_add,
db432672
RH		 1618 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
1619 .vece = MO_64 },
1620 };
1621
1622 tcg_debug_assert(vece <= MO_64);
1623 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
1624}
1625
22fc3527
RH		 1626void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs,
1627 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
1628{
1629 static const GVecGen2s g[4] = {
1630 { .fni8 = tcg_gen_vec_add8_i64,
1631 .fniv = tcg_gen_add_vec,
1632 .fno = gen_helper_gvec_adds8,
53229a77 1633 .opt_opc = vecop_list_add,
22fc3527
RH		 1634 .vece = MO_8 },
1635 { .fni8 = tcg_gen_vec_add16_i64,
1636 .fniv = tcg_gen_add_vec,
1637 .fno = gen_helper_gvec_adds16,
53229a77 1638 .opt_opc = vecop_list_add,
22fc3527
RH		 1639 .vece = MO_16 },
1640 { .fni4 = tcg_gen_add_i32,
1641 .fniv = tcg_gen_add_vec,
1642 .fno = gen_helper_gvec_adds32,
53229a77 1643 .opt_opc = vecop_list_add,
22fc3527
RH		 1644 .vece = MO_32 },
1645 { .fni8 = tcg_gen_add_i64,
1646 .fniv = tcg_gen_add_vec,
1647 .fno = gen_helper_gvec_adds64,
53229a77 1648 .opt_opc = vecop_list_add,
22fc3527
RH		 1649 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
1650 .vece = MO_64 },
1651 };
1652
1653 tcg_debug_assert(vece <= MO_64);
1654 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]);
1655}
1656
1657void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, uint32_t aofs,
1658 int64_t c, uint32_t oprsz, uint32_t maxsz)
1659{
1660 TCGv_i64 tmp = tcg_const_i64(c);
1661 tcg_gen_gvec_adds(vece, dofs, aofs, tmp, oprsz, maxsz);
1662 tcg_temp_free_i64(tmp);
1663}
1664
53229a77
RH		 1665static const TCGOpcode vecop_list_sub[] = { INDEX_op_sub_vec, 0 };
1666
22fc3527
RH		 1667void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs,
1668 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
1669{
1670 static const GVecGen2s g[4] = {
1671 { .fni8 = tcg_gen_vec_sub8_i64,
1672 .fniv = tcg_gen_sub_vec,
1673 .fno = gen_helper_gvec_subs8,
53229a77 1674 .opt_opc = vecop_list_sub,
22fc3527
RH		 1675 .vece = MO_8 },
1676 { .fni8 = tcg_gen_vec_sub16_i64,
1677 .fniv = tcg_gen_sub_vec,
1678 .fno = gen_helper_gvec_subs16,
53229a77 1679 .opt_opc = vecop_list_sub,
22fc3527
RH		 1680 .vece = MO_16 },
1681 { .fni4 = tcg_gen_sub_i32,
1682 .fniv = tcg_gen_sub_vec,
1683 .fno = gen_helper_gvec_subs32,
53229a77 1684 .opt_opc = vecop_list_sub,
22fc3527
RH		 1685 .vece = MO_32 },
1686 { .fni8 = tcg_gen_sub_i64,
1687 .fniv = tcg_gen_sub_vec,
1688 .fno = gen_helper_gvec_subs64,
53229a77 1689 .opt_opc = vecop_list_sub,
22fc3527
RH		 1690 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
1691 .vece = MO_64 },
1692 };
1693
1694 tcg_debug_assert(vece <= MO_64);
1695 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]);
1696}
1697
db432672
RH		 1698/* Perform a vector subtraction using normal subtraction and a mask.
1699 Compare gen_addv_mask above. */
1700static void gen_subv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)
1701{
1702 TCGv_i64 t1 = tcg_temp_new_i64();
1703 TCGv_i64 t2 = tcg_temp_new_i64();
1704 TCGv_i64 t3 = tcg_temp_new_i64();
1705
1706 tcg_gen_or_i64(t1, a, m);
1707 tcg_gen_andc_i64(t2, b, m);
1708 tcg_gen_eqv_i64(t3, a, b);
1709 tcg_gen_sub_i64(d, t1, t2);
1710 tcg_gen_and_i64(t3, t3, m);
1711 tcg_gen_xor_i64(d, d, t3);
1712
1713 tcg_temp_free_i64(t1);
1714 tcg_temp_free_i64(t2);
1715 tcg_temp_free_i64(t3);
1716}
1717
1718void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
1719{
1720 TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80));
1721 gen_subv_mask(d, a, b, m);
1722 tcg_temp_free_i64(m);
1723}
1724
1725void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
1726{
1727 TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000));
1728 gen_subv_mask(d, a, b, m);
1729 tcg_temp_free_i64(m);
1730}
1731
1732void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
1733{
1734 TCGv_i64 t1 = tcg_temp_new_i64();
1735 TCGv_i64 t2 = tcg_temp_new_i64();
1736
1737 tcg_gen_andi_i64(t1, b, ~0xffffffffull);
1738 tcg_gen_sub_i64(t2, a, b);
1739 tcg_gen_sub_i64(t1, a, t1);
1740 tcg_gen_deposit_i64(d, t1, t2, 0, 32);
1741
1742 tcg_temp_free_i64(t1);
1743 tcg_temp_free_i64(t2);
1744}
1745
1746void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,
1747 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
1748{
1749 static const GVecGen3 g[4] = {
1750 { .fni8 = tcg_gen_vec_sub8_i64,
1751 .fniv = tcg_gen_sub_vec,
1752 .fno = gen_helper_gvec_sub8,
53229a77 1753 .opt_opc = vecop_list_sub,
db432672
RH		 1754 .vece = MO_8 },
1755 { .fni8 = tcg_gen_vec_sub16_i64,
1756 .fniv = tcg_gen_sub_vec,
1757 .fno = gen_helper_gvec_sub16,
53229a77 1758 .opt_opc = vecop_list_sub,
db432672
RH		 1759 .vece = MO_16 },
1760 { .fni4 = tcg_gen_sub_i32,
1761 .fniv = tcg_gen_sub_vec,
1762 .fno = gen_helper_gvec_sub32,
53229a77 1763 .opt_opc = vecop_list_sub,
db432672
RH		 1764 .vece = MO_32 },
1765 { .fni8 = tcg_gen_sub_i64,
1766 .fniv = tcg_gen_sub_vec,
1767 .fno = gen_helper_gvec_sub64,
53229a77 1768 .opt_opc = vecop_list_sub,
db432672
RH		 1769 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
1770 .vece = MO_64 },
1771 };
1772
1773 tcg_debug_assert(vece <= MO_64);
1774 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
1775}
1776
53229a77
RH		 1777static const TCGOpcode vecop_list_mul[] = { INDEX_op_mul_vec, 0 };
1778
3774030a
RH		 1779void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,
1780 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
1781{
1782 static const GVecGen3 g[4] = {
1783 { .fniv = tcg_gen_mul_vec,
1784 .fno = gen_helper_gvec_mul8,
53229a77 1785 .opt_opc = vecop_list_mul,
3774030a
RH		 1786 .vece = MO_8 },
1787 { .fniv = tcg_gen_mul_vec,
1788 .fno = gen_helper_gvec_mul16,
53229a77 1789 .opt_opc = vecop_list_mul,
3774030a
RH		 1790 .vece = MO_16 },
1791 { .fni4 = tcg_gen_mul_i32,
1792 .fniv = tcg_gen_mul_vec,
1793 .fno = gen_helper_gvec_mul32,
53229a77 1794 .opt_opc = vecop_list_mul,
3774030a
RH		 1795 .vece = MO_32 },
1796 { .fni8 = tcg_gen_mul_i64,
1797 .fniv = tcg_gen_mul_vec,
1798 .fno = gen_helper_gvec_mul64,
53229a77 1799 .opt_opc = vecop_list_mul,
3774030a
RH		 1800 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
1801 .vece = MO_64 },
1802 };
1803
1804 tcg_debug_assert(vece <= MO_64);
1805 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
1806}
1807
22fc3527
RH		 1808void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs,
1809 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
1810{
1811 static const GVecGen2s g[4] = {
1812 { .fniv = tcg_gen_mul_vec,
1813 .fno = gen_helper_gvec_muls8,
53229a77 1814 .opt_opc = vecop_list_mul,
22fc3527
RH		 1815 .vece = MO_8 },
1816 { .fniv = tcg_gen_mul_vec,
1817 .fno = gen_helper_gvec_muls16,
53229a77 1818 .opt_opc = vecop_list_mul,
22fc3527
RH		 1819 .vece = MO_16 },
1820 { .fni4 = tcg_gen_mul_i32,
1821 .fniv = tcg_gen_mul_vec,
1822 .fno = gen_helper_gvec_muls32,
53229a77 1823 .opt_opc = vecop_list_mul,
22fc3527
RH		 1824 .vece = MO_32 },
1825 { .fni8 = tcg_gen_mul_i64,
1826 .fniv = tcg_gen_mul_vec,
1827 .fno = gen_helper_gvec_muls64,
53229a77 1828 .opt_opc = vecop_list_mul,
22fc3527
RH		 1829 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
1830 .vece = MO_64 },
1831 };
1832
1833 tcg_debug_assert(vece <= MO_64);
1834 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]);
1835}
1836
1837void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs, uint32_t aofs,
1838 int64_t c, uint32_t oprsz, uint32_t maxsz)
1839{
1840 TCGv_i64 tmp = tcg_const_i64(c);
1841 tcg_gen_gvec_muls(vece, dofs, aofs, tmp, oprsz, maxsz);
1842 tcg_temp_free_i64(tmp);
1843}
1844
f49b12c6
RH		 1845void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,
1846 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
1847{
53229a77 1848 static const TCGOpcode vecop_list[] = { INDEX_op_ssadd_vec, 0 };
f49b12c6 1849 static const GVecGen3 g[4] = {
8afaf050
RH		 1850 { .fniv = tcg_gen_ssadd_vec,
1851 .fno = gen_helper_gvec_ssadd8,
53229a77 1852 .opt_opc = vecop_list,
8afaf050
RH		 1853 .vece = MO_8 },
1854 { .fniv = tcg_gen_ssadd_vec,
1855 .fno = gen_helper_gvec_ssadd16,
53229a77 1856 .opt_opc = vecop_list,
8afaf050
RH		 1857 .vece = MO_16 },
1858 { .fniv = tcg_gen_ssadd_vec,
1859 .fno = gen_helper_gvec_ssadd32,
53229a77 1860 .opt_opc = vecop_list,
8afaf050
RH		 1861 .vece = MO_32 },
1862 { .fniv = tcg_gen_ssadd_vec,
1863 .fno = gen_helper_gvec_ssadd64,
53229a77 1864 .opt_opc = vecop_list,
8afaf050 1865 .vece = MO_64 },
f49b12c6
RH		 1866 };
1867 tcg_debug_assert(vece <= MO_64);
1868 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
1869}
1870
1871void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs,
1872 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
1873{
53229a77 1874 static const TCGOpcode vecop_list[] = { INDEX_op_sssub_vec, 0 };
f49b12c6 1875 static const GVecGen3 g[4] = {
8afaf050
RH		 1876 { .fniv = tcg_gen_sssub_vec,
1877 .fno = gen_helper_gvec_sssub8,
53229a77 1878 .opt_opc = vecop_list,
8afaf050
RH		 1879 .vece = MO_8 },
1880 { .fniv = tcg_gen_sssub_vec,
1881 .fno = gen_helper_gvec_sssub16,
53229a77 1882 .opt_opc = vecop_list,
8afaf050
RH		 1883 .vece = MO_16 },
1884 { .fniv = tcg_gen_sssub_vec,
1885 .fno = gen_helper_gvec_sssub32,
53229a77 1886 .opt_opc = vecop_list,
8afaf050
RH		 1887 .vece = MO_32 },
1888 { .fniv = tcg_gen_sssub_vec,
1889 .fno = gen_helper_gvec_sssub64,
53229a77 1890 .opt_opc = vecop_list,
8afaf050 1891 .vece = MO_64 },
f49b12c6
RH		 1892 };
1893 tcg_debug_assert(vece <= MO_64);
1894 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
1895}
1896
8afaf050 1897static void tcg_gen_usadd_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
f49b12c6
RH		 1898{
1899 TCGv_i32 max = tcg_const_i32(-1);
1900 tcg_gen_add_i32(d, a, b);
1901 tcg_gen_movcond_i32(TCG_COND_LTU, d, d, a, max, d);
1902 tcg_temp_free_i32(max);
1903}
1904
8afaf050 1905static void tcg_gen_usadd_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
f49b12c6
RH		 1906{
1907 TCGv_i64 max = tcg_const_i64(-1);
1908 tcg_gen_add_i64(d, a, b);
1909 tcg_gen_movcond_i64(TCG_COND_LTU, d, d, a, max, d);
1910 tcg_temp_free_i64(max);
1911}
1912
1913void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,
1914 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
1915{
53229a77 1916 static const TCGOpcode vecop_list[] = { INDEX_op_usadd_vec, 0 };
f49b12c6 1917 static const GVecGen3 g[4] = {
8afaf050
RH		 1918 { .fniv = tcg_gen_usadd_vec,
1919 .fno = gen_helper_gvec_usadd8,
53229a77 1920 .opt_opc = vecop_list,
8afaf050
RH		 1921 .vece = MO_8 },
1922 { .fniv = tcg_gen_usadd_vec,
1923 .fno = gen_helper_gvec_usadd16,
53229a77 1924 .opt_opc = vecop_list,
8afaf050
RH		 1925 .vece = MO_16 },
1926 { .fni4 = tcg_gen_usadd_i32,
1927 .fniv = tcg_gen_usadd_vec,
f49b12c6 1928 .fno = gen_helper_gvec_usadd32,
53229a77 1929 .opt_opc = vecop_list,
f49b12c6 1930 .vece = MO_32 },
8afaf050
RH		 1931 { .fni8 = tcg_gen_usadd_i64,
1932 .fniv = tcg_gen_usadd_vec,
f49b12c6 1933 .fno = gen_helper_gvec_usadd64,
53229a77 1934 .opt_opc = vecop_list,
f49b12c6
RH		 1935 .vece = MO_64 }
1936 };
1937 tcg_debug_assert(vece <= MO_64);
1938 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
1939}
1940
8afaf050 1941static void tcg_gen_ussub_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
f49b12c6
RH		 1942{
1943 TCGv_i32 min = tcg_const_i32(0);
1944 tcg_gen_sub_i32(d, a, b);
1945 tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, min, d);
1946 tcg_temp_free_i32(min);
1947}
1948
8afaf050 1949static void tcg_gen_ussub_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
f49b12c6
RH		 1950{
1951 TCGv_i64 min = tcg_const_i64(0);
1952 tcg_gen_sub_i64(d, a, b);
1953 tcg_gen_movcond_i64(TCG_COND_LTU, d, a, b, min, d);
1954 tcg_temp_free_i64(min);
1955}
1956
1957void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,
1958 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
1959{
53229a77 1960 static const TCGOpcode vecop_list[] = { INDEX_op_ussub_vec, 0 };
f49b12c6 1961 static const GVecGen3 g[4] = {
8afaf050
RH		 1962 { .fniv = tcg_gen_ussub_vec,
1963 .fno = gen_helper_gvec_ussub8,
53229a77 1964 .opt_opc = vecop_list,
8afaf050
RH		 1965 .vece = MO_8 },
1966 { .fniv = tcg_gen_ussub_vec,
1967 .fno = gen_helper_gvec_ussub16,
53229a77 1968 .opt_opc = vecop_list,
8afaf050
RH		 1969 .vece = MO_16 },
1970 { .fni4 = tcg_gen_ussub_i32,
1971 .fniv = tcg_gen_ussub_vec,
f49b12c6 1972 .fno = gen_helper_gvec_ussub32,
53229a77 1973 .opt_opc = vecop_list,
f49b12c6 1974 .vece = MO_32 },
8afaf050
RH		 1975 { .fni8 = tcg_gen_ussub_i64,
1976 .fniv = tcg_gen_ussub_vec,
f49b12c6 1977 .fno = gen_helper_gvec_ussub64,
53229a77 1978 .opt_opc = vecop_list,
f49b12c6
RH		 1979 .vece = MO_64 }
1980 };
1981 tcg_debug_assert(vece <= MO_64);
1982 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
dd0a0fcd
RH		 1983}
1984
1985void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs,
1986 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
1987{
53229a77 1988 static const TCGOpcode vecop_list[] = { INDEX_op_smin_vec, 0 };
dd0a0fcd
RH		 1989 static const GVecGen3 g[4] = {
1990 { .fniv = tcg_gen_smin_vec,
1991 .fno = gen_helper_gvec_smin8,
53229a77 1992 .opt_opc = vecop_list,
dd0a0fcd
RH		 1993 .vece = MO_8 },
1994 { .fniv = tcg_gen_smin_vec,
1995 .fno = gen_helper_gvec_smin16,
53229a77 1996 .opt_opc = vecop_list,
dd0a0fcd
RH		 1997 .vece = MO_16 },
1998 { .fni4 = tcg_gen_smin_i32,
1999 .fniv = tcg_gen_smin_vec,
2000 .fno = gen_helper_gvec_smin32,
53229a77 2001 .opt_opc = vecop_list,
dd0a0fcd
RH		 2002 .vece = MO_32 },
2003 { .fni8 = tcg_gen_smin_i64,
2004 .fniv = tcg_gen_smin_vec,
2005 .fno = gen_helper_gvec_smin64,
53229a77 2006 .opt_opc = vecop_list,
dd0a0fcd
RH		 2007 .vece = MO_64 }
2008 };
2009 tcg_debug_assert(vece <= MO_64);
2010 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
2011}
2012
2013void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs,
2014 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2015{
53229a77 2016 static const TCGOpcode vecop_list[] = { INDEX_op_umin_vec, 0 };
dd0a0fcd
RH		 2017 static const GVecGen3 g[4] = {
2018 { .fniv = tcg_gen_umin_vec,
2019 .fno = gen_helper_gvec_umin8,
53229a77 2020 .opt_opc = vecop_list,
dd0a0fcd
RH		 2021 .vece = MO_8 },
2022 { .fniv = tcg_gen_umin_vec,
2023 .fno = gen_helper_gvec_umin16,
53229a77 2024 .opt_opc = vecop_list,
dd0a0fcd
RH		 2025 .vece = MO_16 },
2026 { .fni4 = tcg_gen_umin_i32,
2027 .fniv = tcg_gen_umin_vec,
2028 .fno = gen_helper_gvec_umin32,
53229a77 2029 .opt_opc = vecop_list,
dd0a0fcd
RH		 2030 .vece = MO_32 },
2031 { .fni8 = tcg_gen_umin_i64,
2032 .fniv = tcg_gen_umin_vec,
2033 .fno = gen_helper_gvec_umin64,
53229a77 2034 .opt_opc = vecop_list,
dd0a0fcd
RH		 2035 .vece = MO_64 }
2036 };
2037 tcg_debug_assert(vece <= MO_64);
2038 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
2039}
2040
2041void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs,
2042 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2043{
53229a77 2044 static const TCGOpcode vecop_list[] = { INDEX_op_smax_vec, 0 };
dd0a0fcd
RH		 2045 static const GVecGen3 g[4] = {
2046 { .fniv = tcg_gen_smax_vec,
2047 .fno = gen_helper_gvec_smax8,
53229a77 2048 .opt_opc = vecop_list,
dd0a0fcd
RH		 2049 .vece = MO_8 },
2050 { .fniv = tcg_gen_smax_vec,
2051 .fno = gen_helper_gvec_smax16,
53229a77 2052 .opt_opc = vecop_list,
dd0a0fcd
RH		 2053 .vece = MO_16 },
2054 { .fni4 = tcg_gen_smax_i32,
2055 .fniv = tcg_gen_smax_vec,
2056 .fno = gen_helper_gvec_smax32,
53229a77 2057 .opt_opc = vecop_list,
dd0a0fcd
RH		 2058 .vece = MO_32 },
2059 { .fni8 = tcg_gen_smax_i64,
2060 .fniv = tcg_gen_smax_vec,
2061 .fno = gen_helper_gvec_smax64,
53229a77 2062 .opt_opc = vecop_list,
dd0a0fcd
RH		 2063 .vece = MO_64 }
2064 };
2065 tcg_debug_assert(vece <= MO_64);
2066 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
2067}
2068
2069void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs,
2070 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2071{
53229a77 2072 static const TCGOpcode vecop_list[] = { INDEX_op_umax_vec, 0 };
dd0a0fcd
RH		 2073 static const GVecGen3 g[4] = {
2074 { .fniv = tcg_gen_umax_vec,
2075 .fno = gen_helper_gvec_umax8,
53229a77 2076 .opt_opc = vecop_list,
dd0a0fcd
RH		 2077 .vece = MO_8 },
2078 { .fniv = tcg_gen_umax_vec,
2079 .fno = gen_helper_gvec_umax16,
53229a77 2080 .opt_opc = vecop_list,
dd0a0fcd
RH		 2081 .vece = MO_16 },
2082 { .fni4 = tcg_gen_umax_i32,
2083 .fniv = tcg_gen_umax_vec,
2084 .fno = gen_helper_gvec_umax32,
53229a77 2085 .opt_opc = vecop_list,
dd0a0fcd
RH		 2086 .vece = MO_32 },
2087 { .fni8 = tcg_gen_umax_i64,
2088 .fniv = tcg_gen_umax_vec,
2089 .fno = gen_helper_gvec_umax64,
53229a77 2090 .opt_opc = vecop_list,
dd0a0fcd
RH		 2091 .vece = MO_64 }
2092 };
2093 tcg_debug_assert(vece <= MO_64);
2094 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
f49b12c6
RH		 2095}
2096
db432672
RH		 2097/* Perform a vector negation using normal negation and a mask.
2098 Compare gen_subv_mask above. */
2099static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m)
2100{
2101 TCGv_i64 t2 = tcg_temp_new_i64();
2102 TCGv_i64 t3 = tcg_temp_new_i64();
2103
2104 tcg_gen_andc_i64(t3, m, b);
2105 tcg_gen_andc_i64(t2, b, m);
2106 tcg_gen_sub_i64(d, m, t2);
2107 tcg_gen_xor_i64(d, d, t3);
2108
2109 tcg_temp_free_i64(t2);
2110 tcg_temp_free_i64(t3);
2111}
2112
2113void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 b)
2114{
2115 TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80));
2116 gen_negv_mask(d, b, m);
2117 tcg_temp_free_i64(m);
2118}
2119
2120void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 b)
2121{
2122 TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000));
2123 gen_negv_mask(d, b, m);
2124 tcg_temp_free_i64(m);
2125}
2126
2127void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 b)
2128{
2129 TCGv_i64 t1 = tcg_temp_new_i64();
2130 TCGv_i64 t2 = tcg_temp_new_i64();
2131
2132 tcg_gen_andi_i64(t1, b, ~0xffffffffull);
2133 tcg_gen_neg_i64(t2, b);
2134 tcg_gen_neg_i64(t1, t1);
2135 tcg_gen_deposit_i64(d, t1, t2, 0, 32);
2136
2137 tcg_temp_free_i64(t1);
2138 tcg_temp_free_i64(t2);
2139}
2140
2141void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs,
2142 uint32_t oprsz, uint32_t maxsz)
2143{
53229a77 2144 static const TCGOpcode vecop_list[] = { INDEX_op_neg_vec, 0 };
db432672
RH		 2145 static const GVecGen2 g[4] = {
2146 { .fni8 = tcg_gen_vec_neg8_i64,
2147 .fniv = tcg_gen_neg_vec,
2148 .fno = gen_helper_gvec_neg8,
53229a77 2149 .opt_opc = vecop_list,
db432672
RH		 2150 .vece = MO_8 },
2151 { .fni8 = tcg_gen_vec_neg16_i64,
2152 .fniv = tcg_gen_neg_vec,
2153 .fno = gen_helper_gvec_neg16,
53229a77 2154 .opt_opc = vecop_list,
db432672
RH		 2155 .vece = MO_16 },
2156 { .fni4 = tcg_gen_neg_i32,
2157 .fniv = tcg_gen_neg_vec,
2158 .fno = gen_helper_gvec_neg32,
53229a77 2159 .opt_opc = vecop_list,
db432672
RH		 2160 .vece = MO_32 },
2161 { .fni8 = tcg_gen_neg_i64,
2162 .fniv = tcg_gen_neg_vec,
2163 .fno = gen_helper_gvec_neg64,
53229a77 2164 .opt_opc = vecop_list,
db432672
RH		 2165 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2166 .vece = MO_64 },
2167 };
2168
2169 tcg_debug_assert(vece <= MO_64);
2170 tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g[vece]);
2171}
2172
2173void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs,
2174 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2175{
2176 static const GVecGen3 g = {
2177 .fni8 = tcg_gen_and_i64,
2178 .fniv = tcg_gen_and_vec,
2179 .fno = gen_helper_gvec_and,
db432672
RH		 2180 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2181 };
9a9eda78
RH		 2182
2183 if (aofs == bofs) {
2184 tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
2185 } else {
2186 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
2187 }
db432672
RH		 2188}
2189
2190void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs,
2191 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2192{
2193 static const GVecGen3 g = {
2194 .fni8 = tcg_gen_or_i64,
2195 .fniv = tcg_gen_or_vec,
2196 .fno = gen_helper_gvec_or,
db432672
RH		 2197 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2198 };
9a9eda78
RH		 2199
2200 if (aofs == bofs) {
2201 tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
2202 } else {
2203 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
2204 }
db432672
RH		 2205}
2206
2207void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs,
2208 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2209{
2210 static const GVecGen3 g = {
2211 .fni8 = tcg_gen_xor_i64,
2212 .fniv = tcg_gen_xor_vec,
2213 .fno = gen_helper_gvec_xor,
db432672
RH		 2214 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2215 };
9a9eda78
RH		 2216
2217 if (aofs == bofs) {
2218 tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0);
2219 } else {
2220 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
2221 }
db432672
RH		 2222}
2223
2224void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs,
2225 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2226{
2227 static const GVecGen3 g = {
2228 .fni8 = tcg_gen_andc_i64,
2229 .fniv = tcg_gen_andc_vec,
2230 .fno = gen_helper_gvec_andc,
db432672
RH		 2231 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2232 };
9a9eda78
RH		 2233
2234 if (aofs == bofs) {
2235 tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0);
2236 } else {
2237 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
2238 }
db432672
RH		 2239}
2240
2241void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
2242 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2243{
2244 static const GVecGen3 g = {
2245 .fni8 = tcg_gen_orc_i64,
2246 .fniv = tcg_gen_orc_vec,
2247 .fno = gen_helper_gvec_orc,
db432672
RH		 2248 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2249 };
9a9eda78
RH		 2250
2251 if (aofs == bofs) {
2252 tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, -1);
2253 } else {
f550805d
RH		 2254 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
2255 }
2256}
2257
2258void tcg_gen_gvec_nand(unsigned vece, uint32_t dofs, uint32_t aofs,
2259 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2260{
2261 static const GVecGen3 g = {
2262 .fni8 = tcg_gen_nand_i64,
2263 .fniv = tcg_gen_nand_vec,
2264 .fno = gen_helper_gvec_nand,
2265 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2266 };
2267
2268 if (aofs == bofs) {
2269 tcg_gen_gvec_not(vece, dofs, aofs, oprsz, maxsz);
2270 } else {
2271 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
2272 }
2273}
2274
2275void tcg_gen_gvec_nor(unsigned vece, uint32_t dofs, uint32_t aofs,
2276 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2277{
2278 static const GVecGen3 g = {
2279 .fni8 = tcg_gen_nor_i64,
2280 .fniv = tcg_gen_nor_vec,
2281 .fno = gen_helper_gvec_nor,
2282 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2283 };
2284
2285 if (aofs == bofs) {
2286 tcg_gen_gvec_not(vece, dofs, aofs, oprsz, maxsz);
2287 } else {
2288 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
2289 }
2290}
2291
2292void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, uint32_t aofs,
2293 uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
2294{
2295 static const GVecGen3 g = {
2296 .fni8 = tcg_gen_eqv_i64,
2297 .fniv = tcg_gen_eqv_vec,
2298 .fno = gen_helper_gvec_eqv,
2299 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2300 };
2301
2302 if (aofs == bofs) {
2303 tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, -1);
2304 } else {
9a9eda78
RH		 2305 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
2306 }
db432672 2307}
d0ec9796 2308
22fc3527
RH		 2309static const GVecGen2s gop_ands = {
2310 .fni8 = tcg_gen_and_i64,
2311 .fniv = tcg_gen_and_vec,
2312 .fno = gen_helper_gvec_ands,
22fc3527
RH		 2313 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2314 .vece = MO_64
2315};
2316
2317void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs,
2318 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
2319{
2320 TCGv_i64 tmp = tcg_temp_new_i64();
2321 gen_dup_i64(vece, tmp, c);
2322 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ands);
2323 tcg_temp_free_i64(tmp);
2324}
2325
2326void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs,
2327 int64_t c, uint32_t oprsz, uint32_t maxsz)
2328{
2329 TCGv_i64 tmp = tcg_const_i64(dup_const(vece, c));
2330 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ands);
2331 tcg_temp_free_i64(tmp);
2332}
2333
2334static const GVecGen2s gop_xors = {
2335 .fni8 = tcg_gen_xor_i64,
2336 .fniv = tcg_gen_xor_vec,
2337 .fno = gen_helper_gvec_xors,
22fc3527
RH		 2338 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2339 .vece = MO_64
2340};
2341
2342void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs,
2343 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
2344{
2345 TCGv_i64 tmp = tcg_temp_new_i64();
2346 gen_dup_i64(vece, tmp, c);
2347 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_xors);
2348 tcg_temp_free_i64(tmp);
2349}
2350
2351void tcg_gen_gvec_xori(unsigned vece, uint32_t dofs, uint32_t aofs,
2352 int64_t c, uint32_t oprsz, uint32_t maxsz)
2353{
2354 TCGv_i64 tmp = tcg_const_i64(dup_const(vece, c));
2355 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_xors);
2356 tcg_temp_free_i64(tmp);
2357}
2358
2359static const GVecGen2s gop_ors = {
2360 .fni8 = tcg_gen_or_i64,
2361 .fniv = tcg_gen_or_vec,
2362 .fno = gen_helper_gvec_ors,
22fc3527
RH		 2363 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2364 .vece = MO_64
2365};
2366
2367void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs,
2368 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
2369{
2370 TCGv_i64 tmp = tcg_temp_new_i64();
2371 gen_dup_i64(vece, tmp, c);
2372 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ors);
2373 tcg_temp_free_i64(tmp);
2374}
2375
2376void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs,
2377 int64_t c, uint32_t oprsz, uint32_t maxsz)
2378{
2379 TCGv_i64 tmp = tcg_const_i64(dup_const(vece, c));
2380 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ors);
2381 tcg_temp_free_i64(tmp);
2382}
2383
d0ec9796
RH		 2384void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
2385{
2386 uint64_t mask = dup_const(MO_8, 0xff << c);
2387 tcg_gen_shli_i64(d, a, c);
2388 tcg_gen_andi_i64(d, d, mask);
2389}
2390
2391void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
2392{
2393 uint64_t mask = dup_const(MO_16, 0xffff << c);
2394 tcg_gen_shli_i64(d, a, c);
2395 tcg_gen_andi_i64(d, d, mask);
2396}
2397
2398void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,
2399 int64_t shift, uint32_t oprsz, uint32_t maxsz)
2400{
53229a77 2401 static const TCGOpcode vecop_list[] = { INDEX_op_shli_vec, 0 };
d0ec9796
RH		 2402 static const GVecGen2i g[4] = {
2403 { .fni8 = tcg_gen_vec_shl8i_i64,
2404 .fniv = tcg_gen_shli_vec,
2405 .fno = gen_helper_gvec_shl8i,
53229a77 2406 .opt_opc = vecop_list,
d0ec9796
RH		 2407 .vece = MO_8 },
2408 { .fni8 = tcg_gen_vec_shl16i_i64,
2409 .fniv = tcg_gen_shli_vec,
2410 .fno = gen_helper_gvec_shl16i,
53229a77 2411 .opt_opc = vecop_list,
d0ec9796
RH		 2412 .vece = MO_16 },
2413 { .fni4 = tcg_gen_shli_i32,
2414 .fniv = tcg_gen_shli_vec,
2415 .fno = gen_helper_gvec_shl32i,
53229a77 2416 .opt_opc = vecop_list,
d0ec9796
RH		 2417 .vece = MO_32 },
2418 { .fni8 = tcg_gen_shli_i64,
2419 .fniv = tcg_gen_shli_vec,
2420 .fno = gen_helper_gvec_shl64i,
53229a77 2421 .opt_opc = vecop_list,
d0ec9796
RH		 2422 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2423 .vece = MO_64 },
2424 };
2425
2426 tcg_debug_assert(vece <= MO_64);
2427 tcg_debug_assert(shift >= 0 && shift < (8 << vece));
2428 if (shift == 0) {
2429 tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
2430 } else {
2431 tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]);
2432 }
2433}
2434
2435void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
2436{
2437 uint64_t mask = dup_const(MO_8, 0xff >> c);
2438 tcg_gen_shri_i64(d, a, c);
2439 tcg_gen_andi_i64(d, d, mask);
2440}
2441
2442void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
2443{
2444 uint64_t mask = dup_const(MO_16, 0xffff >> c);
2445 tcg_gen_shri_i64(d, a, c);
2446 tcg_gen_andi_i64(d, d, mask);
2447}
2448
2449void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
2450 int64_t shift, uint32_t oprsz, uint32_t maxsz)
2451{
53229a77 2452 static const TCGOpcode vecop_list[] = { INDEX_op_shri_vec, 0 };
d0ec9796
RH		 2453 static const GVecGen2i g[4] = {
2454 { .fni8 = tcg_gen_vec_shr8i_i64,
2455 .fniv = tcg_gen_shri_vec,
2456 .fno = gen_helper_gvec_shr8i,
53229a77 2457 .opt_opc = vecop_list,
d0ec9796
RH		 2458 .vece = MO_8 },
2459 { .fni8 = tcg_gen_vec_shr16i_i64,
2460 .fniv = tcg_gen_shri_vec,
2461 .fno = gen_helper_gvec_shr16i,
53229a77 2462 .opt_opc = vecop_list,
d0ec9796
RH		 2463 .vece = MO_16 },
2464 { .fni4 = tcg_gen_shri_i32,
2465 .fniv = tcg_gen_shri_vec,
2466 .fno = gen_helper_gvec_shr32i,
53229a77 2467 .opt_opc = vecop_list,
d0ec9796
RH		 2468 .vece = MO_32 },
2469 { .fni8 = tcg_gen_shri_i64,
2470 .fniv = tcg_gen_shri_vec,
2471 .fno = gen_helper_gvec_shr64i,
53229a77 2472 .opt_opc = vecop_list,
d0ec9796
RH		 2473 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2474 .vece = MO_64 },
2475 };
2476
2477 tcg_debug_assert(vece <= MO_64);
2478 tcg_debug_assert(shift >= 0 && shift < (8 << vece));
2479 if (shift == 0) {
2480 tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
2481 } else {
2482 tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]);
2483 }
2484}
2485
2486void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
2487{
2488 uint64_t s_mask = dup_const(MO_8, 0x80 >> c);
2489 uint64_t c_mask = dup_const(MO_8, 0xff >> c);
2490 TCGv_i64 s = tcg_temp_new_i64();
2491
2492 tcg_gen_shri_i64(d, a, c);
2493 tcg_gen_andi_i64(s, d, s_mask); /* isolate (shifted) sign bit */
2494 tcg_gen_muli_i64(s, s, (2 << c) - 2); /* replicate isolated signs */
2495 tcg_gen_andi_i64(d, d, c_mask); /* clear out bits above sign */
2496 tcg_gen_or_i64(d, d, s); /* include sign extension */
2497 tcg_temp_free_i64(s);
2498}
2499
2500void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
2501{
2502 uint64_t s_mask = dup_const(MO_16, 0x8000 >> c);
2503 uint64_t c_mask = dup_const(MO_16, 0xffff >> c);
2504 TCGv_i64 s = tcg_temp_new_i64();
2505
2506 tcg_gen_shri_i64(d, a, c);
2507 tcg_gen_andi_i64(s, d, s_mask); /* isolate (shifted) sign bit */
2508 tcg_gen_andi_i64(d, d, c_mask); /* clear out bits above sign */
2509 tcg_gen_muli_i64(s, s, (2 << c) - 2); /* replicate isolated signs */
2510 tcg_gen_or_i64(d, d, s); /* include sign extension */
2511 tcg_temp_free_i64(s);
2512}
2513
2514void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
2515 int64_t shift, uint32_t oprsz, uint32_t maxsz)
2516{
53229a77 2517 static const TCGOpcode vecop_list[] = { INDEX_op_sari_vec, 0 };
d0ec9796
RH		 2518 static const GVecGen2i g[4] = {
2519 { .fni8 = tcg_gen_vec_sar8i_i64,
2520 .fniv = tcg_gen_sari_vec,
2521 .fno = gen_helper_gvec_sar8i,
53229a77 2522 .opt_opc = vecop_list,
d0ec9796
RH		 2523 .vece = MO_8 },
2524 { .fni8 = tcg_gen_vec_sar16i_i64,
2525 .fniv = tcg_gen_sari_vec,
2526 .fno = gen_helper_gvec_sar16i,
53229a77 2527 .opt_opc = vecop_list,
d0ec9796
RH		 2528 .vece = MO_16 },
2529 { .fni4 = tcg_gen_sari_i32,
2530 .fniv = tcg_gen_sari_vec,
2531 .fno = gen_helper_gvec_sar32i,
53229a77 2532 .opt_opc = vecop_list,
d0ec9796
RH		 2533 .vece = MO_32 },
2534 { .fni8 = tcg_gen_sari_i64,
2535 .fniv = tcg_gen_sari_vec,
2536 .fno = gen_helper_gvec_sar64i,
53229a77 2537 .opt_opc = vecop_list,
d0ec9796
RH		 2538 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2539 .vece = MO_64 },
2540 };
2541
2542 tcg_debug_assert(vece <= MO_64);
2543 tcg_debug_assert(shift >= 0 && shift < (8 << vece));
2544 if (shift == 0) {
2545 tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
2546 } else {
2547 tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]);
2548 }
2549}
212be173
RH		 2550
2551/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
2552static void expand_cmp_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
2553 uint32_t oprsz, TCGCond cond)
2554{
2555 TCGv_i32 t0 = tcg_temp_new_i32();
2556 TCGv_i32 t1 = tcg_temp_new_i32();
2557 uint32_t i;
2558
2559 for (i = 0; i < oprsz; i += 4) {
2560 tcg_gen_ld_i32(t0, cpu_env, aofs + i);
2561 tcg_gen_ld_i32(t1, cpu_env, bofs + i);
2562 tcg_gen_setcond_i32(cond, t0, t0, t1);
2563 tcg_gen_neg_i32(t0, t0);
2564 tcg_gen_st_i32(t0, cpu_env, dofs + i);
2565 }
2566 tcg_temp_free_i32(t1);
2567 tcg_temp_free_i32(t0);
2568}
2569
2570static void expand_cmp_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
2571 uint32_t oprsz, TCGCond cond)
2572{
2573 TCGv_i64 t0 = tcg_temp_new_i64();
2574 TCGv_i64 t1 = tcg_temp_new_i64();
2575 uint32_t i;
2576
2577 for (i = 0; i < oprsz; i += 8) {
2578 tcg_gen_ld_i64(t0, cpu_env, aofs + i);
2579 tcg_gen_ld_i64(t1, cpu_env, bofs + i);
2580 tcg_gen_setcond_i64(cond, t0, t0, t1);
2581 tcg_gen_neg_i64(t0, t0);
2582 tcg_gen_st_i64(t0, cpu_env, dofs + i);
2583 }
2584 tcg_temp_free_i64(t1);
2585 tcg_temp_free_i64(t0);
2586}
2587
2588static void expand_cmp_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
2589 uint32_t bofs, uint32_t oprsz, uint32_t tysz,
2590 TCGType type, TCGCond cond)
2591{
2592 TCGv_vec t0 = tcg_temp_new_vec(type);
2593 TCGv_vec t1 = tcg_temp_new_vec(type);
2594 uint32_t i;
2595
2596 for (i = 0; i < oprsz; i += tysz) {
2597 tcg_gen_ld_vec(t0, cpu_env, aofs + i);
2598 tcg_gen_ld_vec(t1, cpu_env, bofs + i);
2599 tcg_gen_cmp_vec(cond, vece, t0, t0, t1);
2600 tcg_gen_st_vec(t0, cpu_env, dofs + i);
2601 }
2602 tcg_temp_free_vec(t1);
2603 tcg_temp_free_vec(t0);
2604}
2605
2606void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
2607 uint32_t aofs, uint32_t bofs,
2608 uint32_t oprsz, uint32_t maxsz)
2609{
53229a77 2610 static const TCGOpcode cmp_list[] = { INDEX_op_cmp_vec, 0 };
212be173
RH		 2611 static gen_helper_gvec_3 * const eq_fn[4] = {
2612 gen_helper_gvec_eq8, gen_helper_gvec_eq16,
2613 gen_helper_gvec_eq32, gen_helper_gvec_eq64
2614 };
2615 static gen_helper_gvec_3 * const ne_fn[4] = {
2616 gen_helper_gvec_ne8, gen_helper_gvec_ne16,
2617 gen_helper_gvec_ne32, gen_helper_gvec_ne64
2618 };
2619 static gen_helper_gvec_3 * const lt_fn[4] = {
2620 gen_helper_gvec_lt8, gen_helper_gvec_lt16,
2621 gen_helper_gvec_lt32, gen_helper_gvec_lt64
2622 };
2623 static gen_helper_gvec_3 * const le_fn[4] = {
2624 gen_helper_gvec_le8, gen_helper_gvec_le16,
2625 gen_helper_gvec_le32, gen_helper_gvec_le64
2626 };
2627 static gen_helper_gvec_3 * const ltu_fn[4] = {
2628 gen_helper_gvec_ltu8, gen_helper_gvec_ltu16,
2629 gen_helper_gvec_ltu32, gen_helper_gvec_ltu64
2630 };
2631 static gen_helper_gvec_3 * const leu_fn[4] = {
2632 gen_helper_gvec_leu8, gen_helper_gvec_leu16,
2633 gen_helper_gvec_leu32, gen_helper_gvec_leu64
2634 };
2635 static gen_helper_gvec_3 * const * const fns[16] = {
2636 [TCG_COND_EQ] = eq_fn,
2637 [TCG_COND_NE] = ne_fn,
2638 [TCG_COND_LT] = lt_fn,
2639 [TCG_COND_LE] = le_fn,
2640 [TCG_COND_LTU] = ltu_fn,
2641 [TCG_COND_LEU] = leu_fn,
2642 };
53229a77
RH		 2643
2644 const TCGOpcode *hold_list;
adb196cb
RH		 2645 TCGType type;
2646 uint32_t some;
212be173
RH		 2647
2648 check_size_align(oprsz, maxsz, dofs | aofs | bofs);
2649 check_overlap_3(dofs, aofs, bofs, maxsz);
2650
2651 if (cond == TCG_COND_NEVER || cond == TCG_COND_ALWAYS) {
2652 do_dup(MO_8, dofs, oprsz, maxsz,
2653 NULL, NULL, -(cond == TCG_COND_ALWAYS));
2654 return;
2655 }
2656
53229a77
RH		 2657 /*
2658 * Implement inline with a vector type, if possible.
adb196cb
RH		 2659 * Prefer integer when 64-bit host and 64-bit comparison.
2660 */
53229a77
RH		 2661 hold_list = tcg_swap_vecop_list(cmp_list);
2662 type = choose_vector_type(cmp_list, vece, oprsz,
adb196cb
RH		 2663 TCG_TARGET_REG_BITS == 64 && vece == MO_64);
2664 switch (type) {
2665 case TCG_TYPE_V256:
2666 /* Recall that ARM SVE allows vector sizes that are not a
2667 * power of 2, but always a multiple of 16. The intent is
2668 * that e.g. size == 80 would be expanded with 2x32 + 1x16.
2669 */
2670 some = QEMU_ALIGN_DOWN(oprsz, 32);
212be173
RH		 2671 expand_cmp_vec(vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256, cond);
2672 if (some == oprsz) {
adb196cb 2673 break;
212be173
RH		 2674 }
2675 dofs += some;
2676 aofs += some;
2677 bofs += some;
2678 oprsz -= some;
2679 maxsz -= some;
adb196cb
RH		 2680 /* fallthru */
2681 case TCG_TYPE_V128:
212be173 2682 expand_cmp_vec(vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128, cond);
adb196cb
RH		 2683 break;
2684 case TCG_TYPE_V64:
212be173 2685 expand_cmp_vec(vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64, cond);
adb196cb
RH		 2686 break;
2687
2688 case 0:
2689 if (vece == MO_64 && check_size_impl(oprsz, 8)) {
2690 expand_cmp_i64(dofs, aofs, bofs, oprsz, cond);
2691 } else if (vece == MO_32 && check_size_impl(oprsz, 4)) {
2692 expand_cmp_i32(dofs, aofs, bofs, oprsz, cond);
2693 } else {
2694 gen_helper_gvec_3 * const *fn = fns[cond];
2695
2696 if (fn == NULL) {
2697 uint32_t tmp;
2698 tmp = aofs, aofs = bofs, bofs = tmp;
2699 cond = tcg_swap_cond(cond);
2700 fn = fns[cond];
2701 assert(fn != NULL);
2702 }
2703 tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, 0, fn[vece]);
53229a77 2704 oprsz = maxsz;
212be173 2705 }
adb196cb
RH		 2706 break;
2707
2708 default:
2709 g_assert_not_reached();
212be173 2710 }
53229a77 2711 tcg_swap_vecop_list(hold_list);
212be173 2712
212be173
RH		 2713 if (oprsz < maxsz) {
2714 expand_clr(dofs + oprsz, maxsz - oprsz);
2715 }
2716}
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