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db432672
RH		 1/*
2 * Generic vector operation expansion
3 *
4 * Copyright (c) 2018 Linaro
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
fb0343d5 9 * version 2.1 of the License, or (at your option) any later version.
db432672
RH		 10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20/*
21 * "Generic" vectors. All operands are given as offsets from ENV,
22 * and therefore cannot also be allocated via tcg_global_mem_new_*.
23 * OPRSZ is the byte size of the vector upon which the operation is performed.
24 * MAXSZ is the byte size of the full vector; bytes beyond OPSZ are cleared.
25 *
26 * All sizes must be 8 or any multiple of 16.
27 * When OPRSZ is 8, the alignment may be 8, otherwise must be 16.
28 * Operands may completely, but not partially, overlap.
29 */
30
31/* Expand a call to a gvec-style helper, with pointers to two vector
32 operands, and a descriptor (see tcg-gvec-desc.h). */
33typedef void gen_helper_gvec_2(TCGv_ptr, TCGv_ptr, TCGv_i32);
34void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs,
35 uint32_t oprsz, uint32_t maxsz, int32_t data,
36 gen_helper_gvec_2 *fn);
37
22fc3527
RH		 38/* Similarly, passing an extra data value. */
39typedef void gen_helper_gvec_2i(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32);
40void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c,
41 uint32_t oprsz, uint32_t maxsz, int32_t data,
42 gen_helper_gvec_2i *fn);
43
db432672
RH		 44/* Similarly, passing an extra pointer (e.g. env or float_status). */
45typedef void gen_helper_gvec_2_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
46void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs,
47 TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
48 int32_t data, gen_helper_gvec_2_ptr *fn);
49
50/* Similarly, with three vector operands. */
51typedef void gen_helper_gvec_3(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
52void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
53 uint32_t oprsz, uint32_t maxsz, int32_t data,
54 gen_helper_gvec_3 *fn);
55
56/* Similarly, with four vector operands. */
57typedef void gen_helper_gvec_4(TCGv_ptr, TCGv_ptr, TCGv_ptr,
58 TCGv_ptr, TCGv_i32);
59void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
60 uint32_t cofs, uint32_t oprsz, uint32_t maxsz,
61 int32_t data, gen_helper_gvec_4 *fn);
62
63/* Similarly, with five vector operands. */
64typedef void gen_helper_gvec_5(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
65 TCGv_ptr, TCGv_i32);
66void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
67 uint32_t cofs, uint32_t xofs, uint32_t oprsz,
68 uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn);
69
70typedef void gen_helper_gvec_3_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr,
71 TCGv_ptr, TCGv_i32);
72void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
73 TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
74 int32_t data, gen_helper_gvec_3_ptr *fn);
75
76typedef void gen_helper_gvec_4_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr,
77 TCGv_ptr, TCGv_ptr, TCGv_i32);
78void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
79 uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz,
80 uint32_t maxsz, int32_t data,
81 gen_helper_gvec_4_ptr *fn);
82
83/* Expand a gvec operation. Either inline or out-of-line depending on
84 the actual vector size and the operations supported by the host. */
85typedef struct {
86 /* Expand inline as a 64-bit or 32-bit integer.
87 Only one of these will be non-NULL. */
88 void (*fni8)(TCGv_i64, TCGv_i64);
89 void (*fni4)(TCGv_i32, TCGv_i32);
90 /* Expand inline with a host vector type. */
91 void (*fniv)(unsigned, TCGv_vec, TCGv_vec);
92 /* Expand out-of-line helper w/descriptor. */
93 gen_helper_gvec_2 *fno;
53229a77
RH		 94 /* The optional opcodes, if any, utilized by .fniv. */
95 const TCGOpcode *opt_opc;
db432672
RH		 96 /* The data argument to the out-of-line helper. */
97 int32_t data;
98 /* The vector element size, if applicable. */
99 uint8_t vece;
100 /* Prefer i64 to v64. */
101 bool prefer_i64;
102} GVecGen2;
103
d0ec9796
RH		 104typedef struct {
105 /* Expand inline as a 64-bit or 32-bit integer.
106 Only one of these will be non-NULL. */
107 void (*fni8)(TCGv_i64, TCGv_i64, int64_t);
108 void (*fni4)(TCGv_i32, TCGv_i32, int32_t);
109 /* Expand inline with a host vector type. */
110 void (*fniv)(unsigned, TCGv_vec, TCGv_vec, int64_t);
22fc3527 111 /* Expand out-of-line helper w/descriptor, data in descriptor. */
d0ec9796 112 gen_helper_gvec_2 *fno;
22fc3527
RH		 113 /* Expand out-of-line helper w/descriptor, data as argument. */
114 gen_helper_gvec_2i *fnoi;
53229a77
RH		 115 /* The optional opcodes, if any, utilized by .fniv. */
116 const TCGOpcode *opt_opc;
d0ec9796
RH		 117 /* The vector element size, if applicable. */
118 uint8_t vece;
119 /* Prefer i64 to v64. */
120 bool prefer_i64;
121 /* Load dest as a 3rd source operand. */
122 bool load_dest;
123} GVecGen2i;
124
22fc3527
RH		 125typedef struct {
126 /* Expand inline as a 64-bit or 32-bit integer.
127 Only one of these will be non-NULL. */
128 void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64);
129 void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32);
130 /* Expand inline with a host vector type. */
131 void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec);
132 /* Expand out-of-line helper w/descriptor. */
133 gen_helper_gvec_2i *fno;
53229a77
RH		 134 /* The optional opcodes, if any, utilized by .fniv. */
135 const TCGOpcode *opt_opc;
22fc3527
RH		 136 /* The data argument to the out-of-line helper. */
137 uint32_t data;
138 /* The vector element size, if applicable. */
139 uint8_t vece;
140 /* Prefer i64 to v64. */
141 bool prefer_i64;
142 /* Load scalar as 1st source operand. */
143 bool scalar_first;
144} GVecGen2s;
145
db432672
RH		 146typedef struct {
147 /* Expand inline as a 64-bit or 32-bit integer.
148 Only one of these will be non-NULL. */
149 void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64);
150 void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32);
151 /* Expand inline with a host vector type. */
152 void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec);
153 /* Expand out-of-line helper w/descriptor. */
154 gen_helper_gvec_3 *fno;
53229a77
RH		 155 /* The optional opcodes, if any, utilized by .fniv. */
156 const TCGOpcode *opt_opc;
db432672
RH		 157 /* The data argument to the out-of-line helper. */
158 int32_t data;
159 /* The vector element size, if applicable. */
160 uint8_t vece;
161 /* Prefer i64 to v64. */
162 bool prefer_i64;
163 /* Load dest as a 3rd source operand. */
164 bool load_dest;
165} GVecGen3;
166
e1227bb6
DH		 167typedef struct {
168 /*
169 * Expand inline as a 64-bit or 32-bit integer. Only one of these will be
170 * non-NULL.
171 */
172 void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, int64_t);
173 void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, int32_t);
174 /* Expand inline with a host vector type. */
175 void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, int64_t);
176 /* Expand out-of-line helper w/descriptor, data in descriptor. */
177 gen_helper_gvec_3 *fno;
53229a77
RH		 178 /* The optional opcodes, if any, utilized by .fniv. */
179 const TCGOpcode *opt_opc;
e1227bb6
DH		 180 /* The vector element size, if applicable. */
181 uint8_t vece;
182 /* Prefer i64 to v64. */
183 bool prefer_i64;
184 /* Load dest as a 3rd source operand. */
185 bool load_dest;
186} GVecGen3i;
187
db432672
RH		 188typedef struct {
189 /* Expand inline as a 64-bit or 32-bit integer.
190 Only one of these will be non-NULL. */
191 void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64);
192 void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
193 /* Expand inline with a host vector type. */
194 void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec);
195 /* Expand out-of-line helper w/descriptor. */
196 gen_helper_gvec_4 *fno;
53229a77
RH		 197 /* The optional opcodes, if any, utilized by .fniv. */
198 const TCGOpcode *opt_opc;
db432672
RH		 199 /* The data argument to the out-of-line helper. */
200 int32_t data;
201 /* The vector element size, if applicable. */
202 uint8_t vece;
203 /* Prefer i64 to v64. */
204 bool prefer_i64;
5d6acdd4
RH		 205 /* Write aofs as a 2nd dest operand. */
206 bool write_aofs;
db432672
RH		 207} GVecGen4;
208
209void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
210 uint32_t oprsz, uint32_t maxsz, const GVecGen2 *);
d0ec9796
RH		 211void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
212 uint32_t maxsz, int64_t c, const GVecGen2i *);
22fc3527
RH		 213void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
214 uint32_t maxsz, TCGv_i64 c, const GVecGen2s *);
db432672
RH		 215void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
216 uint32_t oprsz, uint32_t maxsz, const GVecGen3 *);
e1227bb6
DH		 217void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs,
218 uint32_t oprsz, uint32_t maxsz, int64_t c,
219 const GVecGen3i *);
db432672
RH		 220void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
221 uint32_t oprsz, uint32_t maxsz, const GVecGen4 *);
222
223/* Expand a specific vector operation. */
224
225void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs, uint32_t aofs,
226 uint32_t oprsz, uint32_t maxsz);
227void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs,
228 uint32_t oprsz, uint32_t maxsz);
229void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs,
230 uint32_t oprsz, uint32_t maxsz);
231
232void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,
233 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
234void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,
235 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
3774030a
RH		 236void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,
237 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
f49b12c6 238
22fc3527
RH		 239void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, uint32_t aofs,
240 int64_t c, uint32_t oprsz, uint32_t maxsz);
241void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs, uint32_t aofs,
242 int64_t c, uint32_t oprsz, uint32_t maxsz);
243
244void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs,
245 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz);
246void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs,
247 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz);
248void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs,
249 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz);
250
f49b12c6
RH		 251/* Saturated arithmetic. */
252void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,
253 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
254void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs,
255 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
256void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,
257 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
258void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,
259 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
db432672 260
dd0a0fcd
RH		 261/* Min/max. */
262void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs,
263 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
264void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs,
265 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
266void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs,
267 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
268void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs,
269 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
270
db432672
RH		 271void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs,
272 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
273void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs,
274 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
275void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs,
276 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
277void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs,
278 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
279void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
280 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
f550805d
RH		 281void tcg_gen_gvec_nand(unsigned vece, uint32_t dofs, uint32_t aofs,
282 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
283void tcg_gen_gvec_nor(unsigned vece, uint32_t dofs, uint32_t aofs,
284 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
285void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, uint32_t aofs,
286 uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
db432672 287
22fc3527
RH		 288void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs,
289 int64_t c, uint32_t oprsz, uint32_t maxsz);
290void tcg_gen_gvec_xori(unsigned vece, uint32_t dofs, uint32_t aofs,
291 int64_t c, uint32_t oprsz, uint32_t maxsz);
292void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs,
293 int64_t c, uint32_t oprsz, uint32_t maxsz);
294
295void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs,
296 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz);
297void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs,
298 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz);
299void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs,
300 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz);
301
db432672
RH		 302void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
303 uint32_t s, uint32_t m);
304void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,
305 uint32_t m, TCGv_i32);
306void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s,
307 uint32_t m, TCGv_i64);
308
309void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t s, uint32_t m, uint8_t x);
310void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t s, uint32_t m, uint16_t x);
311void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t s, uint32_t m, uint32_t x);
312void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t s, uint32_t m, uint64_t x);
313
d0ec9796
RH		 314void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,
315 int64_t shift, uint32_t oprsz, uint32_t maxsz);
316void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
317 int64_t shift, uint32_t oprsz, uint32_t maxsz);
318void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
319 int64_t shift, uint32_t oprsz, uint32_t maxsz);
320
212be173
RH		 321void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
322 uint32_t aofs, uint32_t bofs,
323 uint32_t oprsz, uint32_t maxsz);
324
db432672
RH		 325/*
326 * 64-bit vector operations. Use these when the register has been allocated
327 * with tcg_global_mem_new_i64, and so we cannot also address it via pointer.
328 * OPRSZ = MAXSZ = 8.
329 */
330
331void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 a);
332void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 a);
333void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 a);
334
335void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
336void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
337void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
338
339void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
340void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
341void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
d0ec9796
RH		 342
343void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
344void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
345void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
346void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
347void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
348void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
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