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[mirror_qemu.git] / tcg / tcg-op.h
CommitLineData
c896fe29
FB		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
951c6300 24
a7ce790a
PM		 25#ifndef TCG_TCG_OP_H
26#define TCG_TCG_OP_H
27
c896fe29 28#include "tcg.h"
944eea96 29#include "exec/helper-proto.h"
c017230d
RH		 30#include "exec/helper-gen.h"
31
951c6300 32/* Basic output routines. Not for general consumption. */
c896fe29 33
b7e8b17a
RH		 34void tcg_gen_op1(TCGOpcode, TCGArg);
35void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg);
36void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg);
37void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
38void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
39void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
951c6300 40
d2fd745f
RH		 41void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg);
42void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg);
43void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg);
44
951c6300 45static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
c896fe29 46{
ae8b75dc 47 tcg_gen_op1(opc, tcgv_i32_arg(a1));
a7812ae4
PB		 48}
49
951c6300 50static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
a7812ae4 51{
ae8b75dc 52 tcg_gen_op1(opc, tcgv_i64_arg(a1));
c896fe29
FB		 53}
54
951c6300 55static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
c896fe29 56{
b7e8b17a 57 tcg_gen_op1(opc, a1);
c896fe29
FB		 58}
59
951c6300 60static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
a7812ae4 61{
ae8b75dc 62 tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2));
a7812ae4
PB		 63}
64
951c6300 65static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
a7812ae4 66{
ae8b75dc 67 tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2));
a7812ae4
PB		 68}
69
951c6300 70static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
c896fe29 71{
ae8b75dc 72 tcg_gen_op2(opc, tcgv_i32_arg(a1), a2);
c896fe29
FB		 73}
74
951c6300 75static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
c896fe29 76{
ae8b75dc 77 tcg_gen_op2(opc, tcgv_i64_arg(a1), a2);
ac56dd48
PB		 78}
79
951c6300 80static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
bcb0126f 81{
b7e8b17a 82 tcg_gen_op2(opc, a1, a2);
bcb0126f
PB		 83}
84
951c6300
RH		 85static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
86 TCGv_i32 a2, TCGv_i32 a3)
a7812ae4 87{
ae8b75dc 88 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3));
a7812ae4
PB		 89}
90
951c6300
RH		 91static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
92 TCGv_i64 a2, TCGv_i64 a3)
a7812ae4 93{
ae8b75dc 94 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3));
a7812ae4
PB		 95}
96
951c6300
RH		 97static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
98 TCGv_i32 a2, TCGArg a3)
ac56dd48 99{
ae8b75dc 100 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3);
ac56dd48
PB		 101}
102
951c6300
RH		 103static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
104 TCGv_i64 a2, TCGArg a3)
ac56dd48 105{
ae8b75dc 106 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3);
ac56dd48
PB		 107}
108
a9751609
RH		 109static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
110 TCGv_ptr base, TCGArg offset)
a7812ae4 111{
ae8b75dc 112 tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset);
a7812ae4
PB		 113}
114
a9751609
RH		 115static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
116 TCGv_ptr base, TCGArg offset)
a7812ae4 117{
ae8b75dc 118 tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset);
a7812ae4
PB		 119}
120
951c6300
RH		 121static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
122 TCGv_i32 a3, TCGv_i32 a4)
a7812ae4 123{
ae8b75dc
RH		 124 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
125 tcgv_i32_arg(a3), tcgv_i32_arg(a4));
a7812ae4
PB		 126}
127
951c6300
RH		 128static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
129 TCGv_i64 a3, TCGv_i64 a4)
a7812ae4 130{
ae8b75dc
RH		 131 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
132 tcgv_i64_arg(a3), tcgv_i64_arg(a4));
a7812ae4
PB		 133}
134
951c6300
RH		 135static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
136 TCGv_i32 a3, TCGArg a4)
a7812ae4 137{
ae8b75dc
RH		 138 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
139 tcgv_i32_arg(a3), a4);
a7812ae4
PB		 140}
141
951c6300
RH		 142static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
143 TCGv_i64 a3, TCGArg a4)
ac56dd48 144{
ae8b75dc
RH		 145 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
146 tcgv_i64_arg(a3), a4);
ac56dd48
PB		 147}
148
951c6300
RH		 149static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
150 TCGArg a3, TCGArg a4)
ac56dd48 151{
ae8b75dc 152 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4);
c896fe29
FB		 153}
154
951c6300
RH		 155static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
156 TCGArg a3, TCGArg a4)
c896fe29 157{
ae8b75dc 158 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4);
ac56dd48
PB		 159}
160
951c6300
RH		 161static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
162 TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5)
a7812ae4 163{
ae8b75dc
RH		 164 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
165 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5));
a7812ae4
PB		 166}
167
951c6300
RH		 168static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
169 TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5)
a7812ae4 170{
ae8b75dc
RH		 171 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
172 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5));
a7812ae4
PB		 173}
174
951c6300
RH		 175static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
176 TCGv_i32 a3, TCGv_i32 a4, TCGArg a5)
ac56dd48 177{
ae8b75dc
RH		 178 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
179 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5);
ac56dd48
PB		 180}
181
951c6300
RH		 182static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
183 TCGv_i64 a3, TCGv_i64 a4, TCGArg a5)
ac56dd48 184{
ae8b75dc
RH		 185 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
186 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5);
c896fe29
FB		 187}
188
951c6300
RH		 189static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
190 TCGv_i32 a3, TCGArg a4, TCGArg a5)
b7767f0f 191{
ae8b75dc
RH		 192 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
193 tcgv_i32_arg(a3), a4, a5);
b7767f0f
RH		 194}
195
951c6300
RH		 196static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
197 TCGv_i64 a3, TCGArg a4, TCGArg a5)
b7767f0f 198{
ae8b75dc
RH		 199 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
200 tcgv_i64_arg(a3), a4, a5);
b7767f0f
RH		 201}
202
951c6300
RH		 203static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
204 TCGv_i32 a3, TCGv_i32 a4,
205 TCGv_i32 a5, TCGv_i32 a6)
a7812ae4 206{
ae8b75dc
RH		 207 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
208 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5),
209 tcgv_i32_arg(a6));
a7812ae4
PB		 210}
211
951c6300
RH		 212static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
213 TCGv_i64 a3, TCGv_i64 a4,
214 TCGv_i64 a5, TCGv_i64 a6)
c896fe29 215{
ae8b75dc
RH		 216 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
217 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5),
218 tcgv_i64_arg(a6));
ac56dd48
PB		 219}
220
951c6300
RH		 221static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
222 TCGv_i32 a3, TCGv_i32 a4,
223 TCGv_i32 a5, TCGArg a6)
be210acb 224{
ae8b75dc
RH		 225 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
226 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6);
be210acb
RH		 227}
228
951c6300
RH		 229static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
230 TCGv_i64 a3, TCGv_i64 a4,
231 TCGv_i64 a5, TCGArg a6)
be210acb 232{
ae8b75dc
RH		 233 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
234 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6);
be210acb
RH		 235}
236
951c6300
RH		 237static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
238 TCGv_i32 a3, TCGv_i32 a4,
239 TCGArg a5, TCGArg a6)
ac56dd48 240{
ae8b75dc
RH		 241 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
242 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6);
a7812ae4
PB		 243}
244
951c6300
RH		 245static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
246 TCGv_i64 a3, TCGv_i64 a4,
247 TCGArg a5, TCGArg a6)
a7812ae4 248{
ae8b75dc
RH		 249 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
250 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6);
c896fe29
FB		 251}
252
f713d6ad 253
951c6300
RH		 254/* Generic ops. */
255
42a268c2 256static inline void gen_set_label(TCGLabel *l)
c896fe29 257{
bef16ab4 258 l->present = 1;
b7e8b17a 259 tcg_gen_op1(INDEX_op_set_label, label_arg(l));
c896fe29
FB		 260}
261
42a268c2 262static inline void tcg_gen_br(TCGLabel *l)
fb50d413 263{
d88a117e 264 l->refs++;
b7e8b17a 265 tcg_gen_op1(INDEX_op_br, label_arg(l));
951c6300
RH		 266}
267
f65e19bc
PK		 268void tcg_gen_mb(TCGBar);
269
951c6300
RH		 270/* Helper calls. */
271
272/* 32 bit ops */
273
274void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
275void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2);
276void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
474b2e8f 277void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
951c6300
RH		 278void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
279void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
474b2e8f
RH		 280void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
281void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
282void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
951c6300
RH		 283void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
284void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
285void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
286void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
287void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
288void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
289void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
290void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
291void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
292void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
0e28d006
RH		 293void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
294void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
295void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
296void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
086920c2 297void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg);
a768e4e9 298void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2);
951c6300
RH		 299void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
300void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
301void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
302void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
303void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
304 unsigned int ofs, unsigned int len);
07cc68d5
RH		 305void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg,
306 unsigned int ofs, unsigned int len);
7ec8bab3
RH		 307void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
308 unsigned int ofs, unsigned int len);
309void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
310 unsigned int ofs, unsigned int len);
42a268c2
RH		 311void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
312void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
951c6300
RH		 313void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
314 TCGv_i32 arg1, TCGv_i32 arg2);
315void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
316 TCGv_i32 arg1, int32_t arg2);
317void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
318 TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2);
319void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
320 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
321void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
322 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
323void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
324void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
5087abfb 325void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
951c6300
RH		 326void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg);
327void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg);
328void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg);
329void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg);
330void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg);
331void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg);
b87fb8cd
RH		 332void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
333void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
334void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
335void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
951c6300
RH		 336
337static inline void tcg_gen_discard_i32(TCGv_i32 arg)
338{
339 tcg_gen_op1_i32(INDEX_op_discard, arg);
fb50d413
BS		 340}
341
a7812ae4 342static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 343{
11f4e8f8 344 if (ret != arg) {
a7812ae4 345 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
951c6300 346 }
c896fe29
FB		 347}
348
a7812ae4 349static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
c896fe29 350{
a7812ae4 351 tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
c896fe29
FB		 352}
353
951c6300
RH		 354static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2,
355 tcg_target_long offset)
c896fe29 356{
a7812ae4 357 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
c896fe29
FB		 358}
359
951c6300
RH		 360static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2,
361 tcg_target_long offset)
c896fe29 362{
a7812ae4 363 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
c896fe29
FB		 364}
365
951c6300
RH		 366static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2,
367 tcg_target_long offset)
c896fe29 368{
a7812ae4 369 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
c896fe29
FB		 370}
371
951c6300
RH		 372static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2,
373 tcg_target_long offset)
c896fe29 374{
a7812ae4 375 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
c896fe29
FB		 376}
377
951c6300
RH		 378static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2,
379 tcg_target_long offset)
c896fe29 380{
a7812ae4 381 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
c896fe29
FB		 382}
383
951c6300
RH		 384static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2,
385 tcg_target_long offset)
c896fe29 386{
a7812ae4 387 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
c896fe29
FB		 388}
389
951c6300
RH		 390static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2,
391 tcg_target_long offset)
c896fe29 392{
a7812ae4 393 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
c896fe29
FB		 394}
395
951c6300
RH		 396static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2,
397 tcg_target_long offset)
c896fe29 398{
a7812ae4 399 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
c896fe29
FB		 400}
401
a7812ae4 402static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 403{
a7812ae4 404 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
c896fe29
FB		 405}
406
a7812ae4 407static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 408{
a7812ae4 409 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
c896fe29
FB		 410}
411
a7812ae4 412static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 413{
951c6300 414 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
c896fe29
FB		 415}
416
a7812ae4 417static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 418{
951c6300 419 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
c896fe29
FB		 420}
421
a7812ae4 422static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 423{
951c6300 424 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
c896fe29
FB		 425}
426
a7812ae4 427static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 428{
a7812ae4 429 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
c896fe29
FB		 430}
431
a7812ae4 432static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 433{
a7812ae4 434 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
c896fe29
FB		 435}
436
a7812ae4 437static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 438{
a7812ae4 439 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
c896fe29
FB		 440}
441
a7812ae4 442static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 443{
a7812ae4 444 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
c896fe29
FB		 445}
446
951c6300 447static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 448{
951c6300
RH		 449 if (TCG_TARGET_HAS_neg_i32) {
450 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
25c4d9cc 451 } else {
951c6300 452 tcg_gen_subfi_i32(ret, 0, arg);
25c4d9cc 453 }
31d66551
AJ		 454}
455
951c6300 456static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
31d66551 457{
951c6300
RH		 458 if (TCG_TARGET_HAS_not_i32) {
459 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
25c4d9cc 460 } else {
951c6300 461 tcg_gen_xori_i32(ret, arg, -1);
25c4d9cc 462 }
31d66551
AJ		 463}
464
951c6300
RH		 465/* 64 bit ops */
466
467void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
468void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2);
469void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474b2e8f 470void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
951c6300
RH		 471void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
472void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474b2e8f
RH		 473void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
475void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
951c6300
RH		 476void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
477void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
478void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
479void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
480void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
481void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
482void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
483void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
484void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
485void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
0e28d006
RH		 486void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
487void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
488void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
489void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
086920c2 490void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg);
a768e4e9 491void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2);
951c6300
RH		 492void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
493void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
494void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
495void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
496void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
497 unsigned int ofs, unsigned int len);
07cc68d5
RH		 498void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg,
499 unsigned int ofs, unsigned int len);
7ec8bab3
RH		 500void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
501 unsigned int ofs, unsigned int len);
502void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
503 unsigned int ofs, unsigned int len);
42a268c2
RH		 504void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
505void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
951c6300
RH		 506void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
507 TCGv_i64 arg1, TCGv_i64 arg2);
508void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
509 TCGv_i64 arg1, int64_t arg2);
510void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
511 TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2);
512void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
513 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
514void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
515 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
516void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
517void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
5087abfb 518void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
951c6300
RH		 519void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg);
520void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg);
521void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg);
522void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg);
523void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg);
524void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg);
525void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg);
526void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg);
527void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg);
528void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg);
b87fb8cd
RH		 529void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
530void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
531void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
532void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
c896fe29 533
951c6300
RH		 534#if TCG_TARGET_REG_BITS == 64
535static inline void tcg_gen_discard_i64(TCGv_i64 arg)
536{
537 tcg_gen_op1_i64(INDEX_op_discard, arg);
538}
c896fe29 539
a7812ae4 540static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 541{
11f4e8f8 542 if (ret != arg) {
951c6300 543 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
4d07272d 544 }
c896fe29
FB		 545}
546
a7812ae4 547static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
c896fe29 548{
951c6300 549 tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
c896fe29
FB		 550}
551
a7812ae4
PB		 552static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
553 tcg_target_long offset)
c896fe29 554{
951c6300 555 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
c896fe29
FB		 556}
557
a7812ae4
PB		 558static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
559 tcg_target_long offset)
c896fe29 560{
951c6300 561 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
c896fe29
FB		 562}
563
a7812ae4
PB		 564static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
565 tcg_target_long offset)
c896fe29 566{
951c6300 567 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
c896fe29
FB		 568}
569
a7812ae4
PB		 570static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
571 tcg_target_long offset)
c896fe29 572{
951c6300 573 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
c896fe29
FB		 574}
575
a7812ae4
PB		 576static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
577 tcg_target_long offset)
c896fe29 578{
951c6300 579 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
c896fe29
FB		 580}
581
a7812ae4
PB		 582static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
583 tcg_target_long offset)
c896fe29 584{
951c6300 585 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
c896fe29
FB		 586}
587
a7812ae4
PB		 588static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
589 tcg_target_long offset)
c896fe29 590{
951c6300 591 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
c896fe29
FB		 592}
593
a7812ae4
PB		 594static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
595 tcg_target_long offset)
c896fe29 596{
951c6300 597 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
c896fe29
FB		 598}
599
a7812ae4
PB		 600static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
601 tcg_target_long offset)
c896fe29 602{
951c6300 603 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
c896fe29
FB		 604}
605
a7812ae4
PB		 606static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
607 tcg_target_long offset)
c896fe29 608{
951c6300 609 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
c896fe29
FB		 610}
611
a7812ae4
PB		 612static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
613 tcg_target_long offset)
c896fe29 614{
951c6300 615 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
c896fe29
FB		 616}
617
a7812ae4 618static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 619{
951c6300 620 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
c896fe29
FB		 621}
622
a7812ae4 623static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 624{
951c6300 625 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
c896fe29
FB		 626}
627
a7812ae4 628static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 629{
951c6300 630 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
c896fe29
FB		 631}
632
a7812ae4 633static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 634{
951c6300 635 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
c896fe29
FB		 636}
637
a7812ae4 638static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 639{
951c6300 640 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
c896fe29
FB		 641}
642
a7812ae4 643static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 644{
951c6300 645 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
c896fe29
FB		 646}
647
a7812ae4 648static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 649{
951c6300 650 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
c896fe29
FB		 651}
652
a7812ae4 653static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 654{
951c6300 655 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
5105c556
AJ		 656}
657
a7812ae4 658static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 659{
951c6300 660 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
c896fe29 661}
951c6300
RH		 662#else /* TCG_TARGET_REG_BITS == 32 */
663static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
664 tcg_target_long offset)
c896fe29 665{
951c6300 666 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 667}
668
951c6300
RH		 669static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
670 tcg_target_long offset)
c896fe29 671{
951c6300 672 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 673}
674
951c6300
RH		 675static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
676 tcg_target_long offset)
c896fe29 677{
951c6300 678 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 679}
680
951c6300 681static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 682{
951c6300
RH		 683 tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
684 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
c896fe29
FB		 685}
686
951c6300 687static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 688{
951c6300
RH		 689 tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
690 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
691}
692
693void tcg_gen_discard_i64(TCGv_i64 arg);
694void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg);
695void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg);
696void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
697void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
698void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
699void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
700void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
701void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
702void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
703void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
704void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
705void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
706void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
707void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
708void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
709void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
710void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
711#endif /* TCG_TARGET_REG_BITS */
c896fe29 712
951c6300 713static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 714{
951c6300
RH		 715 if (TCG_TARGET_HAS_neg_i64) {
716 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
717 } else {
718 tcg_gen_subfi_i64(ret, 0, arg);
719 }
c896fe29
FB		 720}
721
951c6300 722/* Size changing operations. */
c896fe29 723
951c6300
RH		 724void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
725void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
726void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high);
609ad705
RH		 727void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
728void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
951c6300
RH		 729void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg);
730void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg);
c896fe29 731
951c6300 732static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi)
c896fe29 733{
951c6300 734 tcg_gen_deposit_i64(ret, lo, hi, 32, 32);
c896fe29
FB		 735}
736
951c6300 737/* QEMU specific operations. */
c896fe29 738
951c6300
RH		 739#ifndef TARGET_LONG_BITS
740#error must include QEMU headers
741#endif
c896fe29 742
9aef40ed
RH		 743#if TARGET_INSN_START_WORDS == 1
744# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
745static inline void tcg_gen_insn_start(target_ulong pc)
c896fe29 746{
b7e8b17a 747 tcg_gen_op1(INDEX_op_insn_start, pc);
9aef40ed
RH		 748}
749# else
750static inline void tcg_gen_insn_start(target_ulong pc)
751{
b7e8b17a 752 tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32));
9aef40ed
RH		 753}
754# endif
755#elif TARGET_INSN_START_WORDS == 2
756# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
757static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
758{
b7e8b17a 759 tcg_gen_op2(INDEX_op_insn_start, pc, a1);
9aef40ed
RH		 760}
761# else
762static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
763{
b7e8b17a 764 tcg_gen_op4(INDEX_op_insn_start,
9aef40ed
RH		 765 (uint32_t)pc, (uint32_t)(pc >> 32),
766 (uint32_t)a1, (uint32_t)(a1 >> 32));
767}
768# endif
769#elif TARGET_INSN_START_WORDS == 3
770# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
771static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
772 target_ulong a2)
773{
b7e8b17a 774 tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2);
9aef40ed
RH		 775}
776# else
777static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
778 target_ulong a2)
779{
b7e8b17a 780 tcg_gen_op6(INDEX_op_insn_start,
9aef40ed
RH		 781 (uint32_t)pc, (uint32_t)(pc >> 32),
782 (uint32_t)a1, (uint32_t)(a1 >> 32),
783 (uint32_t)a2, (uint32_t)(a2 >> 32));
784}
785# endif
951c6300 786#else
9aef40ed 787# error "Unhandled number of operands to insn_start"
951c6300 788#endif
c896fe29 789
07ea28b4
RH		 790/**
791 * tcg_gen_exit_tb() - output exit_tb TCG operation
792 * @tb: The TranslationBlock from which we are exiting
793 * @idx: Direct jump slot index, or exit request
794 *
795 * See tcg/README for more info about this TCG operation.
796 * See also tcg.h and the block comment above TB_EXIT_MASK.
797 *
798 * For a normal exit from the TB, back to the main loop, @tb should
799 * be NULL and @idx should be 0. Otherwise, @tb should be valid and
800 * @idx should be one of the TB_EXIT_ values.
801 */
802void tcg_gen_exit_tb(TranslationBlock *tb, unsigned idx);
c896fe29 803
5b053a4a
SF		 804/**
805 * tcg_gen_goto_tb() - output goto_tb TCG operation
806 * @idx: Direct jump slot index (0 or 1)
807 *
808 * See tcg/README for more info about this TCG operation.
809 *
90aa39a1
SF		 810 * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within
811 * the pages this TB resides in because we don't take care of direct jumps when
812 * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a
813 * static address translation, so the destination address is always valid, TBs
814 * are always invalidated properly, and direct jumps are reset when mapping
815 * changes.
5b053a4a 816 */
951c6300 817void tcg_gen_goto_tb(unsigned idx);
c896fe29 818
cedbcb01 819/**
7f11636d 820 * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid
cedbcb01
EC		 821 * @addr: Guest address of the target TB
822 *
823 * If the TB is not valid, jump to the epilogue.
824 *
825 * This operation is optional. If the TCG backend does not implement goto_ptr,
826 * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument.
827 */
7f11636d 828void tcg_gen_lookup_and_goto_ptr(void);
cedbcb01 829
a7812ae4 830#if TARGET_LONG_BITS == 32
a7812ae4
PB		 831#define tcg_temp_new() tcg_temp_new_i32()
832#define tcg_global_reg_new tcg_global_reg_new_i32
833#define tcg_global_mem_new tcg_global_mem_new_i32
df9247b2 834#define tcg_temp_local_new() tcg_temp_local_new_i32()
a7812ae4 835#define tcg_temp_free tcg_temp_free_i32
f713d6ad
RH		 836#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
837#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
a7812ae4 838#else
a7812ae4
PB		 839#define tcg_temp_new() tcg_temp_new_i64()
840#define tcg_global_reg_new tcg_global_reg_new_i64
841#define tcg_global_mem_new tcg_global_mem_new_i64
df9247b2 842#define tcg_temp_local_new() tcg_temp_local_new_i64()
a7812ae4 843#define tcg_temp_free tcg_temp_free_i64
f713d6ad
RH		 844#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
845#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
a7812ae4
PB		 846#endif
847
f713d6ad
RH		 848void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
849void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
850void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
851void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
c896fe29 852
ac56dd48 853static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
c896fe29 854{
f713d6ad 855 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB);
c896fe29
FB		 856}
857
ac56dd48 858static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
c896fe29 859{
f713d6ad 860 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB);
c896fe29
FB		 861}
862
ac56dd48 863static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
c896fe29 864{
f713d6ad 865 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW);
c896fe29
FB		 866}
867
ac56dd48 868static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
c896fe29 869{
f713d6ad 870 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW);
c896fe29
FB		 871}
872
ac56dd48 873static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
c896fe29 874{
f713d6ad 875 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL);
c896fe29
FB		 876}
877
ac56dd48 878static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
c896fe29 879{
f713d6ad 880 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL);
c896fe29
FB		 881}
882
a7812ae4 883static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
c896fe29 884{
f713d6ad 885 tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEQ);
c896fe29
FB		 886}
887
ac56dd48 888static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
c896fe29 889{
f713d6ad 890 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB);
c896fe29
FB		 891}
892
ac56dd48 893static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
c896fe29 894{
f713d6ad 895 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW);
c896fe29
FB		 896}
897
ac56dd48 898static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
c896fe29 899{
f713d6ad 900 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL);
c896fe29
FB		 901}
902
a7812ae4 903static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
c896fe29 904{
f713d6ad 905 tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ);
c896fe29
FB		 906}
907
c482cb11
RH		 908void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
909 TCGArg, TCGMemOp);
910void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
911 TCGArg, TCGMemOp);
912
913void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
914void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
5507c2bf 915
c482cb11
RH		 916void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
917void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
918void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
919void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
920void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
921void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
922void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
923void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
5507c2bf
RH		 924void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
925void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
926void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
927void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
928void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
929void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
930void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
931void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
932
c482cb11
RH		 933void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
934void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
935void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
936void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
937void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
938void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
939void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
940void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
5507c2bf
RH		 941void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
942void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
943void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
944void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
945void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
946void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
947void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
948void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
c482cb11 949
d2fd745f
RH		 950void tcg_gen_mov_vec(TCGv_vec, TCGv_vec);
951void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32);
952void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64);
953void tcg_gen_dup8i_vec(TCGv_vec, uint32_t);
954void tcg_gen_dup16i_vec(TCGv_vec, uint32_t);
955void tcg_gen_dup32i_vec(TCGv_vec, uint32_t);
956void tcg_gen_dup64i_vec(TCGv_vec, uint64_t);
db432672 957void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t);
d2fd745f
RH		 958void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
959void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
3774030a 960void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
d2fd745f
RH		 961void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
962void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
963void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
964void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
965void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
f550805d
RH		 966void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
967void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
968void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
d2fd745f
RH		 969void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
970void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
8afaf050
RH		 971void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
972void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
973void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
974void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
dd0a0fcd
RH		 975void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
976void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
977void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
978void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
d2fd745f 979
d0ec9796
RH		 980void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
981void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
982void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
983
212be173
RH		 984void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
985 TCGv_vec a, TCGv_vec b);
986
d2fd745f
RH		 987void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
988void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
989void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
990
f8422f52 991#if TARGET_LONG_BITS == 64
f8422f52
BS		 992#define tcg_gen_movi_tl tcg_gen_movi_i64
993#define tcg_gen_mov_tl tcg_gen_mov_i64
994#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
995#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
996#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
997#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
998#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
999#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
1000#define tcg_gen_ld_tl tcg_gen_ld_i64
1001#define tcg_gen_st8_tl tcg_gen_st8_i64
1002#define tcg_gen_st16_tl tcg_gen_st16_i64
1003#define tcg_gen_st32_tl tcg_gen_st32_i64
1004#define tcg_gen_st_tl tcg_gen_st_i64
1005#define tcg_gen_add_tl tcg_gen_add_i64
1006#define tcg_gen_addi_tl tcg_gen_addi_i64
1007#define tcg_gen_sub_tl tcg_gen_sub_i64
390efc54 1008#define tcg_gen_neg_tl tcg_gen_neg_i64
10460c8a 1009#define tcg_gen_subfi_tl tcg_gen_subfi_i64
f8422f52
BS		 1010#define tcg_gen_subi_tl tcg_gen_subi_i64
1011#define tcg_gen_and_tl tcg_gen_and_i64
1012#define tcg_gen_andi_tl tcg_gen_andi_i64
1013#define tcg_gen_or_tl tcg_gen_or_i64
1014#define tcg_gen_ori_tl tcg_gen_ori_i64
1015#define tcg_gen_xor_tl tcg_gen_xor_i64
1016#define tcg_gen_xori_tl tcg_gen_xori_i64
0b6ce4cf 1017#define tcg_gen_not_tl tcg_gen_not_i64
f8422f52
BS		 1018#define tcg_gen_shl_tl tcg_gen_shl_i64
1019#define tcg_gen_shli_tl tcg_gen_shli_i64
1020#define tcg_gen_shr_tl tcg_gen_shr_i64
1021#define tcg_gen_shri_tl tcg_gen_shri_i64
1022#define tcg_gen_sar_tl tcg_gen_sar_i64
1023#define tcg_gen_sari_tl tcg_gen_sari_i64
0cf767d6 1024#define tcg_gen_brcond_tl tcg_gen_brcond_i64
cb63669a 1025#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
be210acb 1026#define tcg_gen_setcond_tl tcg_gen_setcond_i64
add1e7ea 1027#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
f730fd27
TS		 1028#define tcg_gen_mul_tl tcg_gen_mul_i64
1029#define tcg_gen_muli_tl tcg_gen_muli_i64
ab36421e
AJ		 1030#define tcg_gen_div_tl tcg_gen_div_i64
1031#define tcg_gen_rem_tl tcg_gen_rem_i64
864951af
AJ		 1032#define tcg_gen_divu_tl tcg_gen_divu_i64
1033#define tcg_gen_remu_tl tcg_gen_remu_i64
a768e4b2 1034#define tcg_gen_discard_tl tcg_gen_discard_i64
ecc7b3aa 1035#define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32
e429073d
BS		 1036#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
1037#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
1038#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
1039#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
1040#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
0b6ce4cf
FB		 1041#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
1042#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
1043#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
1044#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
1045#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
1046#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
911d79ba
AJ		 1047#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
1048#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
1049#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
945ca823 1050#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
3c51a985 1051#define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
f24cb33e
AJ		 1052#define tcg_gen_andc_tl tcg_gen_andc_i64
1053#define tcg_gen_eqv_tl tcg_gen_eqv_i64
1054#define tcg_gen_nand_tl tcg_gen_nand_i64
1055#define tcg_gen_nor_tl tcg_gen_nor_i64
1056#define tcg_gen_orc_tl tcg_gen_orc_i64
0e28d006
RH		 1057#define tcg_gen_clz_tl tcg_gen_clz_i64
1058#define tcg_gen_ctz_tl tcg_gen_ctz_i64
1059#define tcg_gen_clzi_tl tcg_gen_clzi_i64
1060#define tcg_gen_ctzi_tl tcg_gen_ctzi_i64
086920c2 1061#define tcg_gen_clrsb_tl tcg_gen_clrsb_i64
a768e4e9 1062#define tcg_gen_ctpop_tl tcg_gen_ctpop_i64
15824571
AJ		 1063#define tcg_gen_rotl_tl tcg_gen_rotl_i64
1064#define tcg_gen_rotli_tl tcg_gen_rotli_i64
1065#define tcg_gen_rotr_tl tcg_gen_rotr_i64
1066#define tcg_gen_rotri_tl tcg_gen_rotri_i64
b7767f0f 1067#define tcg_gen_deposit_tl tcg_gen_deposit_i64
07cc68d5 1068#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
7ec8bab3
RH		 1069#define tcg_gen_extract_tl tcg_gen_extract_i64
1070#define tcg_gen_sextract_tl tcg_gen_sextract_i64
a98824ac 1071#define tcg_const_tl tcg_const_i64
bdffd4a9 1072#define tcg_const_local_tl tcg_const_local_i64
ffc5ea09 1073#define tcg_gen_movcond_tl tcg_gen_movcond_i64
f6953a73
RH		 1074#define tcg_gen_add2_tl tcg_gen_add2_i64
1075#define tcg_gen_sub2_tl tcg_gen_sub2_i64
696a8be6
RH		 1076#define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
1077#define tcg_gen_muls2_tl tcg_gen_muls2_i64
5087abfb 1078#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64
b87fb8cd
RH		 1079#define tcg_gen_smin_tl tcg_gen_smin_i64
1080#define tcg_gen_umin_tl tcg_gen_umin_i64
1081#define tcg_gen_smax_tl tcg_gen_smax_i64
1082#define tcg_gen_umax_tl tcg_gen_umax_i64
c482cb11
RH		 1083#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64
1084#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64
1085#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64
1086#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64
1087#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64
1088#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64
5507c2bf
RH		 1089#define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i64
1090#define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i64
1091#define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i64
1092#define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i64
c482cb11
RH		 1093#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64
1094#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64
1095#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64
1096#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64
5507c2bf
RH		 1097#define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i64
1098#define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i64
1099#define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i64
1100#define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64
d2fd745f 1101#define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec
f8422f52 1102#else
f8422f52
BS		 1103#define tcg_gen_movi_tl tcg_gen_movi_i32
1104#define tcg_gen_mov_tl tcg_gen_mov_i32
1105#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
1106#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
1107#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
1108#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
1109#define tcg_gen_ld32u_tl tcg_gen_ld_i32
1110#define tcg_gen_ld32s_tl tcg_gen_ld_i32
1111#define tcg_gen_ld_tl tcg_gen_ld_i32
1112#define tcg_gen_st8_tl tcg_gen_st8_i32
1113#define tcg_gen_st16_tl tcg_gen_st16_i32
1114#define tcg_gen_st32_tl tcg_gen_st_i32
1115#define tcg_gen_st_tl tcg_gen_st_i32
1116#define tcg_gen_add_tl tcg_gen_add_i32
1117#define tcg_gen_addi_tl tcg_gen_addi_i32
1118#define tcg_gen_sub_tl tcg_gen_sub_i32
390efc54 1119#define tcg_gen_neg_tl tcg_gen_neg_i32
0045734a 1120#define tcg_gen_subfi_tl tcg_gen_subfi_i32
f8422f52
BS		 1121#define tcg_gen_subi_tl tcg_gen_subi_i32
1122#define tcg_gen_and_tl tcg_gen_and_i32
1123#define tcg_gen_andi_tl tcg_gen_andi_i32
1124#define tcg_gen_or_tl tcg_gen_or_i32
1125#define tcg_gen_ori_tl tcg_gen_ori_i32
1126#define tcg_gen_xor_tl tcg_gen_xor_i32
1127#define tcg_gen_xori_tl tcg_gen_xori_i32
0b6ce4cf 1128#define tcg_gen_not_tl tcg_gen_not_i32
f8422f52
BS		 1129#define tcg_gen_shl_tl tcg_gen_shl_i32
1130#define tcg_gen_shli_tl tcg_gen_shli_i32
1131#define tcg_gen_shr_tl tcg_gen_shr_i32
1132#define tcg_gen_shri_tl tcg_gen_shri_i32
1133#define tcg_gen_sar_tl tcg_gen_sar_i32
1134#define tcg_gen_sari_tl tcg_gen_sari_i32
0cf767d6 1135#define tcg_gen_brcond_tl tcg_gen_brcond_i32
cb63669a 1136#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
be210acb 1137#define tcg_gen_setcond_tl tcg_gen_setcond_i32
add1e7ea 1138#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
f730fd27
TS		 1139#define tcg_gen_mul_tl tcg_gen_mul_i32
1140#define tcg_gen_muli_tl tcg_gen_muli_i32
ab36421e
AJ		 1141#define tcg_gen_div_tl tcg_gen_div_i32
1142#define tcg_gen_rem_tl tcg_gen_rem_i32
864951af
AJ		 1143#define tcg_gen_divu_tl tcg_gen_divu_i32
1144#define tcg_gen_remu_tl tcg_gen_remu_i32
a768e4b2 1145#define tcg_gen_discard_tl tcg_gen_discard_i32
e429073d 1146#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
ecc7b3aa 1147#define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32
e429073d
BS		 1148#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
1149#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
1150#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
1151#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
0b6ce4cf
FB		 1152#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
1153#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
1154#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
1155#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
1156#define tcg_gen_ext32u_tl tcg_gen_mov_i32
1157#define tcg_gen_ext32s_tl tcg_gen_mov_i32
911d79ba
AJ		 1158#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
1159#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
945ca823 1160#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
e3eb9806 1161#define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
f24cb33e
AJ		 1162#define tcg_gen_andc_tl tcg_gen_andc_i32
1163#define tcg_gen_eqv_tl tcg_gen_eqv_i32
1164#define tcg_gen_nand_tl tcg_gen_nand_i32
1165#define tcg_gen_nor_tl tcg_gen_nor_i32
1166#define tcg_gen_orc_tl tcg_gen_orc_i32
0e28d006
RH		 1167#define tcg_gen_clz_tl tcg_gen_clz_i32
1168#define tcg_gen_ctz_tl tcg_gen_ctz_i32
1169#define tcg_gen_clzi_tl tcg_gen_clzi_i32
1170#define tcg_gen_ctzi_tl tcg_gen_ctzi_i32
086920c2 1171#define tcg_gen_clrsb_tl tcg_gen_clrsb_i32
a768e4e9 1172#define tcg_gen_ctpop_tl tcg_gen_ctpop_i32
15824571
AJ		 1173#define tcg_gen_rotl_tl tcg_gen_rotl_i32
1174#define tcg_gen_rotli_tl tcg_gen_rotli_i32
1175#define tcg_gen_rotr_tl tcg_gen_rotr_i32
1176#define tcg_gen_rotri_tl tcg_gen_rotri_i32
b7767f0f 1177#define tcg_gen_deposit_tl tcg_gen_deposit_i32
07cc68d5 1178#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
7ec8bab3
RH		 1179#define tcg_gen_extract_tl tcg_gen_extract_i32
1180#define tcg_gen_sextract_tl tcg_gen_sextract_i32
a98824ac 1181#define tcg_const_tl tcg_const_i32
bdffd4a9 1182#define tcg_const_local_tl tcg_const_local_i32
ffc5ea09 1183#define tcg_gen_movcond_tl tcg_gen_movcond_i32
f6953a73
RH		 1184#define tcg_gen_add2_tl tcg_gen_add2_i32
1185#define tcg_gen_sub2_tl tcg_gen_sub2_i32
696a8be6
RH		 1186#define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
1187#define tcg_gen_muls2_tl tcg_gen_muls2_i32
5087abfb 1188#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32
b87fb8cd
RH		 1189#define tcg_gen_smin_tl tcg_gen_smin_i32
1190#define tcg_gen_umin_tl tcg_gen_umin_i32
1191#define tcg_gen_smax_tl tcg_gen_smax_i32
1192#define tcg_gen_umax_tl tcg_gen_umax_i32
c482cb11
RH		 1193#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32
1194#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32
1195#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32
1196#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32
1197#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32
1198#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32
5507c2bf
RH		 1199#define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i32
1200#define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i32
1201#define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i32
1202#define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i32
c482cb11
RH		 1203#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32
1204#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32
1205#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32
1206#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32
5507c2bf
RH		 1207#define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i32
1208#define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i32
1209#define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i32
1210#define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32
d2fd745f 1211#define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec
f8422f52 1212#endif
6ddbc6e4 1213
71b92699 1214#if UINTPTR_MAX == UINT32_MAX
5bfa8034
RH		 1215# define PTR i32
1216# define NAT TCGv_i32
f713d6ad 1217#else
5bfa8034
RH		 1218# define PTR i64
1219# define NAT TCGv_i64
1220#endif
1221
1222static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o)
1223{
1224 glue(tcg_gen_ld_,PTR)((NAT)r, a, o);
1225}
1226
1227static inline void tcg_gen_discard_ptr(TCGv_ptr a)
1228{
1229 glue(tcg_gen_discard_,PTR)((NAT)a);
1230}
1231
1232static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b)
1233{
1234 glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b);
1235}
1236
1237static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b)
1238{
1239 glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b);
1240}
1241
1242static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a,
1243 intptr_t b, TCGLabel *label)
1244{
1245 glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label);
1246}
1247
1248static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a)
1249{
1250#if UINTPTR_MAX == UINT32_MAX
1251 tcg_gen_mov_i32((NAT)r, a);
1252#else
1253 tcg_gen_ext_i32_i64((NAT)r, a);
1254#endif
1255}
1256
1257static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a)
1258{
1259#if UINTPTR_MAX == UINT32_MAX
1260 tcg_gen_extrl_i64_i32((NAT)r, a);
1261#else
1262 tcg_gen_mov_i64((NAT)r, a);
1263#endif
1264}
1265
1266static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a)
1267{
1268#if UINTPTR_MAX == UINT32_MAX
1269 tcg_gen_extu_i32_i64(r, (NAT)a);
1270#else
1271 tcg_gen_mov_i64(r, (NAT)a);
1272#endif
1273}
1274
1275static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a)
1276{
1277#if UINTPTR_MAX == UINT32_MAX
1278 tcg_gen_mov_i32(r, (NAT)a);
1279#else
1280 tcg_gen_extrl_i64_i32(r, (NAT)a);
1281#endif
1282}
1283
1284#undef PTR
1285#undef NAT
a7ce790a
PM		 1286
1287#endif /* TCG_TCG_OP_H */
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