[mirror_qemu.git] / tcg / tcg-opc.h

/*
 * Tiny Code Generator for QEMU
 *
 * Copyright (c) 2008 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/*
 * DEF(name, oargs, iargs, cargs, flags)
 */

/* predefined ops */
DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)

/* variable number of parameters */
DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT)

DEF(br, 0, 0, 1, TCG_OPF_BB_END)

#define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0)
#if TCG_TARGET_REG_BITS == 32
# define IMPL64  TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
#else
# define IMPL64  TCG_OPF_64BIT
#endif

DEF(mb, 0, 0, 1, 0)

DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
DEF(setcond_i32, 1, 2, 1, 0)
DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
/* load/store */
DEF(ld8u_i32, 1, 1, 1, 0)
DEF(ld8s_i32, 1, 1, 1, 0)
DEF(ld16u_i32, 1, 1, 1, 0)
DEF(ld16s_i32, 1, 1, 1, 0)
DEF(ld_i32, 1, 1, 1, 0)
DEF(st8_i32, 0, 2, 1, 0)
DEF(st16_i32, 0, 2, 1, 0)
DEF(st_i32, 0, 2, 1, 0)
/* arith */
DEF(add_i32, 1, 2, 0, 0)
DEF(sub_i32, 1, 2, 0, 0)
DEF(mul_i32, 1, 2, 0, 0)
DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
DEF(and_i32, 1, 2, 0, 0)
DEF(or_i32, 1, 2, 0, 0)
DEF(xor_i32, 1, 2, 0, 0)
/* shifts/rotates */
DEF(shl_i32, 1, 2, 0, 0)
DEF(shr_i32, 1, 2, 0, 0)
DEF(sar_i32, 1, 2, 0, 0)
DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32))
DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32))
DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32))

DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)

DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32))
DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32))
DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32))
DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))

DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32))
DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32))
DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32))
DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32))
DEF(clz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_clz_i32))
DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32))
DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32))

DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
DEF(setcond_i64, 1, 2, 1, IMPL64)
DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64))
/* load/store */
DEF(ld8u_i64, 1, 1, 1, IMPL64)
DEF(ld8s_i64, 1, 1, 1, IMPL64)
DEF(ld16u_i64, 1, 1, 1, IMPL64)
DEF(ld16s_i64, 1, 1, 1, IMPL64)
DEF(ld32u_i64, 1, 1, 1, IMPL64)
DEF(ld32s_i64, 1, 1, 1, IMPL64)
DEF(ld_i64, 1, 1, 1, IMPL64)
DEF(st8_i64, 0, 2, 1, IMPL64)
DEF(st16_i64, 0, 2, 1, IMPL64)
DEF(st32_i64, 0, 2, 1, IMPL64)
DEF(st_i64, 0, 2, 1, IMPL64)
/* arith */
DEF(add_i64, 1, 2, 0, IMPL64)
DEF(sub_i64, 1, 2, 0, IMPL64)
DEF(mul_i64, 1, 2, 0, IMPL64)
DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
DEF(and_i64, 1, 2, 0, IMPL64)
DEF(or_i64, 1, 2, 0, IMPL64)
DEF(xor_i64, 1, 2, 0, IMPL64)
/* shifts/rotates */
DEF(shl_i64, 1, 2, 0, IMPL64)
DEF(shr_i64, 1, 2, 0, IMPL64)
DEF(sar_i64, 1, 2, 0, IMPL64)
DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64))
DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64))
DEF(extract2_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_extract2_i64))

/* size changing ops */
DEF(ext_i32_i64, 1, 1, 0, IMPL64)
DEF(extu_i32_i64, 1, 1, 0, IMPL64)
DEF(extrl_i64_i32, 1, 1, 0,
    IMPL(TCG_TARGET_HAS_extrl_i64_i32)
    | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
DEF(extrh_i64_i32, 1, 1, 0,
    IMPL(TCG_TARGET_HAS_extrh_i64_i32)
    | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))

DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64)
DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64))
DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64))
DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64))
DEF(bswap16_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
DEF(bswap32_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
DEF(bswap64_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64))
DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64))
DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64))
DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64))
DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64))
DEF(clz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_clz_i64))
DEF(ctz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctz_i64))
DEF(ctpop_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctpop_i64))

DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh_i64))
DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64))

#define TLADDR_ARGS  (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2)
#define DATA64_ARGS  (TCG_TARGET_REG_BITS == 64 ? 1 : 2)

/* QEMU specific */
DEF(insn_start, 0, 0, TLADDR_ARGS * TARGET_INSN_START_WORDS,
    TCG_OPF_NOT_PRESENT)
DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
DEF(goto_ptr, 0, 1, 0,
    TCG_OPF_BB_EXIT | TCG_OPF_BB_END | IMPL(TCG_TARGET_HAS_goto_ptr))

DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1,
    TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 1,
    TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1,
    TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1,
    TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)

/* Host vector support.  */

#define IMPLVEC  TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec)

DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
DEF(dupi_vec, 1, 0, 1, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)

DEF(dup_vec, 1, 1, 0, IMPLVEC)
DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32))

DEF(ld_vec, 1, 1, 1, IMPLVEC)
DEF(st_vec, 0, 2, 1, IMPLVEC)

DEF(add_vec, 1, 2, 0, IMPLVEC)
DEF(sub_vec, 1, 2, 0, IMPLVEC)
DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec))
DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec))
DEF(ssadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
DEF(usadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
DEF(sssub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
DEF(ussub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
DEF(smin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
DEF(umin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
DEF(smax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
DEF(umax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))

DEF(and_vec, 1, 2, 0, IMPLVEC)
DEF(or_vec, 1, 2, 0, IMPLVEC)
DEF(xor_vec, 1, 2, 0, IMPLVEC)
DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))

DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))

DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))

DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))

DEF(cmp_vec, 1, 2, 1, IMPLVEC)

DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)

#if TCG_TARGET_MAYBE_vec
#include "tcg-target.opc.h"
#endif

#undef TLADDR_ARGS
#undef DATA64_ARGS
#undef IMPL
#undef IMPL64
#undef IMPLVEC
#undef DEF
Commit	Line	Data
c896fe29 FB	1	/*
	2	* Tiny Code Generator for QEMU
	3	*
	4	* Copyright (c) 2008 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
c61aaf7a AJ	24
	25	/*
	26	* DEF(name, oargs, iargs, cargs, flags)
	27	*/
c896fe29 FB	28
c896fe29 FB	29	/* predefined ops */
c1a61f6c RH	30	DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
	31	DEF(set_label, 0, 0, 1, TCG_OPF_BB_END \| TCG_OPF_NOT_PRESENT)
	32
	33	/* variable number of parameters */
96d0ee7f	34	DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER \| TCG_OPF_NOT_PRESENT)
5ff9d6a4	35
344028ba	36	DEF(br, 0, 0, 1, TCG_OPF_BB_END)
c896fe29	37
4ef76952	38	#define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0)
25c4d9cc RH	39	#if TCG_TARGET_REG_BITS == 32
	40	# define IMPL64 TCG_OPF_64BIT \| TCG_OPF_NOT_PRESENT
	41	#else
	42	# define IMPL64 TCG_OPF_64BIT
	43	#endif
	44
f65e19bc PK	45	DEF(mb, 0, 0, 1, 0)
f65e19bc PK	46
96d0ee7f RH	47	DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
96d0ee7f RH	48	DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
c61aaf7a	49	DEF(setcond_i32, 1, 2, 1, 0)
ffc5ea09	50	DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
c896fe29	51	/* load/store */
c61aaf7a AJ	52	DEF(ld8u_i32, 1, 1, 1, 0)
	53	DEF(ld8s_i32, 1, 1, 1, 0)
	54	DEF(ld16u_i32, 1, 1, 1, 0)
	55	DEF(ld16s_i32, 1, 1, 1, 0)
	56	DEF(ld_i32, 1, 1, 1, 0)
b202d41e AJ	57	DEF(st8_i32, 0, 2, 1, 0)
	58	DEF(st16_i32, 0, 2, 1, 0)
	59	DEF(st_i32, 0, 2, 1, 0)
c896fe29	60	/* arith */
c61aaf7a AJ	61	DEF(add_i32, 1, 2, 0, 0)
	62	DEF(sub_i32, 1, 2, 0, 0)
	63	DEF(mul_i32, 1, 2, 0, 0)
25c4d9cc RH	64	DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
25c4d9cc RH	65	DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
ca675f46 RH	66	DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
ca675f46 RH	67	DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
25c4d9cc RH	68	DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
25c4d9cc RH	69	DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
c61aaf7a AJ	70	DEF(and_i32, 1, 2, 0, 0)
	71	DEF(or_i32, 1, 2, 0, 0)
	72	DEF(xor_i32, 1, 2, 0, 0)
d42f183c	73	/* shifts/rotates */
c61aaf7a AJ	74	DEF(shl_i32, 1, 2, 0, 0)
	75	DEF(shr_i32, 1, 2, 0, 0)
	76	DEF(sar_i32, 1, 2, 0, 0)
25c4d9cc RH	77	DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
	78	DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
	79	DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
7ec8bab3 RH	80	DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32))
7ec8bab3 RH	81	DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32))
fce1296f	82	DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32))
c896fe29	83
344028ba	84	DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
c896fe29	85
e6a72734 RH	86	DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
	87	DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
	88	DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
4d3203fd	89	DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
03271524 RH	90	DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32))
03271524 RH	91	DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32))
344028ba	92	DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END \| IMPL(TCG_TARGET_REG_BITS == 32))
25c4d9cc RH	93	DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
	94
	95	DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
	96	DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
	97	DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
	98	DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
	99	DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32))
	100	DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32))
	101	DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
	102	DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
	103	DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
	104	DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
	105	DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
	106	DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32))
	107	DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32))
0e28d006 RH	108	DEF(clz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_clz_i32))
0e28d006 RH	109	DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32))
a768e4e9	110	DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32))
25c4d9cc	111
96d0ee7f RH	112	DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT \| TCG_OPF_NOT_PRESENT)
96d0ee7f RH	113	DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT \| TCG_OPF_NOT_PRESENT)
25c4d9cc	114	DEF(setcond_i64, 1, 2, 1, IMPL64)
ffc5ea09	115	DEF(movcond_i64, 1, 4, 1, IMPL64 \| IMPL(TCG_TARGET_HAS_movcond_i64))
c896fe29	116	/* load/store */
25c4d9cc RH	117	DEF(ld8u_i64, 1, 1, 1, IMPL64)
	118	DEF(ld8s_i64, 1, 1, 1, IMPL64)
	119	DEF(ld16u_i64, 1, 1, 1, IMPL64)
	120	DEF(ld16s_i64, 1, 1, 1, IMPL64)
	121	DEF(ld32u_i64, 1, 1, 1, IMPL64)
	122	DEF(ld32s_i64, 1, 1, 1, IMPL64)
	123	DEF(ld_i64, 1, 1, 1, IMPL64)
b202d41e AJ	124	DEF(st8_i64, 0, 2, 1, IMPL64)
	125	DEF(st16_i64, 0, 2, 1, IMPL64)
	126	DEF(st32_i64, 0, 2, 1, IMPL64)
	127	DEF(st_i64, 0, 2, 1, IMPL64)
c896fe29	128	/* arith */
25c4d9cc RH	129	DEF(add_i64, 1, 2, 0, IMPL64)
	130	DEF(sub_i64, 1, 2, 0, IMPL64)
	131	DEF(mul_i64, 1, 2, 0, IMPL64)
	132	DEF(div_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_div_i64))
	133	DEF(divu_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_div_i64))
ca675f46 RH	134	DEF(rem_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_rem_i64))
ca675f46 RH	135	DEF(remu_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_rem_i64))
25c4d9cc RH	136	DEF(div2_i64, 2, 3, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_div2_i64))
	137	DEF(divu2_i64, 2, 3, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_div2_i64))
	138	DEF(and_i64, 1, 2, 0, IMPL64)
	139	DEF(or_i64, 1, 2, 0, IMPL64)
	140	DEF(xor_i64, 1, 2, 0, IMPL64)
d42f183c	141	/* shifts/rotates */
25c4d9cc RH	142	DEF(shl_i64, 1, 2, 0, IMPL64)
	143	DEF(shr_i64, 1, 2, 0, IMPL64)
	144	DEF(sar_i64, 1, 2, 0, IMPL64)
	145	DEF(rotl_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_rot_i64))
	146	DEF(rotr_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_rot_i64))
	147	DEF(deposit_i64, 1, 2, 2, IMPL64 \| IMPL(TCG_TARGET_HAS_deposit_i64))
7ec8bab3 RH	148	DEF(extract_i64, 1, 1, 2, IMPL64 \| IMPL(TCG_TARGET_HAS_extract_i64))
7ec8bab3 RH	149	DEF(sextract_i64, 1, 1, 2, IMPL64 \| IMPL(TCG_TARGET_HAS_sextract_i64))
fce1296f	150	DEF(extract2_i64, 1, 2, 1, IMPL64 \| IMPL(TCG_TARGET_HAS_extract2_i64))
c896fe29	151
4f2331e5 AJ	152	/* size changing ops */
	153	DEF(ext_i32_i64, 1, 1, 0, IMPL64)
	154	DEF(extu_i32_i64, 1, 1, 0, IMPL64)
609ad705 RH	155	DEF(extrl_i64_i32, 1, 1, 0,
	156	IMPL(TCG_TARGET_HAS_extrl_i64_i32)
	157	\| (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
	158	DEF(extrh_i64_i32, 1, 1, 0,
	159	IMPL(TCG_TARGET_HAS_extrh_i64_i32)
4bb7a41e RH	160	\| (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
4bb7a41e RH	161
344028ba	162	DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END \| IMPL64)
25c4d9cc RH	163	DEF(ext8s_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_ext8s_i64))
	164	DEF(ext16s_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_ext16s_i64))
	165	DEF(ext32s_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_ext32s_i64))
	166	DEF(ext8u_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_ext8u_i64))
	167	DEF(ext16u_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_ext16u_i64))
	168	DEF(ext32u_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_ext32u_i64))
	169	DEF(bswap16_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_bswap16_i64))
	170	DEF(bswap32_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_bswap32_i64))
	171	DEF(bswap64_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_bswap64_i64))
	172	DEF(not_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_not_i64))
	173	DEF(neg_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_neg_i64))
	174	DEF(andc_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_andc_i64))
	175	DEF(orc_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_orc_i64))
	176	DEF(eqv_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_eqv_i64))
	177	DEF(nand_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_nand_i64))
	178	DEF(nor_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_nor_i64))
0e28d006 RH	179	DEF(clz_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_clz_i64))
0e28d006 RH	180	DEF(ctz_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_ctz_i64))
a768e4e9	181	DEF(ctpop_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_ctpop_i64))
c896fe29	182
d7156f7c RH	183	DEF(add2_i64, 2, 4, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_add2_i64))
	184	DEF(sub2_i64, 2, 4, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_sub2_i64))
	185	DEF(mulu2_i64, 2, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_mulu2_i64))
4d3203fd	186	DEF(muls2_i64, 2, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_muls2_i64))
f2f1dde7 RH	187	DEF(muluh_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_muluh_i64))
f2f1dde7 RH	188	DEF(mulsh_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_mulsh_i64))
d7156f7c	189
c0e40dbd JH	190	#define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2)
	191	#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
	192
c896fe29	193	/* QEMU specific */
c0e40dbd JH	194	DEF(insn_start, 0, 0, TLADDR_ARGS * TARGET_INSN_START_WORDS,
c0e40dbd JH	195	TCG_OPF_NOT_PRESENT)
ae36a246 RH	196	DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT \| TCG_OPF_BB_END)
	197	DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT \| TCG_OPF_BB_END)
	198	DEF(goto_ptr, 0, 1, 0,
	199	TCG_OPF_BB_EXIT \| TCG_OPF_BB_END \| IMPL(TCG_TARGET_HAS_goto_ptr))
f713d6ad	200
59227d5d	201	DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1,
3d1b2ff6	202	TCG_OPF_CALL_CLOBBER \| TCG_OPF_SIDE_EFFECTS)
59227d5d	203	DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 1,
3d1b2ff6	204	TCG_OPF_CALL_CLOBBER \| TCG_OPF_SIDE_EFFECTS)
59227d5d	205	DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1,
3d1b2ff6	206	TCG_OPF_CALL_CLOBBER \| TCG_OPF_SIDE_EFFECTS \| TCG_OPF_64BIT)
59227d5d	207	DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1,
3d1b2ff6 RH	208	TCG_OPF_CALL_CLOBBER \| TCG_OPF_SIDE_EFFECTS \| TCG_OPF_64BIT)
3d1b2ff6 RH	209
d2fd745f RH	210	/* Host vector support. */
	211
	212	#define IMPLVEC TCG_OPF_VECTOR \| IMPL(TCG_TARGET_MAYBE_vec)
	213
	214	DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR \| TCG_OPF_NOT_PRESENT)
	215	DEF(dupi_vec, 1, 0, 1, TCG_OPF_VECTOR \| TCG_OPF_NOT_PRESENT)
	216
	217	DEF(dup_vec, 1, 1, 0, IMPLVEC)
	218	DEF(dup2_vec, 1, 2, 0, IMPLVEC \| IMPL(TCG_TARGET_REG_BITS == 32))
	219
	220	DEF(ld_vec, 1, 1, 1, IMPLVEC)
	221	DEF(st_vec, 0, 2, 1, IMPLVEC)
	222
	223	DEF(add_vec, 1, 2, 0, IMPLVEC)
	224	DEF(sub_vec, 1, 2, 0, IMPLVEC)
3774030a	225	DEF(mul_vec, 1, 2, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_mul_vec))
d2fd745f	226	DEF(neg_vec, 1, 1, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_neg_vec))
8afaf050 RH	227	DEF(ssadd_vec, 1, 2, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_sat_vec))
	228	DEF(usadd_vec, 1, 2, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_sat_vec))
	229	DEF(sssub_vec, 1, 2, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_sat_vec))
	230	DEF(ussub_vec, 1, 2, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_sat_vec))
dd0a0fcd RH	231	DEF(smin_vec, 1, 2, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_minmax_vec))
	232	DEF(umin_vec, 1, 2, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_minmax_vec))
	233	DEF(smax_vec, 1, 2, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_minmax_vec))
	234	DEF(umax_vec, 1, 2, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_minmax_vec))
d2fd745f RH	235
	236	DEF(and_vec, 1, 2, 0, IMPLVEC)
	237	DEF(or_vec, 1, 2, 0, IMPLVEC)
	238	DEF(xor_vec, 1, 2, 0, IMPLVEC)
	239	DEF(andc_vec, 1, 2, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_andc_vec))
	240	DEF(orc_vec, 1, 2, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_orc_vec))
	241	DEF(not_vec, 1, 1, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_not_vec))
	242
d0ec9796 RH	243	DEF(shli_vec, 1, 1, 1, IMPLVEC \| IMPL(TCG_TARGET_HAS_shi_vec))
	244	DEF(shri_vec, 1, 1, 1, IMPLVEC \| IMPL(TCG_TARGET_HAS_shi_vec))
	245	DEF(sari_vec, 1, 1, 1, IMPLVEC \| IMPL(TCG_TARGET_HAS_shi_vec))
	246
	247	DEF(shls_vec, 1, 2, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_shs_vec))
	248	DEF(shrs_vec, 1, 2, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_shs_vec))
	249	DEF(sars_vec, 1, 2, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_shs_vec))
	250
	251	DEF(shlv_vec, 1, 2, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_shv_vec))
	252	DEF(shrv_vec, 1, 2, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_shv_vec))
	253	DEF(sarv_vec, 1, 2, 0, IMPLVEC \| IMPL(TCG_TARGET_HAS_shv_vec))
	254
212be173 RH	255	DEF(cmp_vec, 1, 2, 1, IMPLVEC)
212be173 RH	256
db432672 RH	257	DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
	258
	259	#if TCG_TARGET_MAYBE_vec
	260	#include "tcg-target.opc.h"
	261	#endif
	262
3d1b2ff6 RH	263	#undef TLADDR_ARGS
3d1b2ff6 RH	264	#undef DATA64_ARGS
25c4d9cc RH	265	#undef IMPL
25c4d9cc RH	266	#undef IMPL64
d2fd745f	267	#undef IMPLVEC
c61aaf7a	268	#undef DEF