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bbfc2efe
AF
1/*
2 * QTest testcase for ivshmem
3 *
4 * Copyright (c) 2014 SUSE LINUX Products GmbH
ddef6a0d 5 * Copyright (c) 2015 Red Hat, Inc.
bbfc2efe
AF
6 *
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
9 */
10
681c28a3 11#include "qemu/osdep.h"
ddef6a0d 12#include <glib/gstdio.h>
ddef6a0d 13#include "contrib/ivshmem-server/ivshmem-server.h"
d69487d5 14#include "libqos/libqos-pc.h"
2bf25e07 15#include "libqos/libqos-spapr.h"
bbfc2efe 16#include "libqtest.h"
ddef6a0d 17#include "qemu-common.h"
bbfc2efe 18
ddef6a0d
MAL
19#define TMPSHMSIZE (1 << 20)
20static char *tmpshm;
21static void *tmpshmem;
22static char *tmpdir;
23static char *tmpserver;
bbfc2efe 24
ddef6a0d 25static void save_fn(QPCIDevice *dev, int devfn, void *data)
bbfc2efe 26{
ddef6a0d
MAL
27 QPCIDevice **pdev = (QPCIDevice **) data;
28
29 *pdev = dev;
30}
31
1760048a 32static QPCIDevice *get_device(QPCIBus *pcibus)
ddef6a0d
MAL
33{
34 QPCIDevice *dev;
ddef6a0d 35
16130947 36 dev = NULL;
ddef6a0d
MAL
37 qpci_device_foreach(pcibus, 0x1af4, 0x1110, save_fn, &dev);
38 g_assert(dev != NULL);
39
40 return dev;
41}
42
43typedef struct _IVState {
d69487d5 44 QOSState *qs;
b4ba67d9 45 QPCIBar reg_bar, mem_bar;
ddef6a0d
MAL
46 QPCIDevice *dev;
47} IVState;
48
49enum Reg {
50 INTRMASK = 0,
51 INTRSTATUS = 4,
52 IVPOSITION = 8,
53 DOORBELL = 12,
54};
55
56static const char* reg2str(enum Reg reg) {
57 switch (reg) {
58 case INTRMASK:
59 return "IntrMask";
60 case INTRSTATUS:
61 return "IntrStatus";
62 case IVPOSITION:
63 return "IVPosition";
64 case DOORBELL:
65 return "DoorBell";
66 default:
67 return NULL;
68 }
69}
70
71static inline unsigned in_reg(IVState *s, enum Reg reg)
72{
73 const char *name = reg2str(reg);
ddef6a0d
MAL
74 unsigned res;
75
b4ba67d9 76 res = qpci_io_readl(s->dev, s->reg_bar, reg);
13ee9e30 77 g_test_message("*%s -> %x", name, res);
ddef6a0d
MAL
78
79 return res;
80}
81
82static inline void out_reg(IVState *s, enum Reg reg, unsigned v)
83{
84 const char *name = reg2str(reg);
ddef6a0d 85
13ee9e30 86 g_test_message("%x -> *%s", v, name);
b4ba67d9 87 qpci_io_writel(s->dev, s->reg_bar, reg, v);
ddef6a0d
MAL
88}
89
204e54b8
DG
90static inline void read_mem(IVState *s, uint64_t off, void *buf, size_t len)
91{
b4ba67d9 92 qpci_memread(s->dev, s->mem_bar, off, buf, len);
204e54b8
DG
93}
94
95static inline void write_mem(IVState *s, uint64_t off,
96 const void *buf, size_t len)
97{
b4ba67d9 98 qpci_memwrite(s->dev, s->mem_bar, off, buf, len);
204e54b8
DG
99}
100
1760048a
MAL
101static void cleanup_vm(IVState *s)
102{
24c01ffa 103 assert(!global_qtest);
1760048a 104 g_free(s->dev);
d69487d5 105 qtest_shutdown(s->qs);
1760048a
MAL
106}
107
ddef6a0d
MAL
108static void setup_vm_cmd(IVState *s, const char *cmd, bool msix)
109{
110 uint64_t barsize;
d69487d5 111 const char *arch = qtest_get_arch();
ddef6a0d 112
d69487d5
LV
113 if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
114 s->qs = qtest_pc_boot(cmd);
2bf25e07
LV
115 } else if (strcmp(arch, "ppc64") == 0) {
116 s->qs = qtest_spapr_boot(cmd);
d69487d5 117 } else {
2bf25e07 118 g_printerr("ivshmem-test tests are only available on x86 or ppc64\n");
d69487d5
LV
119 exit(EXIT_FAILURE);
120 }
121 s->dev = get_device(s->qs->pcibus);
ddef6a0d 122
b4ba67d9 123 s->reg_bar = qpci_iomap(s->dev, 0, &barsize);
99826172 124 g_assert_cmpuint(barsize, ==, 256);
ddef6a0d
MAL
125
126 if (msix) {
127 qpci_msix_enable(s->dev);
128 }
129
b4ba67d9 130 s->mem_bar = qpci_iomap(s->dev, 2, &barsize);
99826172 131 g_assert_cmpuint(barsize, ==, TMPSHMSIZE);
ddef6a0d
MAL
132
133 qpci_device_enable(s->dev);
134}
135
136static void setup_vm(IVState *s)
137{
5400c02b
MA
138 char *cmd = g_strdup_printf("-object memory-backend-file"
139 ",id=mb1,size=1M,share,mem-path=/dev/shm%s"
140 " -device ivshmem-plain,memdev=mb1", tmpshm);
ddef6a0d
MAL
141
142 setup_vm_cmd(s, cmd, false);
143
144 g_free(cmd);
145}
146
147static void test_ivshmem_single(void)
148{
149 IVState state, *s;
150 uint32_t data[1024];
151 int i;
152
153 setup_vm(&state);
154 s = &state;
155
4958fe5d
MA
156 /* initial state of readable registers */
157 g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0);
158 g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 0);
159 g_assert_cmpuint(in_reg(s, IVPOSITION), ==, 0);
ddef6a0d 160
4958fe5d 161 /* trigger interrupt via registers */
ddef6a0d
MAL
162 out_reg(s, INTRMASK, 0xffffffff);
163 g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0xffffffff);
164 out_reg(s, INTRSTATUS, 1);
4958fe5d 165 /* check interrupt status */
ddef6a0d 166 g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 1);
4958fe5d
MA
167 /* reading clears */
168 g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 0);
169 /* TODO intercept actual interrupt (needs qtest work) */
ddef6a0d 170
4958fe5d 171 /* invalid register access */
ddef6a0d 172 out_reg(s, IVPOSITION, 1);
4958fe5d
MA
173 in_reg(s, DOORBELL);
174
175 /* ring the (non-functional) doorbell */
ddef6a0d
MAL
176 out_reg(s, DOORBELL, 8 << 16);
177
4958fe5d 178 /* write shared memory */
ddef6a0d
MAL
179 for (i = 0; i < G_N_ELEMENTS(data); i++) {
180 data[i] = i;
181 }
204e54b8 182 write_mem(s, 0, data, sizeof(data));
ddef6a0d 183
4958fe5d 184 /* verify write */
ddef6a0d
MAL
185 for (i = 0; i < G_N_ELEMENTS(data); i++) {
186 g_assert_cmpuint(((uint32_t *)tmpshmem)[i], ==, i);
187 }
188
4958fe5d 189 /* read it back and verify read */
ddef6a0d 190 memset(data, 0, sizeof(data));
204e54b8 191 read_mem(s, 0, data, sizeof(data));
ddef6a0d
MAL
192 for (i = 0; i < G_N_ELEMENTS(data); i++) {
193 g_assert_cmpuint(data[i], ==, i);
194 }
195
1760048a 196 cleanup_vm(s);
ddef6a0d
MAL
197}
198
199static void test_ivshmem_pair(void)
200{
201 IVState state1, state2, *s1, *s2;
202 char *data;
203 int i;
204
205 setup_vm(&state1);
206 s1 = &state1;
207 setup_vm(&state2);
208 s2 = &state2;
209
210 data = g_malloc0(TMPSHMSIZE);
211
212 /* host write, guest 1 & 2 read */
213 memset(tmpshmem, 0x42, TMPSHMSIZE);
204e54b8 214 read_mem(s1, 0, data, TMPSHMSIZE);
ddef6a0d
MAL
215 for (i = 0; i < TMPSHMSIZE; i++) {
216 g_assert_cmpuint(data[i], ==, 0x42);
217 }
204e54b8 218 read_mem(s2, 0, data, TMPSHMSIZE);
ddef6a0d
MAL
219 for (i = 0; i < TMPSHMSIZE; i++) {
220 g_assert_cmpuint(data[i], ==, 0x42);
221 }
222
223 /* guest 1 write, guest 2 read */
224 memset(data, 0x43, TMPSHMSIZE);
204e54b8 225 write_mem(s1, 0, data, TMPSHMSIZE);
ddef6a0d 226 memset(data, 0, TMPSHMSIZE);
204e54b8 227 read_mem(s2, 0, data, TMPSHMSIZE);
ddef6a0d
MAL
228 for (i = 0; i < TMPSHMSIZE; i++) {
229 g_assert_cmpuint(data[i], ==, 0x43);
230 }
231
232 /* guest 2 write, guest 1 read */
233 memset(data, 0x44, TMPSHMSIZE);
204e54b8 234 write_mem(s2, 0, data, TMPSHMSIZE);
ddef6a0d 235 memset(data, 0, TMPSHMSIZE);
204e54b8 236 read_mem(s1, 0, data, TMPSHMSIZE);
ddef6a0d
MAL
237 for (i = 0; i < TMPSHMSIZE; i++) {
238 g_assert_cmpuint(data[i], ==, 0x44);
239 }
240
1760048a
MAL
241 cleanup_vm(s1);
242 cleanup_vm(s2);
ddef6a0d
MAL
243 g_free(data);
244}
245
246typedef struct ServerThread {
247 GThread *thread;
248 IvshmemServer *server;
249 int pipe[2]; /* to handle quit */
250} ServerThread;
251
252static void *server_thread(void *data)
253{
254 ServerThread *t = data;
255 IvshmemServer *server = t->server;
256
257 while (true) {
258 fd_set fds;
259 int maxfd, ret;
260
261 FD_ZERO(&fds);
262 FD_SET(t->pipe[0], &fds);
263 maxfd = t->pipe[0] + 1;
264
265 ivshmem_server_get_fds(server, &fds, &maxfd);
266
267 ret = select(maxfd, &fds, NULL, NULL, NULL);
268
269 if (ret < 0) {
270 if (errno == EINTR) {
271 continue;
272 }
273
274 g_critical("select error: %s\n", strerror(errno));
275 break;
276 }
277 if (ret == 0) {
278 continue;
279 }
280
281 if (FD_ISSET(t->pipe[0], &fds)) {
282 break;
283 }
284
285 if (ivshmem_server_handle_fds(server, &fds, maxfd) < 0) {
286 g_critical("ivshmem_server_handle_fds() failed\n");
287 break;
288 }
289 }
290
291 return NULL;
292}
293
5a0e75f0 294static void setup_vm_with_server(IVState *s, int nvectors)
ddef6a0d 295{
5a0e75f0 296 char *cmd;
ddef6a0d 297
767abe7f 298 cmd = g_strdup_printf("-chardev socket,id=chr0,path=%s "
5a0e75f0
TH
299 "-device ivshmem-doorbell,chardev=chr0,vectors=%d",
300 tmpserver, nvectors);
301
302 setup_vm_cmd(s, cmd, true);
ddef6a0d
MAL
303
304 g_free(cmd);
305}
306
5a0e75f0 307static void test_ivshmem_server(void)
ddef6a0d
MAL
308{
309 IVState state1, state2, *s1, *s2;
310 ServerThread thread;
311 IvshmemServer server;
312 int ret, vm1, vm2;
313 int nvectors = 2;
314 guint64 end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND;
315
3625c739 316 ret = ivshmem_server_init(&server, tmpserver, tmpshm, true,
ddef6a0d
MAL
317 TMPSHMSIZE, nvectors,
318 g_test_verbose());
319 g_assert_cmpint(ret, ==, 0);
320
321 ret = ivshmem_server_start(&server);
322 g_assert_cmpint(ret, ==, 0);
323
ddef6a0d
MAL
324 thread.server = &server;
325 ret = pipe(thread.pipe);
326 g_assert_cmpint(ret, ==, 0);
327 thread.thread = g_thread_new("ivshmem-server", server_thread, &thread);
328 g_assert(thread.thread != NULL);
329
5a0e75f0 330 setup_vm_with_server(&state1, nvectors);
3a55fc0f 331 s1 = &state1;
5a0e75f0 332 setup_vm_with_server(&state2, nvectors);
3a55fc0f 333 s2 = &state2;
ddef6a0d
MAL
334
335 /* check got different VM ids */
336 vm1 = in_reg(s1, IVPOSITION);
337 vm2 = in_reg(s2, IVPOSITION);
3a55fc0f
MA
338 g_assert_cmpint(vm1, >=, 0);
339 g_assert_cmpint(vm2, >=, 0);
340 g_assert_cmpint(vm1, !=, vm2);
ddef6a0d 341
41b65e5e 342 /* check number of MSI-X vectors */
5a0e75f0
TH
343 ret = qpci_msix_table_size(s1->dev);
344 g_assert_cmpuint(ret, ==, nvectors);
ddef6a0d 345
41b65e5e
MA
346 /* TODO test behavior before MSI-X is enabled */
347
348 /* ping vm2 -> vm1 on vector 0 */
5a0e75f0
TH
349 ret = qpci_msix_pending(s1->dev, 0);
350 g_assert_cmpuint(ret, ==, 0);
ddef6a0d
MAL
351 out_reg(s2, DOORBELL, vm1 << 16);
352 do {
353 g_usleep(10000);
5a0e75f0 354 ret = qpci_msix_pending(s1->dev, 0);
ddef6a0d
MAL
355 } while (ret == 0 && g_get_monotonic_time() < end_time);
356 g_assert_cmpuint(ret, !=, 0);
357
41b65e5e 358 /* ping vm1 -> vm2 on vector 1 */
5a0e75f0
TH
359 ret = qpci_msix_pending(s2->dev, 1);
360 g_assert_cmpuint(ret, ==, 0);
41b65e5e 361 out_reg(s1, DOORBELL, vm2 << 16 | 1);
ddef6a0d
MAL
362 do {
363 g_usleep(10000);
5a0e75f0 364 ret = qpci_msix_pending(s2->dev, 1);
ddef6a0d
MAL
365 } while (ret == 0 && g_get_monotonic_time() < end_time);
366 g_assert_cmpuint(ret, !=, 0);
367
1760048a
MAL
368 cleanup_vm(s2);
369 cleanup_vm(s1);
ddef6a0d
MAL
370
371 if (qemu_write_full(thread.pipe[1], "q", 1) != 1) {
372 g_error("qemu_write_full: %s", g_strerror(errno));
373 }
374
375 g_thread_join(thread.thread);
376
377 ivshmem_server_close(&server);
378 close(thread.pipe[1]);
379 close(thread.pipe[0]);
380}
381
382#define PCI_SLOT_HP 0x06
383
384static void test_ivshmem_hotplug(void)
385{
6ebb8d2a 386 QTestState *qts;
2bf25e07 387 const char *arch = qtest_get_arch();
ddef6a0d 388
6ebb8d2a 389 qts = qtest_init("-object memory-backend-ram,size=1M,id=mb1");
ddef6a0d 390
6ebb8d2a 391 global_qtest = qts; /* TODO: Get rid of global_qtest here */
5a0e75f0
TH
392 qtest_qmp_device_add("ivshmem-plain", "iv1",
393 "{'addr': %s, 'memdev': 'mb1'}",
394 stringify(PCI_SLOT_HP));
2bf25e07 395 if (strcmp(arch, "ppc64") != 0) {
6ebb8d2a 396 qpci_unplug_acpi_device_test(qts, "iv1", PCI_SLOT_HP);
2bf25e07 397 }
ddef6a0d 398
6ebb8d2a
TH
399 qtest_quit(qts);
400 global_qtest = NULL;
ddef6a0d
MAL
401}
402
d9453c93
MAL
403static void test_ivshmem_memdev(void)
404{
405 IVState state;
406
407 /* just for the sake of checking memory-backend property */
408 setup_vm_cmd(&state, "-object memory-backend-ram,size=1M,id=mb1"
5400c02b 409 " -device ivshmem-plain,memdev=mb1", false);
d9453c93 410
1760048a 411 cleanup_vm(&state);
d9453c93
MAL
412}
413
ddef6a0d
MAL
414static void cleanup(void)
415{
416 if (tmpshmem) {
417 munmap(tmpshmem, TMPSHMSIZE);
418 tmpshmem = NULL;
419 }
420
421 if (tmpshm) {
422 shm_unlink(tmpshm);
423 g_free(tmpshm);
424 tmpshm = NULL;
425 }
426
427 if (tmpserver) {
428 g_unlink(tmpserver);
429 g_free(tmpserver);
430 tmpserver = NULL;
431 }
432
433 if (tmpdir) {
434 g_rmdir(tmpdir);
435 tmpdir = NULL;
436 }
437}
438
439static void abrt_handler(void *data)
440{
441 cleanup();
442}
443
444static gchar *mktempshm(int size, int *fd)
445{
446 while (true) {
447 gchar *name;
448
449 name = g_strdup_printf("/qtest-%u-%u", getpid(), g_random_int());
450 *fd = shm_open(name, O_CREAT|O_RDWR|O_EXCL,
451 S_IRWXU|S_IRWXG|S_IRWXO);
452 if (*fd > 0) {
453 g_assert(ftruncate(*fd, size) == 0);
454 return name;
455 }
456
457 g_free(name);
458
459 if (errno != EEXIST) {
460 perror("shm_open");
461 return NULL;
462 }
463 }
bbfc2efe
AF
464}
465
466int main(int argc, char **argv)
467{
bbfc2efe 468 int ret, fd;
2bf25e07 469 const char *arch = qtest_get_arch();
ddef6a0d
MAL
470 gchar dir[] = "/tmp/ivshmem-test.XXXXXX";
471
bbfc2efe 472 g_test_init(&argc, &argv, NULL);
bbfc2efe 473
ddef6a0d
MAL
474 qtest_add_abrt_handler(abrt_handler, NULL);
475 /* shm */
476 tmpshm = mktempshm(TMPSHMSIZE, &fd);
477 if (!tmpshm) {
4848cb3d 478 goto out;
ddef6a0d
MAL
479 }
480 tmpshmem = mmap(0, TMPSHMSIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
481 g_assert(tmpshmem != MAP_FAILED);
482 /* server */
483 if (mkdtemp(dir) == NULL) {
484 g_error("mkdtemp: %s", g_strerror(errno));
485 }
486 tmpdir = dir;
487 tmpserver = g_strconcat(tmpdir, "/server", NULL);
bbfc2efe 488
ddef6a0d 489 qtest_add_func("/ivshmem/single", test_ivshmem_single);
ddef6a0d 490 qtest_add_func("/ivshmem/hotplug", test_ivshmem_hotplug);
d9453c93 491 qtest_add_func("/ivshmem/memdev", test_ivshmem_memdev);
2048a2a4
MAL
492 if (g_test_slow()) {
493 qtest_add_func("/ivshmem/pair", test_ivshmem_pair);
2bf25e07 494 if (strcmp(arch, "ppc64") != 0) {
5a0e75f0 495 qtest_add_func("/ivshmem/server", test_ivshmem_server);
2bf25e07 496 }
2048a2a4 497 }
bbfc2efe 498
4848cb3d 499out:
bbfc2efe 500 ret = g_test_run();
ddef6a0d 501 cleanup();
bbfc2efe
AF
502 return ret;
503}