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Commit | Line | Data |
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0824d6fc | 1 | /* |
1df912cf | 2 | * QEMU PC System Emulator |
0824d6fc | 3 | * |
1df912cf | 4 | * Copyright (c) 2003 Fabrice Bellard |
0824d6fc | 5 | * |
1df912cf FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
0824d6fc FB |
23 | */ |
24 | #include <stdlib.h> | |
25 | #include <stdio.h> | |
1df912cf | 26 | #include <stdarg.h> |
0824d6fc FB |
27 | #include <string.h> |
28 | #include <getopt.h> | |
29 | #include <inttypes.h> | |
30 | #include <unistd.h> | |
31 | #include <sys/mman.h> | |
32 | #include <fcntl.h> | |
33 | #include <signal.h> | |
34 | #include <time.h> | |
35 | #include <sys/time.h> | |
36 | #include <malloc.h> | |
37 | #include <termios.h> | |
38 | #include <sys/poll.h> | |
39 | #include <errno.h> | |
f1510b2c FB |
40 | #include <sys/wait.h> |
41 | ||
42 | #include <sys/ioctl.h> | |
43 | #include <sys/socket.h> | |
44 | #include <linux/if.h> | |
45 | #include <linux/if_tun.h> | |
0824d6fc | 46 | |
a20dd508 | 47 | #include "cpu.h" |
0824d6fc | 48 | #include "disas.h" |
fc01f7e7 FB |
49 | #include "thunk.h" |
50 | ||
51 | #include "vl.h" | |
0824d6fc | 52 | |
5a67135a | 53 | #define DEFAULT_NETWORK_SCRIPT "/etc/qemu-ifup" |
330d0414 FB |
54 | #define BIOS_FILENAME "bios.bin" |
55 | #define VGABIOS_FILENAME "vgabios.bin" | |
f1510b2c | 56 | |
0824d6fc | 57 | //#define DEBUG_UNUSED_IOPORT |
330d0414 | 58 | |
c9159e53 | 59 | //#define DEBUG_IRQ_LATENCY |
0824d6fc | 60 | |
330d0414 FB |
61 | /* output Bochs bios info messages */ |
62 | //#define DEBUG_BIOS | |
63 | ||
7dea1da4 FB |
64 | //#define DEBUG_CMOS |
65 | ||
330d0414 FB |
66 | /* debug PIC */ |
67 | //#define DEBUG_PIC | |
68 | ||
69 | /* debug NE2000 card */ | |
70 | //#define DEBUG_NE2000 | |
71 | ||
72 | /* debug PC keyboard */ | |
73 | //#define DEBUG_KBD | |
74 | ||
313aa567 FB |
75 | /* debug PC keyboard : only mouse */ |
76 | //#define DEBUG_MOUSE | |
77 | ||
7dea1da4 FB |
78 | //#define DEBUG_SERIAL |
79 | ||
7916e224 FB |
80 | #define PHYS_RAM_BASE 0xac000000 |
81 | #define PHYS_RAM_MAX_SIZE (256 * 1024 * 1024) | |
82 | ||
0824d6fc FB |
83 | #define KERNEL_LOAD_ADDR 0x00100000 |
84 | #define INITRD_LOAD_ADDR 0x00400000 | |
85 | #define KERNEL_PARAMS_ADDR 0x00090000 | |
86 | ||
313aa567 FB |
87 | #define GUI_REFRESH_INTERVAL 30 |
88 | ||
0824d6fc FB |
89 | /* from plex86 (BSD license) */ |
90 | struct __attribute__ ((packed)) linux_params { | |
91 | // For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h. | |
92 | // I just padded out the VESA parts, rather than define them. | |
93 | ||
94 | /* 0x000 */ uint8_t orig_x; | |
95 | /* 0x001 */ uint8_t orig_y; | |
96 | /* 0x002 */ uint16_t ext_mem_k; | |
97 | /* 0x004 */ uint16_t orig_video_page; | |
98 | /* 0x006 */ uint8_t orig_video_mode; | |
99 | /* 0x007 */ uint8_t orig_video_cols; | |
100 | /* 0x008 */ uint16_t unused1; | |
101 | /* 0x00a */ uint16_t orig_video_ega_bx; | |
102 | /* 0x00c */ uint16_t unused2; | |
103 | /* 0x00e */ uint8_t orig_video_lines; | |
104 | /* 0x00f */ uint8_t orig_video_isVGA; | |
105 | /* 0x010 */ uint16_t orig_video_points; | |
106 | /* 0x012 */ uint8_t pad0[0x20 - 0x12]; // VESA info. | |
107 | /* 0x020 */ uint16_t cl_magic; // Commandline magic number (0xA33F) | |
108 | /* 0x022 */ uint16_t cl_offset; // Commandline offset. Address of commandline | |
109 | // is calculated as 0x90000 + cl_offset, bu | |
110 | // only if cl_magic == 0xA33F. | |
111 | /* 0x024 */ uint8_t pad1[0x40 - 0x24]; // VESA info. | |
112 | ||
113 | /* 0x040 */ uint8_t apm_bios_info[20]; // struct apm_bios_info | |
114 | /* 0x054 */ uint8_t pad2[0x80 - 0x54]; | |
115 | ||
116 | // Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h. | |
117 | // Might be truncated? | |
118 | /* 0x080 */ uint8_t hd0_info[16]; // hd0-disk-parameter from intvector 0x41 | |
119 | /* 0x090 */ uint8_t hd1_info[16]; // hd1-disk-parameter from intvector 0x46 | |
120 | ||
121 | // System description table truncated to 16 bytes | |
122 | // From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c. | |
123 | /* 0x0a0 */ uint16_t sys_description_len; | |
124 | /* 0x0a2 */ uint8_t sys_description_table[14]; | |
125 | // [0] machine id | |
126 | // [1] machine submodel id | |
127 | // [2] BIOS revision | |
128 | // [3] bit1: MCA bus | |
129 | ||
130 | /* 0x0b0 */ uint8_t pad3[0x1e0 - 0xb0]; | |
131 | /* 0x1e0 */ uint32_t alt_mem_k; | |
132 | /* 0x1e4 */ uint8_t pad4[4]; | |
133 | /* 0x1e8 */ uint8_t e820map_entries; | |
134 | /* 0x1e9 */ uint8_t eddbuf_entries; // EDD_NR | |
135 | /* 0x1ea */ uint8_t pad5[0x1f1 - 0x1ea]; | |
136 | /* 0x1f1 */ uint8_t setup_sects; // size of setup.S, number of sectors | |
137 | /* 0x1f2 */ uint16_t mount_root_rdonly; // MOUNT_ROOT_RDONLY (if !=0) | |
138 | /* 0x1f4 */ uint16_t sys_size; // size of compressed kernel-part in the | |
139 | // (b)zImage-file (in 16 byte units, rounded up) | |
140 | /* 0x1f6 */ uint16_t swap_dev; // (unused AFAIK) | |
141 | /* 0x1f8 */ uint16_t ramdisk_flags; | |
142 | /* 0x1fa */ uint16_t vga_mode; // (old one) | |
143 | /* 0x1fc */ uint16_t orig_root_dev; // (high=Major, low=minor) | |
144 | /* 0x1fe */ uint8_t pad6[1]; | |
145 | /* 0x1ff */ uint8_t aux_device_info; | |
146 | /* 0x200 */ uint16_t jump_setup; // Jump to start of setup code, | |
147 | // aka "reserved" field. | |
148 | /* 0x202 */ uint8_t setup_signature[4]; // Signature for SETUP-header, ="HdrS" | |
149 | /* 0x206 */ uint16_t header_format_version; // Version number of header format; | |
150 | /* 0x208 */ uint8_t setup_S_temp0[8]; // Used by setup.S for communication with | |
151 | // boot loaders, look there. | |
152 | /* 0x210 */ uint8_t loader_type; | |
153 | // 0 for old one. | |
154 | // else 0xTV: | |
155 | // T=0: LILO | |
156 | // T=1: Loadlin | |
157 | // T=2: bootsect-loader | |
158 | // T=3: SYSLINUX | |
159 | // T=4: ETHERBOOT | |
160 | // V=version | |
161 | /* 0x211 */ uint8_t loadflags; | |
162 | // bit0 = 1: kernel is loaded high (bzImage) | |
163 | // bit7 = 1: Heap and pointer (see below) set by boot | |
164 | // loader. | |
165 | /* 0x212 */ uint16_t setup_S_temp1; | |
166 | /* 0x214 */ uint32_t kernel_start; | |
167 | /* 0x218 */ uint32_t initrd_start; | |
168 | /* 0x21c */ uint32_t initrd_size; | |
169 | /* 0x220 */ uint8_t setup_S_temp2[4]; | |
170 | /* 0x224 */ uint16_t setup_S_heap_end_pointer; | |
171 | /* 0x226 */ uint8_t pad7[0x2d0 - 0x226]; | |
172 | ||
173 | /* 0x2d0 : Int 15, ax=e820 memory map. */ | |
174 | // (linux/include/asm-i386/e820.h, 'struct e820entry') | |
175 | #define E820MAX 32 | |
176 | #define E820_RAM 1 | |
177 | #define E820_RESERVED 2 | |
178 | #define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */ | |
179 | #define E820_NVS 4 | |
180 | struct { | |
181 | uint64_t addr; | |
182 | uint64_t size; | |
183 | uint32_t type; | |
184 | } e820map[E820MAX]; | |
185 | ||
186 | /* 0x550 */ uint8_t pad8[0x600 - 0x550]; | |
187 | ||
188 | // BIOS Enhanced Disk Drive Services. | |
189 | // (From linux/include/asm-i386/edd.h, 'struct edd_info') | |
190 | // Each 'struct edd_info is 78 bytes, times a max of 6 structs in array. | |
191 | /* 0x600 */ uint8_t eddbuf[0x7d4 - 0x600]; | |
192 | ||
193 | /* 0x7d4 */ uint8_t pad9[0x800 - 0x7d4]; | |
194 | /* 0x800 */ uint8_t commandline[0x800]; | |
195 | ||
196 | /* 0x1000 */ | |
197 | uint64_t gdt_table[256]; | |
198 | uint64_t idt_table[48]; | |
199 | }; | |
200 | ||
201 | #define KERNEL_CS 0x10 | |
202 | #define KERNEL_DS 0x18 | |
203 | ||
7dea1da4 FB |
204 | /* XXX: use a two level table to limit memory usage */ |
205 | #define MAX_IOPORTS 65536 | |
0824d6fc | 206 | |
5a67135a | 207 | static const char *bios_dir = CONFIG_QEMU_SHAREDIR; |
0824d6fc FB |
208 | char phys_ram_file[1024]; |
209 | CPUX86State *global_env; | |
1df912cf | 210 | CPUX86State *cpu_single_env; |
fc01f7e7 FB |
211 | IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS]; |
212 | IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS]; | |
33e3963e | 213 | BlockDriverState *bs_table[MAX_DISKS]; |
313aa567 FB |
214 | int vga_ram_size; |
215 | static DisplayState display_state; | |
a20dd508 | 216 | int nographic; |
313aa567 FB |
217 | int term_inited; |
218 | int64_t ticks_per_sec; | |
36b486bb | 219 | int boot_device = 'c'; |
0824d6fc FB |
220 | |
221 | /***********************************************************/ | |
222 | /* x86 io ports */ | |
223 | ||
224 | uint32_t default_ioport_readb(CPUX86State *env, uint32_t address) | |
225 | { | |
226 | #ifdef DEBUG_UNUSED_IOPORT | |
227 | fprintf(stderr, "inb: port=0x%04x\n", address); | |
228 | #endif | |
fc01f7e7 | 229 | return 0xff; |
0824d6fc FB |
230 | } |
231 | ||
232 | void default_ioport_writeb(CPUX86State *env, uint32_t address, uint32_t data) | |
233 | { | |
234 | #ifdef DEBUG_UNUSED_IOPORT | |
235 | fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data); | |
236 | #endif | |
237 | } | |
238 | ||
239 | /* default is to make two byte accesses */ | |
240 | uint32_t default_ioport_readw(CPUX86State *env, uint32_t address) | |
241 | { | |
242 | uint32_t data; | |
330d0414 FB |
243 | data = ioport_read_table[0][address & (MAX_IOPORTS - 1)](env, address); |
244 | data |= ioport_read_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1) << 8; | |
0824d6fc FB |
245 | return data; |
246 | } | |
247 | ||
248 | void default_ioport_writew(CPUX86State *env, uint32_t address, uint32_t data) | |
249 | { | |
330d0414 FB |
250 | ioport_write_table[0][address & (MAX_IOPORTS - 1)](env, address, data & 0xff); |
251 | ioport_write_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1, (data >> 8) & 0xff); | |
0824d6fc FB |
252 | } |
253 | ||
fc01f7e7 | 254 | uint32_t default_ioport_readl(CPUX86State *env, uint32_t address) |
0824d6fc | 255 | { |
fc01f7e7 FB |
256 | #ifdef DEBUG_UNUSED_IOPORT |
257 | fprintf(stderr, "inl: port=0x%04x\n", address); | |
258 | #endif | |
259 | return 0xffffffff; | |
0824d6fc FB |
260 | } |
261 | ||
fc01f7e7 | 262 | void default_ioport_writel(CPUX86State *env, uint32_t address, uint32_t data) |
0824d6fc | 263 | { |
fc01f7e7 FB |
264 | #ifdef DEBUG_UNUSED_IOPORT |
265 | fprintf(stderr, "outl: port=0x%04x data=0x%02x\n", address, data); | |
266 | #endif | |
0824d6fc FB |
267 | } |
268 | ||
fc01f7e7 | 269 | void init_ioports(void) |
0824d6fc FB |
270 | { |
271 | int i; | |
272 | ||
fc01f7e7 FB |
273 | for(i = 0; i < MAX_IOPORTS; i++) { |
274 | ioport_read_table[0][i] = default_ioport_readb; | |
275 | ioport_write_table[0][i] = default_ioport_writeb; | |
276 | ioport_read_table[1][i] = default_ioport_readw; | |
277 | ioport_write_table[1][i] = default_ioport_writew; | |
278 | ioport_read_table[2][i] = default_ioport_readl; | |
279 | ioport_write_table[2][i] = default_ioport_writel; | |
280 | } | |
0824d6fc FB |
281 | } |
282 | ||
fc01f7e7 FB |
283 | /* size is the word size in byte */ |
284 | int register_ioport_read(int start, int length, IOPortReadFunc *func, int size) | |
f1510b2c | 285 | { |
fc01f7e7 | 286 | int i, bsize; |
f1510b2c | 287 | |
fc01f7e7 FB |
288 | if (size == 1) |
289 | bsize = 0; | |
290 | else if (size == 2) | |
291 | bsize = 1; | |
292 | else if (size == 4) | |
293 | bsize = 2; | |
294 | else | |
295 | return -1; | |
296 | for(i = start; i < start + length; i += size) | |
297 | ioport_read_table[bsize][i] = func; | |
f1510b2c FB |
298 | return 0; |
299 | } | |
300 | ||
fc01f7e7 FB |
301 | /* size is the word size in byte */ |
302 | int register_ioport_write(int start, int length, IOPortWriteFunc *func, int size) | |
f1510b2c | 303 | { |
fc01f7e7 | 304 | int i, bsize; |
f1510b2c | 305 | |
fc01f7e7 FB |
306 | if (size == 1) |
307 | bsize = 0; | |
308 | else if (size == 2) | |
309 | bsize = 1; | |
310 | else if (size == 4) | |
311 | bsize = 2; | |
312 | else | |
313 | return -1; | |
314 | for(i = start; i < start + length; i += size) | |
315 | ioport_write_table[bsize][i] = func; | |
f1510b2c FB |
316 | return 0; |
317 | } | |
318 | ||
0824d6fc FB |
319 | void pstrcpy(char *buf, int buf_size, const char *str) |
320 | { | |
321 | int c; | |
322 | char *q = buf; | |
323 | ||
324 | if (buf_size <= 0) | |
325 | return; | |
326 | ||
327 | for(;;) { | |
328 | c = *str++; | |
329 | if (c == 0 || q >= buf + buf_size - 1) | |
330 | break; | |
331 | *q++ = c; | |
332 | } | |
333 | *q = '\0'; | |
334 | } | |
335 | ||
336 | /* strcat and truncate. */ | |
337 | char *pstrcat(char *buf, int buf_size, const char *s) | |
338 | { | |
339 | int len; | |
340 | len = strlen(buf); | |
341 | if (len < buf_size) | |
342 | pstrcpy(buf + len, buf_size - len, s); | |
343 | return buf; | |
344 | } | |
345 | ||
346 | int load_kernel(const char *filename, uint8_t *addr) | |
347 | { | |
348 | int fd, size, setup_sects; | |
349 | uint8_t bootsect[512]; | |
350 | ||
351 | fd = open(filename, O_RDONLY); | |
352 | if (fd < 0) | |
353 | return -1; | |
354 | if (read(fd, bootsect, 512) != 512) | |
355 | goto fail; | |
356 | setup_sects = bootsect[0x1F1]; | |
357 | if (!setup_sects) | |
358 | setup_sects = 4; | |
359 | /* skip 16 bit setup code */ | |
360 | lseek(fd, (setup_sects + 1) * 512, SEEK_SET); | |
361 | size = read(fd, addr, 16 * 1024 * 1024); | |
362 | if (size < 0) | |
363 | goto fail; | |
364 | close(fd); | |
365 | return size; | |
366 | fail: | |
367 | close(fd); | |
368 | return -1; | |
369 | } | |
370 | ||
371 | /* return the size or -1 if error */ | |
372 | int load_image(const char *filename, uint8_t *addr) | |
373 | { | |
374 | int fd, size; | |
375 | fd = open(filename, O_RDONLY); | |
376 | if (fd < 0) | |
377 | return -1; | |
378 | size = lseek(fd, 0, SEEK_END); | |
379 | lseek(fd, 0, SEEK_SET); | |
380 | if (read(fd, addr, size) != size) { | |
381 | close(fd); | |
382 | return -1; | |
383 | } | |
384 | close(fd); | |
385 | return size; | |
386 | } | |
387 | ||
388 | void cpu_x86_outb(CPUX86State *env, int addr, int val) | |
389 | { | |
fc01f7e7 | 390 | ioport_write_table[0][addr & (MAX_IOPORTS - 1)](env, addr, val); |
0824d6fc FB |
391 | } |
392 | ||
393 | void cpu_x86_outw(CPUX86State *env, int addr, int val) | |
394 | { | |
fc01f7e7 | 395 | ioport_write_table[1][addr & (MAX_IOPORTS - 1)](env, addr, val); |
0824d6fc FB |
396 | } |
397 | ||
398 | void cpu_x86_outl(CPUX86State *env, int addr, int val) | |
399 | { | |
fc01f7e7 | 400 | ioport_write_table[2][addr & (MAX_IOPORTS - 1)](env, addr, val); |
0824d6fc FB |
401 | } |
402 | ||
403 | int cpu_x86_inb(CPUX86State *env, int addr) | |
404 | { | |
fc01f7e7 | 405 | return ioport_read_table[0][addr & (MAX_IOPORTS - 1)](env, addr); |
0824d6fc FB |
406 | } |
407 | ||
408 | int cpu_x86_inw(CPUX86State *env, int addr) | |
409 | { | |
fc01f7e7 | 410 | return ioport_read_table[1][addr & (MAX_IOPORTS - 1)](env, addr); |
0824d6fc FB |
411 | } |
412 | ||
413 | int cpu_x86_inl(CPUX86State *env, int addr) | |
414 | { | |
fc01f7e7 | 415 | return ioport_read_table[2][addr & (MAX_IOPORTS - 1)](env, addr); |
0824d6fc FB |
416 | } |
417 | ||
418 | /***********************************************************/ | |
419 | void ioport80_write(CPUX86State *env, uint32_t addr, uint32_t data) | |
420 | { | |
421 | } | |
422 | ||
423 | void hw_error(const char *fmt, ...) | |
424 | { | |
425 | va_list ap; | |
426 | ||
427 | va_start(ap, fmt); | |
428 | fprintf(stderr, "qemu: hardware error: "); | |
429 | vfprintf(stderr, fmt, ap); | |
430 | fprintf(stderr, "\n"); | |
431 | #ifdef TARGET_I386 | |
432 | cpu_x86_dump_state(global_env, stderr, X86_DUMP_FPU | X86_DUMP_CCOP); | |
433 | #endif | |
434 | va_end(ap); | |
435 | abort(); | |
436 | } | |
437 | ||
0824d6fc FB |
438 | /***********************************************************/ |
439 | /* cmos emulation */ | |
440 | ||
441 | #define RTC_SECONDS 0 | |
442 | #define RTC_SECONDS_ALARM 1 | |
443 | #define RTC_MINUTES 2 | |
444 | #define RTC_MINUTES_ALARM 3 | |
445 | #define RTC_HOURS 4 | |
446 | #define RTC_HOURS_ALARM 5 | |
447 | #define RTC_ALARM_DONT_CARE 0xC0 | |
448 | ||
449 | #define RTC_DAY_OF_WEEK 6 | |
450 | #define RTC_DAY_OF_MONTH 7 | |
451 | #define RTC_MONTH 8 | |
452 | #define RTC_YEAR 9 | |
453 | ||
454 | #define RTC_REG_A 10 | |
455 | #define RTC_REG_B 11 | |
456 | #define RTC_REG_C 12 | |
457 | #define RTC_REG_D 13 | |
458 | ||
459 | /* PC cmos mappings */ | |
460 | #define REG_EQUIPMENT_BYTE 0x14 | |
461 | ||
462 | uint8_t cmos_data[128]; | |
463 | uint8_t cmos_index; | |
464 | ||
465 | void cmos_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data) | |
466 | { | |
467 | if (addr == 0x70) { | |
468 | cmos_index = data & 0x7f; | |
7dea1da4 FB |
469 | } else { |
470 | #ifdef DEBUG_CMOS | |
471 | printf("cmos: write index=0x%02x val=0x%02x\n", | |
472 | cmos_index, data); | |
473 | #endif | |
474 | switch(addr) { | |
475 | case RTC_SECONDS_ALARM: | |
476 | case RTC_MINUTES_ALARM: | |
477 | case RTC_HOURS_ALARM: | |
478 | /* XXX: not supported */ | |
479 | cmos_data[cmos_index] = data; | |
480 | break; | |
481 | case RTC_SECONDS: | |
482 | case RTC_MINUTES: | |
483 | case RTC_HOURS: | |
484 | case RTC_DAY_OF_WEEK: | |
485 | case RTC_DAY_OF_MONTH: | |
486 | case RTC_MONTH: | |
487 | case RTC_YEAR: | |
488 | cmos_data[cmos_index] = data; | |
489 | break; | |
490 | case RTC_REG_A: | |
491 | case RTC_REG_B: | |
492 | cmos_data[cmos_index] = data; | |
493 | break; | |
494 | case RTC_REG_C: | |
495 | case RTC_REG_D: | |
496 | /* cannot write to them */ | |
497 | break; | |
498 | default: | |
499 | cmos_data[cmos_index] = data; | |
500 | break; | |
501 | } | |
0824d6fc FB |
502 | } |
503 | } | |
504 | ||
505 | uint32_t cmos_ioport_read(CPUX86State *env, uint32_t addr) | |
506 | { | |
507 | int ret; | |
508 | ||
509 | if (addr == 0x70) { | |
510 | return 0xff; | |
511 | } else { | |
0824d6fc | 512 | ret = cmos_data[cmos_index]; |
7dea1da4 FB |
513 | switch(cmos_index) { |
514 | case RTC_REG_A: | |
515 | /* toggle update-in-progress bit for Linux (same hack as | |
516 | plex86) */ | |
0824d6fc | 517 | cmos_data[RTC_REG_A] ^= 0x80; |
7dea1da4 FB |
518 | break; |
519 | case RTC_REG_C: | |
520 | pic_set_irq(8, 0); | |
0824d6fc | 521 | cmos_data[RTC_REG_C] = 0x00; |
7dea1da4 FB |
522 | break; |
523 | } | |
524 | #ifdef DEBUG_CMOS | |
525 | printf("cmos: read index=0x%02x val=0x%02x\n", | |
526 | cmos_index, ret); | |
527 | #endif | |
0824d6fc FB |
528 | return ret; |
529 | } | |
530 | } | |
531 | ||
532 | ||
533 | static inline int to_bcd(int a) | |
534 | { | |
535 | return ((a / 10) << 4) | (a % 10); | |
536 | } | |
537 | ||
538 | void cmos_init(void) | |
539 | { | |
540 | struct tm *tm; | |
541 | time_t ti; | |
330d0414 | 542 | int val; |
0824d6fc FB |
543 | |
544 | ti = time(NULL); | |
545 | tm = gmtime(&ti); | |
546 | cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec); | |
547 | cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min); | |
548 | cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour); | |
549 | cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday); | |
550 | cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday); | |
abd0aaff | 551 | cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon + 1); |
0824d6fc FB |
552 | cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100); |
553 | ||
554 | cmos_data[RTC_REG_A] = 0x26; | |
555 | cmos_data[RTC_REG_B] = 0x02; | |
556 | cmos_data[RTC_REG_C] = 0x00; | |
557 | cmos_data[RTC_REG_D] = 0x80; | |
558 | ||
330d0414 FB |
559 | /* various important CMOS locations needed by PC/Bochs bios */ |
560 | ||
0824d6fc | 561 | cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */ |
313aa567 | 562 | cmos_data[REG_EQUIPMENT_BYTE] |= 0x04; /* PS/2 mouse installed */ |
0824d6fc | 563 | |
330d0414 FB |
564 | /* memory size */ |
565 | val = (phys_ram_size / 1024) - 1024; | |
566 | if (val > 65535) | |
567 | val = 65535; | |
568 | cmos_data[0x17] = val; | |
569 | cmos_data[0x18] = val >> 8; | |
570 | cmos_data[0x30] = val; | |
571 | cmos_data[0x31] = val >> 8; | |
572 | ||
573 | val = (phys_ram_size / 65536) - ((16 * 1024 * 1024) / 65536); | |
574 | if (val > 65535) | |
575 | val = 65535; | |
576 | cmos_data[0x34] = val; | |
577 | cmos_data[0x35] = val >> 8; | |
578 | ||
36b486bb FB |
579 | switch(boot_device) { |
580 | case 'a': | |
581 | cmos_data[0x3d] = 0x01; /* floppy boot */ | |
582 | break; | |
583 | default: | |
584 | case 'c': | |
585 | cmos_data[0x3d] = 0x02; /* hard drive boot */ | |
586 | break; | |
587 | case 'd': | |
588 | cmos_data[0x3d] = 0x03; /* CD-ROM boot */ | |
589 | break; | |
590 | } | |
591 | ||
fc01f7e7 FB |
592 | register_ioport_write(0x70, 2, cmos_ioport_write, 1); |
593 | register_ioport_read(0x70, 2, cmos_ioport_read, 1); | |
0824d6fc FB |
594 | } |
595 | ||
596 | /***********************************************************/ | |
597 | /* 8259 pic emulation */ | |
598 | ||
599 | typedef struct PicState { | |
600 | uint8_t last_irr; /* edge detection */ | |
601 | uint8_t irr; /* interrupt request register */ | |
602 | uint8_t imr; /* interrupt mask register */ | |
603 | uint8_t isr; /* interrupt service register */ | |
604 | uint8_t priority_add; /* used to compute irq priority */ | |
605 | uint8_t irq_base; | |
606 | uint8_t read_reg_select; | |
607 | uint8_t special_mask; | |
608 | uint8_t init_state; | |
609 | uint8_t auto_eoi; | |
610 | uint8_t rotate_on_autoeoi; | |
611 | uint8_t init4; /* true if 4 byte init */ | |
612 | } PicState; | |
613 | ||
614 | /* 0 is master pic, 1 is slave pic */ | |
615 | PicState pics[2]; | |
616 | int pic_irq_requested; | |
617 | ||
618 | /* set irq level. If an edge is detected, then the IRR is set to 1 */ | |
619 | static inline void pic_set_irq1(PicState *s, int irq, int level) | |
620 | { | |
621 | int mask; | |
622 | mask = 1 << irq; | |
623 | if (level) { | |
624 | if ((s->last_irr & mask) == 0) | |
625 | s->irr |= mask; | |
626 | s->last_irr |= mask; | |
627 | } else { | |
628 | s->last_irr &= ~mask; | |
629 | } | |
630 | } | |
631 | ||
632 | static inline int get_priority(PicState *s, int mask) | |
633 | { | |
634 | int priority; | |
635 | if (mask == 0) | |
636 | return -1; | |
637 | priority = 7; | |
638 | while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) | |
639 | priority--; | |
640 | return priority; | |
641 | } | |
642 | ||
643 | /* return the pic wanted interrupt. return -1 if none */ | |
644 | static int pic_get_irq(PicState *s) | |
645 | { | |
646 | int mask, cur_priority, priority; | |
647 | ||
648 | mask = s->irr & ~s->imr; | |
649 | priority = get_priority(s, mask); | |
650 | if (priority < 0) | |
651 | return -1; | |
652 | /* compute current priority */ | |
653 | cur_priority = get_priority(s, s->isr); | |
654 | if (priority > cur_priority) { | |
655 | /* higher priority found: an irq should be generated */ | |
656 | return priority; | |
657 | } else { | |
658 | return -1; | |
659 | } | |
660 | } | |
661 | ||
c9159e53 FB |
662 | /* raise irq to CPU if necessary. must be called every time the active |
663 | irq may change */ | |
664 | static void pic_update_irq(void) | |
0824d6fc FB |
665 | { |
666 | int irq2, irq; | |
667 | ||
668 | /* first look at slave pic */ | |
669 | irq2 = pic_get_irq(&pics[1]); | |
670 | if (irq2 >= 0) { | |
671 | /* if irq request by slave pic, signal master PIC */ | |
672 | pic_set_irq1(&pics[0], 2, 1); | |
673 | pic_set_irq1(&pics[0], 2, 0); | |
674 | } | |
675 | /* look at requested irq */ | |
676 | irq = pic_get_irq(&pics[0]); | |
677 | if (irq >= 0) { | |
678 | if (irq == 2) { | |
679 | /* from slave pic */ | |
680 | pic_irq_requested = 8 + irq2; | |
681 | } else { | |
682 | /* from master pic */ | |
683 | pic_irq_requested = irq; | |
684 | } | |
c9159e53 | 685 | cpu_x86_interrupt(global_env, CPU_INTERRUPT_HARD); |
0824d6fc FB |
686 | } |
687 | } | |
688 | ||
c9159e53 FB |
689 | #ifdef DEBUG_IRQ_LATENCY |
690 | int64_t irq_time[16]; | |
691 | int64_t cpu_get_ticks(void); | |
692 | #endif | |
313aa567 | 693 | #if defined(DEBUG_PIC) |
b118d61e FB |
694 | int irq_level[16]; |
695 | #endif | |
c9159e53 FB |
696 | |
697 | void pic_set_irq(int irq, int level) | |
698 | { | |
313aa567 | 699 | #if defined(DEBUG_PIC) |
b118d61e FB |
700 | if (level != irq_level[irq]) { |
701 | printf("pic_set_irq: irq=%d level=%d\n", irq, level); | |
702 | irq_level[irq] = level; | |
703 | } | |
704 | #endif | |
c9159e53 FB |
705 | #ifdef DEBUG_IRQ_LATENCY |
706 | if (level) { | |
707 | irq_time[irq] = cpu_get_ticks(); | |
708 | } | |
709 | #endif | |
710 | pic_set_irq1(&pics[irq >> 3], irq & 7, level); | |
711 | pic_update_irq(); | |
712 | } | |
713 | ||
0824d6fc FB |
714 | int cpu_x86_get_pic_interrupt(CPUX86State *env) |
715 | { | |
716 | int irq, irq2, intno; | |
717 | ||
718 | /* signal the pic that the irq was acked by the CPU */ | |
719 | irq = pic_irq_requested; | |
c9159e53 | 720 | #ifdef DEBUG_IRQ_LATENCY |
313aa567 FB |
721 | printf("IRQ%d latency=%0.3fus\n", |
722 | irq, | |
723 | (double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec); | |
c9159e53 | 724 | #endif |
7dea1da4 | 725 | #if defined(DEBUG_PIC) |
b118d61e FB |
726 | printf("pic_interrupt: irq=%d\n", irq); |
727 | #endif | |
c9159e53 | 728 | |
0824d6fc FB |
729 | if (irq >= 8) { |
730 | irq2 = irq & 7; | |
731 | pics[1].isr |= (1 << irq2); | |
732 | pics[1].irr &= ~(1 << irq2); | |
733 | irq = 2; | |
734 | intno = pics[1].irq_base + irq2; | |
735 | } else { | |
736 | intno = pics[0].irq_base + irq; | |
737 | } | |
738 | pics[0].isr |= (1 << irq); | |
739 | pics[0].irr &= ~(1 << irq); | |
740 | return intno; | |
741 | } | |
742 | ||
743 | void pic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val) | |
744 | { | |
745 | PicState *s; | |
746 | int priority; | |
747 | ||
b118d61e FB |
748 | #ifdef DEBUG_PIC |
749 | printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val); | |
750 | #endif | |
0824d6fc FB |
751 | s = &pics[addr >> 7]; |
752 | addr &= 1; | |
753 | if (addr == 0) { | |
754 | if (val & 0x10) { | |
755 | /* init */ | |
756 | memset(s, 0, sizeof(PicState)); | |
757 | s->init_state = 1; | |
758 | s->init4 = val & 1; | |
759 | if (val & 0x02) | |
760 | hw_error("single mode not supported"); | |
761 | if (val & 0x08) | |
762 | hw_error("level sensitive irq not supported"); | |
763 | } else if (val & 0x08) { | |
764 | if (val & 0x02) | |
765 | s->read_reg_select = val & 1; | |
766 | if (val & 0x40) | |
767 | s->special_mask = (val >> 5) & 1; | |
768 | } else { | |
769 | switch(val) { | |
770 | case 0x00: | |
771 | case 0x80: | |
772 | s->rotate_on_autoeoi = val >> 7; | |
773 | break; | |
774 | case 0x20: /* end of interrupt */ | |
775 | case 0xa0: | |
776 | priority = get_priority(s, s->isr); | |
777 | if (priority >= 0) { | |
778 | s->isr &= ~(1 << ((priority + s->priority_add) & 7)); | |
779 | } | |
780 | if (val == 0xa0) | |
781 | s->priority_add = (s->priority_add + 1) & 7; | |
313aa567 | 782 | pic_update_irq(); |
0824d6fc FB |
783 | break; |
784 | case 0x60 ... 0x67: | |
785 | priority = val & 7; | |
786 | s->isr &= ~(1 << priority); | |
313aa567 | 787 | pic_update_irq(); |
0824d6fc FB |
788 | break; |
789 | case 0xc0 ... 0xc7: | |
790 | s->priority_add = (val + 1) & 7; | |
313aa567 | 791 | pic_update_irq(); |
0824d6fc FB |
792 | break; |
793 | case 0xe0 ... 0xe7: | |
794 | priority = val & 7; | |
795 | s->isr &= ~(1 << priority); | |
796 | s->priority_add = (priority + 1) & 7; | |
313aa567 | 797 | pic_update_irq(); |
0824d6fc FB |
798 | break; |
799 | } | |
800 | } | |
801 | } else { | |
802 | switch(s->init_state) { | |
803 | case 0: | |
804 | /* normal mode */ | |
805 | s->imr = val; | |
c9159e53 | 806 | pic_update_irq(); |
0824d6fc FB |
807 | break; |
808 | case 1: | |
809 | s->irq_base = val & 0xf8; | |
810 | s->init_state = 2; | |
811 | break; | |
812 | case 2: | |
813 | if (s->init4) { | |
814 | s->init_state = 3; | |
815 | } else { | |
816 | s->init_state = 0; | |
817 | } | |
818 | break; | |
819 | case 3: | |
820 | s->auto_eoi = (val >> 1) & 1; | |
821 | s->init_state = 0; | |
822 | break; | |
823 | } | |
824 | } | |
825 | } | |
826 | ||
b118d61e | 827 | uint32_t pic_ioport_read(CPUX86State *env, uint32_t addr1) |
0824d6fc FB |
828 | { |
829 | PicState *s; | |
b118d61e FB |
830 | unsigned int addr; |
831 | int ret; | |
832 | ||
833 | addr = addr1; | |
0824d6fc FB |
834 | s = &pics[addr >> 7]; |
835 | addr &= 1; | |
836 | if (addr == 0) { | |
837 | if (s->read_reg_select) | |
b118d61e | 838 | ret = s->isr; |
0824d6fc | 839 | else |
b118d61e | 840 | ret = s->irr; |
0824d6fc | 841 | } else { |
b118d61e | 842 | ret = s->imr; |
0824d6fc | 843 | } |
b118d61e FB |
844 | #ifdef DEBUG_PIC |
845 | printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret); | |
846 | #endif | |
847 | return ret; | |
0824d6fc FB |
848 | } |
849 | ||
850 | void pic_init(void) | |
851 | { | |
fc01f7e7 FB |
852 | register_ioport_write(0x20, 2, pic_ioport_write, 1); |
853 | register_ioport_read(0x20, 2, pic_ioport_read, 1); | |
854 | register_ioport_write(0xa0, 2, pic_ioport_write, 1); | |
855 | register_ioport_read(0xa0, 2, pic_ioport_read, 1); | |
0824d6fc FB |
856 | } |
857 | ||
858 | /***********************************************************/ | |
859 | /* 8253 PIT emulation */ | |
860 | ||
861 | #define PIT_FREQ 1193182 | |
862 | ||
863 | #define RW_STATE_LSB 0 | |
864 | #define RW_STATE_MSB 1 | |
865 | #define RW_STATE_WORD0 2 | |
866 | #define RW_STATE_WORD1 3 | |
867 | #define RW_STATE_LATCHED_WORD0 4 | |
868 | #define RW_STATE_LATCHED_WORD1 5 | |
869 | ||
870 | typedef struct PITChannelState { | |
87858c89 | 871 | int count; /* can be 65536 */ |
0824d6fc FB |
872 | uint16_t latched_count; |
873 | uint8_t rw_state; | |
874 | uint8_t mode; | |
875 | uint8_t bcd; /* not supported */ | |
876 | uint8_t gate; /* timer start */ | |
877 | int64_t count_load_time; | |
87858c89 | 878 | int64_t count_last_edge_check_time; |
0824d6fc FB |
879 | } PITChannelState; |
880 | ||
881 | PITChannelState pit_channels[3]; | |
882 | int speaker_data_on; | |
61a2ad53 | 883 | int dummy_refresh_clock; |
87858c89 | 884 | int pit_min_timer_count = 0; |
0824d6fc | 885 | |
34865134 FB |
886 | |
887 | #if defined(__powerpc__) | |
888 | ||
889 | static inline uint32_t get_tbl(void) | |
0824d6fc | 890 | { |
34865134 FB |
891 | uint32_t tbl; |
892 | asm volatile("mftb %0" : "=r" (tbl)); | |
893 | return tbl; | |
0824d6fc FB |
894 | } |
895 | ||
34865134 FB |
896 | static inline uint32_t get_tbu(void) |
897 | { | |
898 | uint32_t tbl; | |
899 | asm volatile("mftbu %0" : "=r" (tbl)); | |
900 | return tbl; | |
901 | } | |
902 | ||
903 | int64_t cpu_get_real_ticks(void) | |
904 | { | |
905 | uint32_t l, h, h1; | |
906 | /* NOTE: we test if wrapping has occurred */ | |
907 | do { | |
908 | h = get_tbu(); | |
909 | l = get_tbl(); | |
910 | h1 = get_tbu(); | |
911 | } while (h != h1); | |
912 | return ((int64_t)h << 32) | l; | |
913 | } | |
914 | ||
915 | #elif defined(__i386__) | |
916 | ||
917 | int64_t cpu_get_real_ticks(void) | |
0824d6fc FB |
918 | { |
919 | int64_t val; | |
920 | asm("rdtsc" : "=A" (val)); | |
921 | return val; | |
922 | } | |
923 | ||
34865134 FB |
924 | #else |
925 | #error unsupported CPU | |
926 | #endif | |
927 | ||
928 | static int64_t cpu_ticks_offset; | |
929 | static int64_t cpu_ticks_last; | |
930 | ||
931 | int64_t cpu_get_ticks(void) | |
932 | { | |
933 | return cpu_get_real_ticks() + cpu_ticks_offset; | |
934 | } | |
935 | ||
936 | /* enable cpu_get_ticks() */ | |
937 | void cpu_enable_ticks(void) | |
938 | { | |
939 | cpu_ticks_offset = cpu_ticks_last - cpu_get_real_ticks(); | |
940 | } | |
941 | ||
942 | /* disable cpu_get_ticks() : the clock is stopped. You must not call | |
943 | cpu_get_ticks() after that. */ | |
944 | void cpu_disable_ticks(void) | |
945 | { | |
946 | cpu_ticks_last = cpu_get_ticks(); | |
947 | } | |
948 | ||
949 | int64_t get_clock(void) | |
950 | { | |
951 | struct timeval tv; | |
952 | gettimeofday(&tv, NULL); | |
953 | return tv.tv_sec * 1000000LL + tv.tv_usec; | |
954 | } | |
955 | ||
0824d6fc FB |
956 | void cpu_calibrate_ticks(void) |
957 | { | |
958 | int64_t usec, ticks; | |
959 | ||
960 | usec = get_clock(); | |
961 | ticks = cpu_get_ticks(); | |
962 | usleep(50 * 1000); | |
963 | usec = get_clock() - usec; | |
964 | ticks = cpu_get_ticks() - ticks; | |
965 | ticks_per_sec = (ticks * 1000000LL + (usec >> 1)) / usec; | |
966 | } | |
967 | ||
87858c89 FB |
968 | /* compute with 96 bit intermediate result: (a*b)/c */ |
969 | static uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c) | |
970 | { | |
971 | union { | |
972 | uint64_t ll; | |
973 | struct { | |
974 | #ifdef WORDS_BIGENDIAN | |
975 | uint32_t high, low; | |
976 | #else | |
977 | uint32_t low, high; | |
978 | #endif | |
979 | } l; | |
980 | } u, res; | |
981 | uint64_t rl, rh; | |
982 | ||
983 | u.ll = a; | |
984 | rl = (uint64_t)u.l.low * (uint64_t)b; | |
985 | rh = (uint64_t)u.l.high * (uint64_t)b; | |
986 | rh += (rl >> 32); | |
987 | res.l.high = rh / c; | |
988 | res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c; | |
989 | return res.ll; | |
990 | } | |
991 | ||
0824d6fc FB |
992 | static int pit_get_count(PITChannelState *s) |
993 | { | |
87858c89 | 994 | uint64_t d; |
0824d6fc FB |
995 | int counter; |
996 | ||
87858c89 | 997 | d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec); |
0824d6fc FB |
998 | switch(s->mode) { |
999 | case 0: | |
1000 | case 1: | |
1001 | case 4: | |
1002 | case 5: | |
1003 | counter = (s->count - d) & 0xffff; | |
1004 | break; | |
1005 | default: | |
1006 | counter = s->count - (d % s->count); | |
1007 | break; | |
1008 | } | |
1009 | return counter; | |
1010 | } | |
1011 | ||
1012 | /* get pit output bit */ | |
1013 | static int pit_get_out(PITChannelState *s) | |
1014 | { | |
87858c89 | 1015 | uint64_t d; |
0824d6fc FB |
1016 | int out; |
1017 | ||
87858c89 | 1018 | d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec); |
0824d6fc FB |
1019 | switch(s->mode) { |
1020 | default: | |
1021 | case 0: | |
1022 | out = (d >= s->count); | |
1023 | break; | |
1024 | case 1: | |
1025 | out = (d < s->count); | |
1026 | break; | |
1027 | case 2: | |
1028 | if ((d % s->count) == 0 && d != 0) | |
1029 | out = 1; | |
1030 | else | |
1031 | out = 0; | |
1032 | break; | |
1033 | case 3: | |
1034 | out = (d % s->count) < (s->count >> 1); | |
1035 | break; | |
1036 | case 4: | |
1037 | case 5: | |
1038 | out = (d == s->count); | |
1039 | break; | |
1040 | } | |
1041 | return out; | |
1042 | } | |
1043 | ||
87858c89 FB |
1044 | /* get the number of 0 to 1 transitions we had since we call this |
1045 | function */ | |
1046 | /* XXX: maybe better to use ticks precision to avoid getting edges | |
1047 | twice if checks are done at very small intervals */ | |
1048 | static int pit_get_out_edges(PITChannelState *s) | |
1049 | { | |
1050 | uint64_t d1, d2; | |
1051 | int64_t ticks; | |
1052 | int ret, v; | |
1053 | ||
1054 | ticks = cpu_get_ticks(); | |
1055 | d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time, | |
1056 | PIT_FREQ, ticks_per_sec); | |
1057 | d2 = muldiv64(ticks - s->count_load_time, | |
1058 | PIT_FREQ, ticks_per_sec); | |
1059 | s->count_last_edge_check_time = ticks; | |
1060 | switch(s->mode) { | |
1061 | default: | |
1062 | case 0: | |
1063 | if (d1 < s->count && d2 >= s->count) | |
1064 | ret = 1; | |
1065 | else | |
1066 | ret = 0; | |
1067 | break; | |
1068 | case 1: | |
1069 | ret = 0; | |
1070 | break; | |
1071 | case 2: | |
1072 | d1 /= s->count; | |
1073 | d2 /= s->count; | |
1074 | ret = d2 - d1; | |
1075 | break; | |
1076 | case 3: | |
1077 | v = s->count - (s->count >> 1); | |
1078 | d1 = (d1 + v) / s->count; | |
1079 | d2 = (d2 + v) / s->count; | |
1080 | ret = d2 - d1; | |
1081 | break; | |
1082 | case 4: | |
1083 | case 5: | |
1084 | if (d1 < s->count && d2 >= s->count) | |
1085 | ret = 1; | |
1086 | else | |
1087 | ret = 0; | |
1088 | break; | |
1089 | } | |
1090 | return ret; | |
1091 | } | |
1092 | ||
1093 | static inline void pit_load_count(PITChannelState *s, int val) | |
1094 | { | |
1095 | if (val == 0) | |
1096 | val = 0x10000; | |
1097 | s->count_load_time = cpu_get_ticks(); | |
1098 | s->count_last_edge_check_time = s->count_load_time; | |
1099 | s->count = val; | |
1100 | if (s == &pit_channels[0] && val <= pit_min_timer_count) { | |
1101 | fprintf(stderr, | |
36b486bb | 1102 | "\nWARNING: qemu: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.5.xx Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n", |
87858c89 FB |
1103 | PIT_FREQ / pit_min_timer_count); |
1104 | } | |
1105 | } | |
1106 | ||
0824d6fc FB |
1107 | void pit_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val) |
1108 | { | |
1109 | int channel, access; | |
1110 | PITChannelState *s; | |
87858c89 | 1111 | |
0824d6fc FB |
1112 | addr &= 3; |
1113 | if (addr == 3) { | |
1114 | channel = val >> 6; | |
1115 | if (channel == 3) | |
1116 | return; | |
1117 | s = &pit_channels[channel]; | |
1118 | access = (val >> 4) & 3; | |
1119 | switch(access) { | |
1120 | case 0: | |
1121 | s->latched_count = pit_get_count(s); | |
1122 | s->rw_state = RW_STATE_LATCHED_WORD0; | |
1123 | break; | |
1124 | default: | |
87858c89 FB |
1125 | s->mode = (val >> 1) & 7; |
1126 | s->bcd = val & 1; | |
0824d6fc FB |
1127 | s->rw_state = access - 1 + RW_STATE_LSB; |
1128 | break; | |
1129 | } | |
0824d6fc FB |
1130 | } else { |
1131 | s = &pit_channels[addr]; | |
1132 | switch(s->rw_state) { | |
1133 | case RW_STATE_LSB: | |
87858c89 | 1134 | pit_load_count(s, val); |
0824d6fc FB |
1135 | break; |
1136 | case RW_STATE_MSB: | |
87858c89 | 1137 | pit_load_count(s, val << 8); |
0824d6fc FB |
1138 | break; |
1139 | case RW_STATE_WORD0: | |
1140 | case RW_STATE_WORD1: | |
1141 | if (s->rw_state & 1) { | |
87858c89 | 1142 | pit_load_count(s, (s->latched_count & 0xff) | (val << 8)); |
0824d6fc FB |
1143 | } else { |
1144 | s->latched_count = val; | |
1145 | } | |
1146 | s->rw_state ^= 1; | |
1147 | break; | |
1148 | } | |
1149 | } | |
1150 | } | |
1151 | ||
1152 | uint32_t pit_ioport_read(CPUX86State *env, uint32_t addr) | |
1153 | { | |
1154 | int ret, count; | |
1155 | PITChannelState *s; | |
1156 | ||
1157 | addr &= 3; | |
1158 | s = &pit_channels[addr]; | |
1159 | switch(s->rw_state) { | |
1160 | case RW_STATE_LSB: | |
1161 | case RW_STATE_MSB: | |
1162 | case RW_STATE_WORD0: | |
1163 | case RW_STATE_WORD1: | |
1164 | count = pit_get_count(s); | |
1165 | if (s->rw_state & 1) | |
1166 | ret = (count >> 8) & 0xff; | |
1167 | else | |
1168 | ret = count & 0xff; | |
1169 | if (s->rw_state & 2) | |
1170 | s->rw_state ^= 1; | |
1171 | break; | |
1172 | default: | |
1173 | case RW_STATE_LATCHED_WORD0: | |
1174 | case RW_STATE_LATCHED_WORD1: | |
1175 | if (s->rw_state & 1) | |
1176 | ret = s->latched_count >> 8; | |
1177 | else | |
1178 | ret = s->latched_count & 0xff; | |
1179 | s->rw_state ^= 1; | |
1180 | break; | |
1181 | } | |
1182 | return ret; | |
1183 | } | |
1184 | ||
1185 | void speaker_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val) | |
1186 | { | |
1187 | speaker_data_on = (val >> 1) & 1; | |
1188 | pit_channels[2].gate = val & 1; | |
1189 | } | |
1190 | ||
1191 | uint32_t speaker_ioport_read(CPUX86State *env, uint32_t addr) | |
1192 | { | |
1193 | int out; | |
1194 | out = pit_get_out(&pit_channels[2]); | |
61a2ad53 FB |
1195 | dummy_refresh_clock ^= 1; |
1196 | return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5) | | |
1197 | (dummy_refresh_clock << 4); | |
0824d6fc FB |
1198 | } |
1199 | ||
1200 | void pit_init(void) | |
1201 | { | |
87858c89 FB |
1202 | PITChannelState *s; |
1203 | int i; | |
1204 | ||
1205 | cpu_calibrate_ticks(); | |
1206 | ||
1207 | for(i = 0;i < 3; i++) { | |
1208 | s = &pit_channels[i]; | |
1209 | s->mode = 3; | |
1210 | s->gate = (i != 2); | |
1211 | pit_load_count(s, 0); | |
1212 | } | |
1213 | ||
fc01f7e7 FB |
1214 | register_ioport_write(0x40, 4, pit_ioport_write, 1); |
1215 | register_ioport_read(0x40, 3, pit_ioport_read, 1); | |
0824d6fc | 1216 | |
fc01f7e7 FB |
1217 | register_ioport_read(0x61, 1, speaker_ioport_read, 1); |
1218 | register_ioport_write(0x61, 1, speaker_ioport_write, 1); | |
0824d6fc FB |
1219 | } |
1220 | ||
1221 | /***********************************************************/ | |
1222 | /* serial port emulation */ | |
1223 | ||
1224 | #define UART_IRQ 4 | |
1225 | ||
1226 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ | |
1227 | ||
1228 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ | |
1229 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ | |
1230 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ | |
1231 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ | |
1232 | ||
1233 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ | |
1234 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ | |
1235 | ||
1236 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ | |
1237 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ | |
1238 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ | |
1239 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ | |
1240 | ||
7dea1da4 FB |
1241 | /* |
1242 | * These are the definitions for the Modem Control Register | |
1243 | */ | |
1244 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ | |
1245 | #define UART_MCR_OUT2 0x08 /* Out2 complement */ | |
1246 | #define UART_MCR_OUT1 0x04 /* Out1 complement */ | |
1247 | #define UART_MCR_RTS 0x02 /* RTS complement */ | |
1248 | #define UART_MCR_DTR 0x01 /* DTR complement */ | |
1249 | ||
1250 | /* | |
1251 | * These are the definitions for the Modem Status Register | |
1252 | */ | |
1253 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ | |
1254 | #define UART_MSR_RI 0x40 /* Ring Indicator */ | |
1255 | #define UART_MSR_DSR 0x20 /* Data Set Ready */ | |
1256 | #define UART_MSR_CTS 0x10 /* Clear to Send */ | |
1257 | #define UART_MSR_DDCD 0x08 /* Delta DCD */ | |
1258 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ | |
1259 | #define UART_MSR_DDSR 0x02 /* Delta DSR */ | |
1260 | #define UART_MSR_DCTS 0x01 /* Delta CTS */ | |
1261 | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ | |
1262 | ||
0824d6fc FB |
1263 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
1264 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ | |
1265 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ | |
1266 | #define UART_LSR_FE 0x08 /* Frame error indicator */ | |
1267 | #define UART_LSR_PE 0x04 /* Parity error indicator */ | |
1268 | #define UART_LSR_OE 0x02 /* Overrun error indicator */ | |
1269 | #define UART_LSR_DR 0x01 /* Receiver data ready */ | |
1270 | ||
1271 | typedef struct SerialState { | |
1272 | uint8_t divider; | |
1273 | uint8_t rbr; /* receive register */ | |
1274 | uint8_t ier; | |
1275 | uint8_t iir; /* read only */ | |
1276 | uint8_t lcr; | |
1277 | uint8_t mcr; | |
1278 | uint8_t lsr; /* read only */ | |
1279 | uint8_t msr; | |
1280 | uint8_t scr; | |
7dea1da4 FB |
1281 | /* NOTE: this hidden state is necessary for tx irq generation as |
1282 | it can be reset while reading iir */ | |
1283 | int thr_ipending; | |
0824d6fc FB |
1284 | } SerialState; |
1285 | ||
1286 | SerialState serial_ports[1]; | |
1287 | ||
1288 | void serial_update_irq(void) | |
1289 | { | |
1290 | SerialState *s = &serial_ports[0]; | |
1291 | ||
1292 | if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) { | |
1293 | s->iir = UART_IIR_RDI; | |
7dea1da4 | 1294 | } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) { |
0824d6fc FB |
1295 | s->iir = UART_IIR_THRI; |
1296 | } else { | |
1297 | s->iir = UART_IIR_NO_INT; | |
1298 | } | |
1299 | if (s->iir != UART_IIR_NO_INT) { | |
1300 | pic_set_irq(UART_IRQ, 1); | |
1301 | } else { | |
1302 | pic_set_irq(UART_IRQ, 0); | |
1303 | } | |
1304 | } | |
1305 | ||
1306 | void serial_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val) | |
1307 | { | |
1308 | SerialState *s = &serial_ports[0]; | |
1309 | unsigned char ch; | |
1310 | int ret; | |
1311 | ||
1312 | addr &= 7; | |
7dea1da4 FB |
1313 | #ifdef DEBUG_SERIAL |
1314 | printf("serial: write addr=0x%02x val=0x%02x\n", addr, val); | |
1315 | #endif | |
0824d6fc FB |
1316 | switch(addr) { |
1317 | default: | |
1318 | case 0: | |
1319 | if (s->lcr & UART_LCR_DLAB) { | |
1320 | s->divider = (s->divider & 0xff00) | val; | |
1321 | } else { | |
7dea1da4 | 1322 | s->thr_ipending = 0; |
0824d6fc FB |
1323 | s->lsr &= ~UART_LSR_THRE; |
1324 | serial_update_irq(); | |
1325 | ||
1326 | ch = val; | |
1327 | do { | |
1328 | ret = write(1, &ch, 1); | |
1329 | } while (ret != 1); | |
7dea1da4 | 1330 | s->thr_ipending = 1; |
0824d6fc FB |
1331 | s->lsr |= UART_LSR_THRE; |
1332 | s->lsr |= UART_LSR_TEMT; | |
1333 | serial_update_irq(); | |
1334 | } | |
1335 | break; | |
1336 | case 1: | |
1337 | if (s->lcr & UART_LCR_DLAB) { | |
1338 | s->divider = (s->divider & 0x00ff) | (val << 8); | |
1339 | } else { | |
1340 | s->ier = val; | |
1341 | serial_update_irq(); | |
1342 | } | |
1343 | break; | |
1344 | case 2: | |
1345 | break; | |
1346 | case 3: | |
1347 | s->lcr = val; | |
1348 | break; | |
1349 | case 4: | |
1350 | s->mcr = val; | |
1351 | break; | |
1352 | case 5: | |
1353 | break; | |
1354 | case 6: | |
1355 | s->msr = val; | |
1356 | break; | |
1357 | case 7: | |
1358 | s->scr = val; | |
1359 | break; | |
1360 | } | |
1361 | } | |
1362 | ||
1363 | uint32_t serial_ioport_read(CPUX86State *env, uint32_t addr) | |
1364 | { | |
1365 | SerialState *s = &serial_ports[0]; | |
1366 | uint32_t ret; | |
1367 | ||
1368 | addr &= 7; | |
1369 | switch(addr) { | |
1370 | default: | |
1371 | case 0: | |
1372 | if (s->lcr & UART_LCR_DLAB) { | |
1373 | ret = s->divider & 0xff; | |
1374 | } else { | |
1375 | ret = s->rbr; | |
1376 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); | |
1377 | serial_update_irq(); | |
1378 | } | |
1379 | break; | |
1380 | case 1: | |
1381 | if (s->lcr & UART_LCR_DLAB) { | |
1382 | ret = (s->divider >> 8) & 0xff; | |
1383 | } else { | |
1384 | ret = s->ier; | |
1385 | } | |
1386 | break; | |
1387 | case 2: | |
1388 | ret = s->iir; | |
7dea1da4 FB |
1389 | /* reset THR pending bit */ |
1390 | if ((ret & 0x7) == UART_IIR_THRI) | |
1391 | s->thr_ipending = 0; | |
1392 | serial_update_irq(); | |
0824d6fc FB |
1393 | break; |
1394 | case 3: | |
1395 | ret = s->lcr; | |
1396 | break; | |
1397 | case 4: | |
1398 | ret = s->mcr; | |
1399 | break; | |
1400 | case 5: | |
1401 | ret = s->lsr; | |
1402 | break; | |
1403 | case 6: | |
7dea1da4 FB |
1404 | if (s->mcr & UART_MCR_LOOP) { |
1405 | /* in loopback, the modem output pins are connected to the | |
1406 | inputs */ | |
1407 | ret = (s->mcr & 0x0c) << 4; | |
1408 | ret |= (s->mcr & 0x02) << 3; | |
1409 | ret |= (s->mcr & 0x01) << 5; | |
1410 | } else { | |
1411 | ret = s->msr; | |
1412 | } | |
0824d6fc FB |
1413 | break; |
1414 | case 7: | |
1415 | ret = s->scr; | |
1416 | break; | |
1417 | } | |
7dea1da4 FB |
1418 | #ifdef DEBUG_SERIAL |
1419 | printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret); | |
1420 | #endif | |
0824d6fc FB |
1421 | return ret; |
1422 | } | |
1423 | ||
1424 | #define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */ | |
1425 | static int term_got_escape; | |
1426 | ||
1427 | void term_print_help(void) | |
1428 | { | |
1429 | printf("\n" | |
1430 | "C-a h print this help\n" | |
1431 | "C-a x exit emulatior\n" | |
33e3963e | 1432 | "C-a s save disk data back to file (if -snapshot)\n" |
0824d6fc FB |
1433 | "C-a b send break (magic sysrq)\n" |
1434 | "C-a C-a send C-a\n" | |
1435 | ); | |
1436 | } | |
1437 | ||
1438 | /* called when a char is received */ | |
1439 | void serial_received_byte(SerialState *s, int ch) | |
1440 | { | |
1441 | if (term_got_escape) { | |
1442 | term_got_escape = 0; | |
1443 | switch(ch) { | |
1444 | case 'h': | |
1445 | term_print_help(); | |
1446 | break; | |
1447 | case 'x': | |
1448 | exit(0); | |
1449 | break; | |
33e3963e FB |
1450 | case 's': |
1451 | { | |
1452 | int i; | |
1453 | for (i = 0; i < MAX_DISKS; i++) { | |
1454 | if (bs_table[i]) | |
1455 | bdrv_commit(bs_table[i]); | |
1456 | } | |
1457 | } | |
1458 | break; | |
0824d6fc FB |
1459 | case 'b': |
1460 | /* send break */ | |
1461 | s->rbr = 0; | |
1462 | s->lsr |= UART_LSR_BI | UART_LSR_DR; | |
1463 | serial_update_irq(); | |
1464 | break; | |
1465 | case TERM_ESCAPE: | |
1466 | goto send_char; | |
1467 | } | |
1468 | } else if (ch == TERM_ESCAPE) { | |
1469 | term_got_escape = 1; | |
1470 | } else { | |
1471 | send_char: | |
1472 | s->rbr = ch; | |
1473 | s->lsr |= UART_LSR_DR; | |
1474 | serial_update_irq(); | |
1475 | } | |
1476 | } | |
1477 | ||
0824d6fc FB |
1478 | void serial_init(void) |
1479 | { | |
1480 | SerialState *s = &serial_ports[0]; | |
1481 | ||
1482 | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; | |
7dea1da4 FB |
1483 | s->iir = UART_IIR_NO_INT; |
1484 | ||
fc01f7e7 FB |
1485 | register_ioport_write(0x3f8, 8, serial_ioport_write, 1); |
1486 | register_ioport_read(0x3f8, 8, serial_ioport_read, 1); | |
0824d6fc FB |
1487 | } |
1488 | ||
f1510b2c FB |
1489 | /***********************************************************/ |
1490 | /* ne2000 emulation */ | |
1491 | ||
f1510b2c FB |
1492 | #define NE2000_IOPORT 0x300 |
1493 | #define NE2000_IRQ 9 | |
1494 | ||
1495 | #define MAX_ETH_FRAME_SIZE 1514 | |
1496 | ||
1497 | #define E8390_CMD 0x00 /* The command register (for all pages) */ | |
1498 | /* Page 0 register offsets. */ | |
1499 | #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ | |
1500 | #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ | |
1501 | #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ | |
1502 | #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ | |
1503 | #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ | |
1504 | #define EN0_TSR 0x04 /* Transmit status reg RD */ | |
1505 | #define EN0_TPSR 0x04 /* Transmit starting page WR */ | |
1506 | #define EN0_NCR 0x05 /* Number of collision reg RD */ | |
1507 | #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ | |
1508 | #define EN0_FIFO 0x06 /* FIFO RD */ | |
1509 | #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ | |
1510 | #define EN0_ISR 0x07 /* Interrupt status reg RD WR */ | |
1511 | #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ | |
1512 | #define EN0_RSARLO 0x08 /* Remote start address reg 0 */ | |
1513 | #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ | |
1514 | #define EN0_RSARHI 0x09 /* Remote start address reg 1 */ | |
1515 | #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ | |
1516 | #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ | |
1517 | #define EN0_RSR 0x0c /* rx status reg RD */ | |
1518 | #define EN0_RXCR 0x0c /* RX configuration reg WR */ | |
1519 | #define EN0_TXCR 0x0d /* TX configuration reg WR */ | |
1520 | #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ | |
1521 | #define EN0_DCFG 0x0e /* Data configuration reg WR */ | |
1522 | #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ | |
1523 | #define EN0_IMR 0x0f /* Interrupt mask reg WR */ | |
1524 | #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ | |
1525 | ||
1526 | #define EN1_PHYS 0x11 | |
1527 | #define EN1_CURPAG 0x17 | |
1528 | #define EN1_MULT 0x18 | |
1529 | ||
1530 | /* Register accessed at EN_CMD, the 8390 base addr. */ | |
1531 | #define E8390_STOP 0x01 /* Stop and reset the chip */ | |
1532 | #define E8390_START 0x02 /* Start the chip, clear reset */ | |
1533 | #define E8390_TRANS 0x04 /* Transmit a frame */ | |
1534 | #define E8390_RREAD 0x08 /* Remote read */ | |
1535 | #define E8390_RWRITE 0x10 /* Remote write */ | |
1536 | #define E8390_NODMA 0x20 /* Remote DMA */ | |
1537 | #define E8390_PAGE0 0x00 /* Select page chip registers */ | |
1538 | #define E8390_PAGE1 0x40 /* using the two high-order bits */ | |
1539 | #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ | |
1540 | ||
1541 | /* Bits in EN0_ISR - Interrupt status register */ | |
1542 | #define ENISR_RX 0x01 /* Receiver, no error */ | |
1543 | #define ENISR_TX 0x02 /* Transmitter, no error */ | |
1544 | #define ENISR_RX_ERR 0x04 /* Receiver, with error */ | |
1545 | #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ | |
1546 | #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ | |
1547 | #define ENISR_COUNTERS 0x20 /* Counters need emptying */ | |
1548 | #define ENISR_RDC 0x40 /* remote dma complete */ | |
1549 | #define ENISR_RESET 0x80 /* Reset completed */ | |
1550 | #define ENISR_ALL 0x3f /* Interrupts we will enable */ | |
1551 | ||
1552 | /* Bits in received packet status byte and EN0_RSR*/ | |
1553 | #define ENRSR_RXOK 0x01 /* Received a good packet */ | |
1554 | #define ENRSR_CRC 0x02 /* CRC error */ | |
1555 | #define ENRSR_FAE 0x04 /* frame alignment error */ | |
1556 | #define ENRSR_FO 0x08 /* FIFO overrun */ | |
1557 | #define ENRSR_MPA 0x10 /* missed pkt */ | |
1558 | #define ENRSR_PHY 0x20 /* physical/multicast address */ | |
1559 | #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ | |
1560 | #define ENRSR_DEF 0x80 /* deferring */ | |
1561 | ||
1562 | /* Transmitted packet status, EN0_TSR. */ | |
1563 | #define ENTSR_PTX 0x01 /* Packet transmitted without error */ | |
1564 | #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ | |
1565 | #define ENTSR_COL 0x04 /* The transmit collided at least once. */ | |
1566 | #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ | |
1567 | #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ | |
1568 | #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ | |
1569 | #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ | |
1570 | #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ | |
1571 | ||
1572 | #define NE2000_MEM_SIZE 32768 | |
1573 | ||
1574 | typedef struct NE2000State { | |
1575 | uint8_t cmd; | |
1576 | uint32_t start; | |
1577 | uint32_t stop; | |
1578 | uint8_t boundary; | |
1579 | uint8_t tsr; | |
1580 | uint8_t tpsr; | |
1581 | uint16_t tcnt; | |
1582 | uint16_t rcnt; | |
1583 | uint32_t rsar; | |
1584 | uint8_t isr; | |
1585 | uint8_t dcfg; | |
1586 | uint8_t imr; | |
1587 | uint8_t phys[6]; /* mac address */ | |
1588 | uint8_t curpag; | |
1589 | uint8_t mult[8]; /* multicast mask array */ | |
1590 | uint8_t mem[NE2000_MEM_SIZE]; | |
1591 | } NE2000State; | |
1592 | ||
1593 | NE2000State ne2000_state; | |
1594 | int net_fd = -1; | |
1595 | char network_script[1024]; | |
1596 | ||
1597 | void ne2000_reset(void) | |
1598 | { | |
1599 | NE2000State *s = &ne2000_state; | |
1600 | int i; | |
1601 | ||
1602 | s->isr = ENISR_RESET; | |
1603 | s->mem[0] = 0x52; | |
1604 | s->mem[1] = 0x54; | |
1605 | s->mem[2] = 0x00; | |
1606 | s->mem[3] = 0x12; | |
1607 | s->mem[4] = 0x34; | |
1608 | s->mem[5] = 0x56; | |
1609 | s->mem[14] = 0x57; | |
1610 | s->mem[15] = 0x57; | |
1611 | ||
1612 | /* duplicate prom data */ | |
1613 | for(i = 15;i >= 0; i--) { | |
1614 | s->mem[2 * i] = s->mem[i]; | |
1615 | s->mem[2 * i + 1] = s->mem[i]; | |
1616 | } | |
1617 | } | |
1618 | ||
1619 | void ne2000_update_irq(NE2000State *s) | |
1620 | { | |
1621 | int isr; | |
1622 | isr = s->isr & s->imr; | |
1623 | if (isr) | |
1624 | pic_set_irq(NE2000_IRQ, 1); | |
1625 | else | |
1626 | pic_set_irq(NE2000_IRQ, 0); | |
1627 | } | |
1628 | ||
1629 | int net_init(void) | |
1630 | { | |
1631 | struct ifreq ifr; | |
1632 | int fd, ret, pid, status; | |
1633 | ||
1634 | fd = open("/dev/net/tun", O_RDWR); | |
1635 | if (fd < 0) { | |
1636 | fprintf(stderr, "warning: could not open /dev/net/tun: no virtual network emulation\n"); | |
1637 | return -1; | |
1638 | } | |
1639 | memset(&ifr, 0, sizeof(ifr)); | |
1640 | ifr.ifr_flags = IFF_TAP | IFF_NO_PI; | |
1641 | pstrcpy(ifr.ifr_name, IFNAMSIZ, "tun%d"); | |
1642 | ret = ioctl(fd, TUNSETIFF, (void *) &ifr); | |
1643 | if (ret != 0) { | |
1644 | fprintf(stderr, "warning: could not configure /dev/net/tun: no virtual network emulation\n"); | |
1645 | close(fd); | |
1646 | return -1; | |
1647 | } | |
fc01f7e7 | 1648 | printf("Connected to host network interface: %s\n", ifr.ifr_name); |
f1510b2c FB |
1649 | fcntl(fd, F_SETFL, O_NONBLOCK); |
1650 | net_fd = fd; | |
1651 | ||
1652 | /* try to launch network init script */ | |
1653 | pid = fork(); | |
1654 | if (pid >= 0) { | |
1655 | if (pid == 0) { | |
1656 | execl(network_script, network_script, ifr.ifr_name, NULL); | |
1657 | exit(1); | |
1658 | } | |
1659 | while (waitpid(pid, &status, 0) != pid); | |
1660 | if (!WIFEXITED(status) || | |
1661 | WEXITSTATUS(status) != 0) { | |
1662 | fprintf(stderr, "%s: could not launch network script for '%s'\n", | |
1663 | network_script, ifr.ifr_name); | |
1664 | } | |
1665 | } | |
1666 | return 0; | |
1667 | } | |
1668 | ||
1669 | void net_send_packet(NE2000State *s, const uint8_t *buf, int size) | |
1670 | { | |
1671 | #ifdef DEBUG_NE2000 | |
1672 | printf("NE2000: sending packet size=%d\n", size); | |
1673 | #endif | |
1674 | write(net_fd, buf, size); | |
1675 | } | |
1676 | ||
1677 | /* return true if the NE2000 can receive more data */ | |
1678 | int ne2000_can_receive(NE2000State *s) | |
1679 | { | |
1680 | int avail, index, boundary; | |
1681 | ||
1682 | if (s->cmd & E8390_STOP) | |
1683 | return 0; | |
1684 | index = s->curpag << 8; | |
1685 | boundary = s->boundary << 8; | |
1686 | if (index < boundary) | |
1687 | avail = boundary - index; | |
1688 | else | |
1689 | avail = (s->stop - s->start) - (index - boundary); | |
1690 | if (avail < (MAX_ETH_FRAME_SIZE + 4)) | |
1691 | return 0; | |
1692 | return 1; | |
1693 | } | |
1694 | ||
1695 | void ne2000_receive(NE2000State *s, uint8_t *buf, int size) | |
1696 | { | |
1697 | uint8_t *p; | |
1698 | int total_len, next, avail, len, index; | |
1699 | ||
1700 | #if defined(DEBUG_NE2000) | |
1701 | printf("NE2000: received len=%d\n", size); | |
1702 | #endif | |
1703 | ||
1704 | index = s->curpag << 8; | |
1705 | /* 4 bytes for header */ | |
1706 | total_len = size + 4; | |
1707 | /* address for next packet (4 bytes for CRC) */ | |
1708 | next = index + ((total_len + 4 + 255) & ~0xff); | |
1709 | if (next >= s->stop) | |
1710 | next -= (s->stop - s->start); | |
1711 | /* prepare packet header */ | |
1712 | p = s->mem + index; | |
1713 | p[0] = ENRSR_RXOK; /* receive status */ | |
1714 | p[1] = next >> 8; | |
1715 | p[2] = total_len; | |
1716 | p[3] = total_len >> 8; | |
1717 | index += 4; | |
1718 | ||
1719 | /* write packet data */ | |
1720 | while (size > 0) { | |
1721 | avail = s->stop - index; | |
1722 | len = size; | |
1723 | if (len > avail) | |
1724 | len = avail; | |
1725 | memcpy(s->mem + index, buf, len); | |
1726 | buf += len; | |
1727 | index += len; | |
1728 | if (index == s->stop) | |
1729 | index = s->start; | |
1730 | size -= len; | |
1731 | } | |
1732 | s->curpag = next >> 8; | |
1733 | ||
1734 | /* now we can signal we have receive something */ | |
1735 | s->isr |= ENISR_RX; | |
1736 | ne2000_update_irq(s); | |
1737 | } | |
1738 | ||
1739 | void ne2000_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val) | |
1740 | { | |
1741 | NE2000State *s = &ne2000_state; | |
1742 | int offset, page; | |
1743 | ||
1744 | addr &= 0xf; | |
1745 | #ifdef DEBUG_NE2000 | |
1746 | printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val); | |
1747 | #endif | |
1748 | if (addr == E8390_CMD) { | |
1749 | /* control register */ | |
1750 | s->cmd = val; | |
1751 | if (val & E8390_START) { | |
1752 | /* test specific case: zero length transfert */ | |
1753 | if ((val & (E8390_RREAD | E8390_RWRITE)) && | |
1754 | s->rcnt == 0) { | |
1755 | s->isr |= ENISR_RDC; | |
1756 | ne2000_update_irq(s); | |
1757 | } | |
1758 | if (val & E8390_TRANS) { | |
1759 | net_send_packet(s, s->mem + (s->tpsr << 8), s->tcnt); | |
1760 | /* signal end of transfert */ | |
1761 | s->tsr = ENTSR_PTX; | |
1762 | s->isr |= ENISR_TX; | |
1763 | ne2000_update_irq(s); | |
1764 | } | |
1765 | } | |
1766 | } else { | |
1767 | page = s->cmd >> 6; | |
1768 | offset = addr | (page << 4); | |
1769 | switch(offset) { | |
1770 | case EN0_STARTPG: | |
1771 | s->start = val << 8; | |
1772 | break; | |
1773 | case EN0_STOPPG: | |
1774 | s->stop = val << 8; | |
1775 | break; | |
1776 | case EN0_BOUNDARY: | |
1777 | s->boundary = val; | |
1778 | break; | |
1779 | case EN0_IMR: | |
1780 | s->imr = val; | |
1781 | ne2000_update_irq(s); | |
1782 | break; | |
1783 | case EN0_TPSR: | |
1784 | s->tpsr = val; | |
1785 | break; | |
1786 | case EN0_TCNTLO: | |
1787 | s->tcnt = (s->tcnt & 0xff00) | val; | |
1788 | break; | |
1789 | case EN0_TCNTHI: | |
1790 | s->tcnt = (s->tcnt & 0x00ff) | (val << 8); | |
1791 | break; | |
1792 | case EN0_RSARLO: | |
1793 | s->rsar = (s->rsar & 0xff00) | val; | |
1794 | break; | |
1795 | case EN0_RSARHI: | |
1796 | s->rsar = (s->rsar & 0x00ff) | (val << 8); | |
1797 | break; | |
1798 | case EN0_RCNTLO: | |
1799 | s->rcnt = (s->rcnt & 0xff00) | val; | |
1800 | break; | |
1801 | case EN0_RCNTHI: | |
1802 | s->rcnt = (s->rcnt & 0x00ff) | (val << 8); | |
1803 | break; | |
1804 | case EN0_DCFG: | |
1805 | s->dcfg = val; | |
1806 | break; | |
1807 | case EN0_ISR: | |
1808 | s->isr &= ~val; | |
1809 | ne2000_update_irq(s); | |
1810 | break; | |
1811 | case EN1_PHYS ... EN1_PHYS + 5: | |
1812 | s->phys[offset - EN1_PHYS] = val; | |
1813 | break; | |
1814 | case EN1_CURPAG: | |
1815 | s->curpag = val; | |
1816 | break; | |
1817 | case EN1_MULT ... EN1_MULT + 7: | |
1818 | s->mult[offset - EN1_MULT] = val; | |
1819 | break; | |
1820 | } | |
1821 | } | |
1822 | } | |
1823 | ||
1824 | uint32_t ne2000_ioport_read(CPUX86State *env, uint32_t addr) | |
1825 | { | |
1826 | NE2000State *s = &ne2000_state; | |
1827 | int offset, page, ret; | |
1828 | ||
1829 | addr &= 0xf; | |
1830 | if (addr == E8390_CMD) { | |
1831 | ret = s->cmd; | |
1832 | } else { | |
1833 | page = s->cmd >> 6; | |
1834 | offset = addr | (page << 4); | |
1835 | switch(offset) { | |
1836 | case EN0_TSR: | |
1837 | ret = s->tsr; | |
1838 | break; | |
1839 | case EN0_BOUNDARY: | |
1840 | ret = s->boundary; | |
1841 | break; | |
1842 | case EN0_ISR: | |
1843 | ret = s->isr; | |
1844 | break; | |
1845 | case EN1_PHYS ... EN1_PHYS + 5: | |
1846 | ret = s->phys[offset - EN1_PHYS]; | |
1847 | break; | |
1848 | case EN1_CURPAG: | |
1849 | ret = s->curpag; | |
1850 | break; | |
1851 | case EN1_MULT ... EN1_MULT + 7: | |
1852 | ret = s->mult[offset - EN1_MULT]; | |
1853 | break; | |
1854 | default: | |
1855 | ret = 0x00; | |
1856 | break; | |
1857 | } | |
1858 | } | |
1859 | #ifdef DEBUG_NE2000 | |
1860 | printf("NE2000: read addr=0x%x val=%02x\n", addr, ret); | |
1861 | #endif | |
1862 | return ret; | |
1863 | } | |
1864 | ||
1865 | void ne2000_asic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val) | |
1866 | { | |
1867 | NE2000State *s = &ne2000_state; | |
1868 | uint8_t *p; | |
1869 | ||
1870 | #ifdef DEBUG_NE2000 | |
1871 | printf("NE2000: asic write val=0x%04x\n", val); | |
1872 | #endif | |
1873 | p = s->mem + s->rsar; | |
1874 | if (s->dcfg & 0x01) { | |
1875 | /* 16 bit access */ | |
1876 | p[0] = val; | |
1877 | p[1] = val >> 8; | |
1878 | s->rsar += 2; | |
1879 | s->rcnt -= 2; | |
1880 | } else { | |
1881 | /* 8 bit access */ | |
1882 | p[0] = val; | |
1883 | s->rsar++; | |
1884 | s->rcnt--; | |
1885 | } | |
1886 | /* wrap */ | |
1887 | if (s->rsar == s->stop) | |
1888 | s->rsar = s->start; | |
1889 | if (s->rcnt == 0) { | |
1890 | /* signal end of transfert */ | |
1891 | s->isr |= ENISR_RDC; | |
1892 | ne2000_update_irq(s); | |
1893 | } | |
1894 | } | |
1895 | ||
1896 | uint32_t ne2000_asic_ioport_read(CPUX86State *env, uint32_t addr) | |
1897 | { | |
1898 | NE2000State *s = &ne2000_state; | |
1899 | uint8_t *p; | |
1900 | int ret; | |
1901 | ||
1902 | p = s->mem + s->rsar; | |
1903 | if (s->dcfg & 0x01) { | |
1904 | /* 16 bit access */ | |
1905 | ret = p[0] | (p[1] << 8); | |
1906 | s->rsar += 2; | |
1907 | s->rcnt -= 2; | |
1908 | } else { | |
1909 | /* 8 bit access */ | |
1910 | ret = p[0]; | |
1911 | s->rsar++; | |
1912 | s->rcnt--; | |
1913 | } | |
1914 | /* wrap */ | |
1915 | if (s->rsar == s->stop) | |
1916 | s->rsar = s->start; | |
1917 | if (s->rcnt == 0) { | |
1918 | /* signal end of transfert */ | |
1919 | s->isr |= ENISR_RDC; | |
1920 | ne2000_update_irq(s); | |
1921 | } | |
1922 | #ifdef DEBUG_NE2000 | |
1923 | printf("NE2000: asic read val=0x%04x\n", ret); | |
1924 | #endif | |
1925 | return ret; | |
1926 | } | |
1927 | ||
1928 | void ne2000_reset_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val) | |
1929 | { | |
1930 | /* nothing to do (end of reset pulse) */ | |
1931 | } | |
1932 | ||
1933 | uint32_t ne2000_reset_ioport_read(CPUX86State *env, uint32_t addr) | |
1934 | { | |
1935 | ne2000_reset(); | |
1936 | return 0; | |
1937 | } | |
1938 | ||
1939 | void ne2000_init(void) | |
1940 | { | |
fc01f7e7 FB |
1941 | register_ioport_write(NE2000_IOPORT, 16, ne2000_ioport_write, 1); |
1942 | register_ioport_read(NE2000_IOPORT, 16, ne2000_ioport_read, 1); | |
f1510b2c | 1943 | |
fc01f7e7 FB |
1944 | register_ioport_write(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write, 1); |
1945 | register_ioport_read(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read, 1); | |
1946 | register_ioport_write(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write, 2); | |
1947 | register_ioport_read(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read, 2); | |
f1510b2c | 1948 | |
fc01f7e7 FB |
1949 | register_ioport_write(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write, 1); |
1950 | register_ioport_read(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read, 1); | |
f1510b2c FB |
1951 | ne2000_reset(); |
1952 | } | |
1953 | ||
cd4c3e88 | 1954 | /***********************************************************/ |
330d0414 FB |
1955 | /* keyboard emulation */ |
1956 | ||
1957 | /* Keyboard Controller Commands */ | |
1958 | #define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */ | |
1959 | #define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */ | |
1960 | #define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */ | |
1961 | #define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */ | |
1962 | #define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */ | |
1963 | #define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */ | |
1964 | #define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */ | |
1965 | #define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */ | |
1966 | #define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */ | |
1967 | #define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */ | |
1968 | #define KBD_CCMD_READ_INPORT 0xC0 /* read input port */ | |
1969 | #define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */ | |
1970 | #define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */ | |
1971 | #define KBD_CCMD_WRITE_OBUF 0xD2 | |
1972 | #define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if | |
1973 | initiated by the auxiliary device */ | |
1974 | #define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */ | |
1f5476fc FB |
1975 | #define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */ |
1976 | #define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */ | |
330d0414 FB |
1977 | #define KBD_CCMD_RESET 0xFE |
1978 | ||
1979 | /* Keyboard Commands */ | |
1980 | #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ | |
1981 | #define KBD_CMD_ECHO 0xEE | |
1982 | #define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */ | |
1983 | #define KBD_CMD_ENABLE 0xF4 /* Enable scanning */ | |
1984 | #define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */ | |
1985 | #define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */ | |
1986 | #define KBD_CMD_RESET 0xFF /* Reset */ | |
1987 | ||
1988 | /* Keyboard Replies */ | |
1989 | #define KBD_REPLY_POR 0xAA /* Power on reset */ | |
1990 | #define KBD_REPLY_ACK 0xFA /* Command ACK */ | |
1991 | #define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */ | |
1992 | ||
1993 | /* Status Register Bits */ | |
1994 | #define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */ | |
1995 | #define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ | |
1996 | #define KBD_STAT_SELFTEST 0x04 /* Self test successful */ | |
1997 | #define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */ | |
1998 | #define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */ | |
1999 | #define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */ | |
2000 | #define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */ | |
2001 | #define KBD_STAT_PERR 0x80 /* Parity error */ | |
2002 | ||
2003 | /* Controller Mode Register Bits */ | |
2004 | #define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */ | |
2005 | #define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */ | |
2006 | #define KBD_MODE_SYS 0x04 /* The system flag (?) */ | |
2007 | #define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */ | |
2008 | #define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */ | |
2009 | #define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */ | |
2010 | #define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ | |
2011 | #define KBD_MODE_RFU 0x80 | |
2012 | ||
2013 | /* Mouse Commands */ | |
330d0414 FB |
2014 | #define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */ |
2015 | #define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */ | |
313aa567 | 2016 | #define AUX_SET_RES 0xE8 /* Set resolution */ |
330d0414 FB |
2017 | #define AUX_GET_SCALE 0xE9 /* Get scaling factor */ |
2018 | #define AUX_SET_STREAM 0xEA /* Set stream mode */ | |
313aa567 FB |
2019 | #define AUX_POLL 0xEB /* Poll */ |
2020 | #define AUX_RESET_WRAP 0xEC /* Reset wrap mode */ | |
2021 | #define AUX_SET_WRAP 0xEE /* Set wrap mode */ | |
2022 | #define AUX_SET_REMOTE 0xF0 /* Set remote mode */ | |
2023 | #define AUX_GET_TYPE 0xF2 /* Get type */ | |
330d0414 FB |
2024 | #define AUX_SET_SAMPLE 0xF3 /* Set sample rate */ |
2025 | #define AUX_ENABLE_DEV 0xF4 /* Enable aux device */ | |
2026 | #define AUX_DISABLE_DEV 0xF5 /* Disable aux device */ | |
313aa567 | 2027 | #define AUX_SET_DEFAULT 0xF6 |
330d0414 FB |
2028 | #define AUX_RESET 0xFF /* Reset aux device */ |
2029 | #define AUX_ACK 0xFA /* Command byte ACK. */ | |
2030 | ||
313aa567 FB |
2031 | #define MOUSE_STATUS_REMOTE 0x40 |
2032 | #define MOUSE_STATUS_ENABLED 0x20 | |
2033 | #define MOUSE_STATUS_SCALE21 0x10 | |
2034 | ||
2035 | #define KBD_QUEUE_SIZE 256 | |
330d0414 FB |
2036 | |
2037 | typedef struct { | |
2038 | uint8_t data[KBD_QUEUE_SIZE]; | |
2039 | int rptr, wptr, count; | |
2040 | } KBDQueue; | |
2041 | ||
330d0414 FB |
2042 | typedef struct KBDState { |
2043 | KBDQueue queues[2]; | |
2044 | uint8_t write_cmd; /* if non zero, write data to port 60 is expected */ | |
2045 | uint8_t status; | |
2046 | uint8_t mode; | |
313aa567 | 2047 | /* keyboard state */ |
330d0414 FB |
2048 | int kbd_write_cmd; |
2049 | int scan_enabled; | |
313aa567 FB |
2050 | /* mouse state */ |
2051 | int mouse_write_cmd; | |
2052 | uint8_t mouse_status; | |
2053 | uint8_t mouse_resolution; | |
2054 | uint8_t mouse_sample_rate; | |
2055 | uint8_t mouse_wrap; | |
2056 | uint8_t mouse_type; /* 0 = PS2, 3 = IMPS/2, 4 = IMEX */ | |
2057 | uint8_t mouse_detect_state; | |
2058 | int mouse_dx; /* current values, needed for 'poll' mode */ | |
2059 | int mouse_dy; | |
2060 | int mouse_dz; | |
2061 | uint8_t mouse_buttons; | |
330d0414 FB |
2062 | } KBDState; |
2063 | ||
2064 | KBDState kbd_state; | |
cd4c3e88 | 2065 | int reset_requested; |
330d0414 | 2066 | |
313aa567 | 2067 | /* update irq and KBD_STAT_[MOUSE_]OBF */ |
330d0414 FB |
2068 | static void kbd_update_irq(KBDState *s) |
2069 | { | |
313aa567 FB |
2070 | int irq12_level, irq1_level; |
2071 | ||
2072 | irq1_level = 0; | |
2073 | irq12_level = 0; | |
2074 | s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF); | |
2075 | if (s->queues[0].count != 0 || | |
2076 | s->queues[1].count != 0) { | |
2077 | s->status |= KBD_STAT_OBF; | |
2078 | if (s->queues[1].count != 0) { | |
2079 | s->status |= KBD_STAT_MOUSE_OBF; | |
2080 | if (s->mode & KBD_MODE_MOUSE_INT) | |
2081 | irq12_level = 1; | |
2082 | } else { | |
2083 | if (s->mode & KBD_MODE_KBD_INT) | |
2084 | irq1_level = 1; | |
2085 | } | |
2086 | } | |
2087 | pic_set_irq(1, irq1_level); | |
2088 | pic_set_irq(12, irq12_level); | |
330d0414 FB |
2089 | } |
2090 | ||
2091 | static void kbd_queue(KBDState *s, int b, int aux) | |
2092 | { | |
2093 | KBDQueue *q = &kbd_state.queues[aux]; | |
2094 | ||
313aa567 FB |
2095 | #if defined(DEBUG_MOUSE) || defined(DEBUG_KBD) |
2096 | if (aux) | |
2097 | printf("mouse event: 0x%02x\n", b); | |
2098 | #ifdef DEBUG_KBD | |
2099 | else | |
2100 | printf("kbd event: 0x%02x\n", b); | |
2101 | #endif | |
2102 | #endif | |
330d0414 FB |
2103 | if (q->count >= KBD_QUEUE_SIZE) |
2104 | return; | |
2105 | q->data[q->wptr] = b; | |
2106 | if (++q->wptr == KBD_QUEUE_SIZE) | |
2107 | q->wptr = 0; | |
2108 | q->count++; | |
330d0414 FB |
2109 | kbd_update_irq(s); |
2110 | } | |
cd4c3e88 | 2111 | |
313aa567 FB |
2112 | void kbd_put_keycode(int keycode) |
2113 | { | |
2114 | KBDState *s = &kbd_state; | |
2115 | kbd_queue(s, keycode, 0); | |
2116 | } | |
2117 | ||
cd4c3e88 FB |
2118 | uint32_t kbd_read_status(CPUX86State *env, uint32_t addr) |
2119 | { | |
330d0414 FB |
2120 | KBDState *s = &kbd_state; |
2121 | int val; | |
2122 | val = s->status; | |
2123 | #if defined(DEBUG_KBD) && 0 | |
2124 | printf("kbd: read status=0x%02x\n", val); | |
2125 | #endif | |
2126 | return val; | |
cd4c3e88 FB |
2127 | } |
2128 | ||
2129 | void kbd_write_command(CPUX86State *env, uint32_t addr, uint32_t val) | |
2130 | { | |
330d0414 FB |
2131 | KBDState *s = &kbd_state; |
2132 | ||
2133 | #ifdef DEBUG_KBD | |
2134 | printf("kbd: write cmd=0x%02x\n", val); | |
2135 | #endif | |
cd4c3e88 | 2136 | switch(val) { |
330d0414 FB |
2137 | case KBD_CCMD_READ_MODE: |
2138 | kbd_queue(s, s->mode, 0); | |
2139 | break; | |
2140 | case KBD_CCMD_WRITE_MODE: | |
2141 | case KBD_CCMD_WRITE_OBUF: | |
2142 | case KBD_CCMD_WRITE_AUX_OBUF: | |
2143 | case KBD_CCMD_WRITE_MOUSE: | |
2144 | case KBD_CCMD_WRITE_OUTPORT: | |
2145 | s->write_cmd = val; | |
2146 | break; | |
2147 | case KBD_CCMD_MOUSE_DISABLE: | |
2148 | s->mode |= KBD_MODE_DISABLE_MOUSE; | |
2149 | break; | |
2150 | case KBD_CCMD_MOUSE_ENABLE: | |
2151 | s->mode &= ~KBD_MODE_DISABLE_MOUSE; | |
2152 | break; | |
2153 | case KBD_CCMD_TEST_MOUSE: | |
2154 | kbd_queue(s, 0x00, 0); | |
2155 | break; | |
2156 | case KBD_CCMD_SELF_TEST: | |
2157 | s->status |= KBD_STAT_SELFTEST; | |
2158 | kbd_queue(s, 0x55, 0); | |
2159 | break; | |
2160 | case KBD_CCMD_KBD_TEST: | |
2161 | kbd_queue(s, 0x00, 0); | |
2162 | break; | |
2163 | case KBD_CCMD_KBD_DISABLE: | |
2164 | s->mode |= KBD_MODE_DISABLE_KBD; | |
2165 | break; | |
2166 | case KBD_CCMD_KBD_ENABLE: | |
2167 | s->mode &= ~KBD_MODE_DISABLE_KBD; | |
2168 | break; | |
2169 | case KBD_CCMD_READ_INPORT: | |
2170 | kbd_queue(s, 0x00, 0); | |
2171 | break; | |
2172 | case KBD_CCMD_READ_OUTPORT: | |
2173 | /* XXX: check that */ | |
2174 | val = 0x01 | (a20_enabled << 1); | |
2175 | if (s->status & KBD_STAT_OBF) | |
2176 | val |= 0x10; | |
2177 | if (s->status & KBD_STAT_MOUSE_OBF) | |
2178 | val |= 0x20; | |
2179 | kbd_queue(s, val, 0); | |
2180 | break; | |
2181 | case KBD_CCMD_ENABLE_A20: | |
1f5476fc | 2182 | cpu_x86_set_a20(env, 1); |
330d0414 FB |
2183 | break; |
2184 | case KBD_CCMD_DISABLE_A20: | |
1f5476fc | 2185 | cpu_x86_set_a20(env, 0); |
330d0414 FB |
2186 | break; |
2187 | case KBD_CCMD_RESET: | |
cd4c3e88 FB |
2188 | reset_requested = 1; |
2189 | cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT); | |
2190 | break; | |
27503323 FB |
2191 | case 0xff: |
2192 | /* ignore that - I don't know what is its use */ | |
2193 | break; | |
330d0414 | 2194 | default: |
36b486bb | 2195 | fprintf(stderr, "qemu: unsupported keyboard cmd=0x%02x\n", val); |
330d0414 FB |
2196 | break; |
2197 | } | |
2198 | } | |
2199 | ||
2200 | uint32_t kbd_read_data(CPUX86State *env, uint32_t addr) | |
2201 | { | |
2202 | KBDState *s = &kbd_state; | |
2203 | KBDQueue *q; | |
7dea1da4 | 2204 | int val, index; |
330d0414 | 2205 | |
313aa567 | 2206 | q = &s->queues[0]; /* first check KBD data */ |
330d0414 | 2207 | if (q->count == 0) |
313aa567 | 2208 | q = &s->queues[1]; /* then check AUX data */ |
330d0414 | 2209 | if (q->count == 0) { |
7dea1da4 FB |
2210 | /* NOTE: if no data left, we return the last keyboard one |
2211 | (needed for EMM386) */ | |
2212 | /* XXX: need a timer to do things correctly */ | |
2213 | q = &s->queues[0]; | |
2214 | index = q->rptr - 1; | |
2215 | if (index < 0) | |
2216 | index = KBD_QUEUE_SIZE - 1; | |
2217 | val = q->data[index]; | |
330d0414 FB |
2218 | } else { |
2219 | val = q->data[q->rptr]; | |
2220 | if (++q->rptr == KBD_QUEUE_SIZE) | |
2221 | q->rptr = 0; | |
2222 | q->count--; | |
313aa567 FB |
2223 | /* reading deasserts IRQ */ |
2224 | if (q == &s->queues[0]) | |
2225 | pic_set_irq(1, 0); | |
2226 | else | |
2227 | pic_set_irq(12, 0); | |
330d0414 | 2228 | } |
313aa567 FB |
2229 | /* reassert IRQs if data left */ |
2230 | kbd_update_irq(s); | |
330d0414 FB |
2231 | #ifdef DEBUG_KBD |
2232 | printf("kbd: read data=0x%02x\n", val); | |
2233 | #endif | |
2234 | return val; | |
2235 | } | |
2236 | ||
2237 | static void kbd_reset_keyboard(KBDState *s) | |
2238 | { | |
2239 | s->scan_enabled = 1; | |
2240 | } | |
2241 | ||
2242 | static void kbd_write_keyboard(KBDState *s, int val) | |
2243 | { | |
2244 | switch(s->kbd_write_cmd) { | |
2245 | default: | |
2246 | case -1: | |
2247 | switch(val) { | |
2248 | case 0x00: | |
2249 | kbd_queue(s, KBD_REPLY_ACK, 0); | |
2250 | break; | |
2251 | case 0x05: | |
2252 | kbd_queue(s, KBD_REPLY_RESEND, 0); | |
2253 | break; | |
2254 | case KBD_CMD_ECHO: | |
2255 | kbd_queue(s, KBD_CMD_ECHO, 0); | |
2256 | break; | |
2257 | case KBD_CMD_ENABLE: | |
2258 | s->scan_enabled = 1; | |
2259 | kbd_queue(s, KBD_REPLY_ACK, 0); | |
2260 | break; | |
2261 | case KBD_CMD_SET_LEDS: | |
2262 | case KBD_CMD_SET_RATE: | |
2263 | s->kbd_write_cmd = val; | |
1f5476fc | 2264 | kbd_queue(s, KBD_REPLY_ACK, 0); |
330d0414 FB |
2265 | break; |
2266 | case KBD_CMD_RESET_DISABLE: | |
2267 | kbd_reset_keyboard(s); | |
2268 | s->scan_enabled = 0; | |
2269 | kbd_queue(s, KBD_REPLY_ACK, 0); | |
2270 | break; | |
2271 | case KBD_CMD_RESET_ENABLE: | |
2272 | kbd_reset_keyboard(s); | |
2273 | s->scan_enabled = 1; | |
2274 | kbd_queue(s, KBD_REPLY_ACK, 0); | |
2275 | break; | |
2276 | case KBD_CMD_RESET: | |
2277 | kbd_reset_keyboard(s); | |
2278 | kbd_queue(s, KBD_REPLY_ACK, 0); | |
2279 | kbd_queue(s, KBD_REPLY_POR, 0); | |
2280 | break; | |
2281 | default: | |
2282 | kbd_queue(s, KBD_REPLY_ACK, 0); | |
2283 | break; | |
2284 | } | |
2285 | break; | |
2286 | case KBD_CMD_SET_LEDS: | |
2287 | kbd_queue(s, KBD_REPLY_ACK, 0); | |
313aa567 | 2288 | s->kbd_write_cmd = -1; |
330d0414 FB |
2289 | break; |
2290 | case KBD_CMD_SET_RATE: | |
2291 | kbd_queue(s, KBD_REPLY_ACK, 0); | |
313aa567 FB |
2292 | s->kbd_write_cmd = -1; |
2293 | break; | |
2294 | } | |
2295 | } | |
2296 | ||
2297 | static void kbd_mouse_send_packet(KBDState *s) | |
2298 | { | |
2299 | unsigned int b; | |
2300 | int dx1, dy1, dz1; | |
2301 | ||
2302 | dx1 = s->mouse_dx; | |
2303 | dy1 = s->mouse_dy; | |
2304 | dz1 = s->mouse_dz; | |
2305 | /* XXX: increase range to 8 bits ? */ | |
2306 | if (dx1 > 127) | |
2307 | dx1 = 127; | |
2308 | else if (dx1 < -127) | |
2309 | dx1 = -127; | |
2310 | if (dy1 > 127) | |
2311 | dy1 = 127; | |
2312 | else if (dy1 < -127) | |
2313 | dy1 = -127; | |
2314 | b = 0x08 | ((dx1 < 0) << 4) | ((dy1 < 0) << 5) | (s->mouse_buttons & 0x07); | |
2315 | kbd_queue(s, b, 1); | |
2316 | kbd_queue(s, dx1 & 0xff, 1); | |
2317 | kbd_queue(s, dy1 & 0xff, 1); | |
2318 | /* extra byte for IMPS/2 or IMEX */ | |
2319 | switch(s->mouse_type) { | |
2320 | default: | |
2321 | break; | |
2322 | case 3: | |
2323 | if (dz1 > 127) | |
2324 | dz1 = 127; | |
2325 | else if (dz1 < -127) | |
2326 | dz1 = -127; | |
2327 | kbd_queue(s, dz1 & 0xff, 1); | |
2328 | break; | |
2329 | case 4: | |
2330 | if (dz1 > 7) | |
2331 | dz1 = 7; | |
2332 | else if (dz1 < -7) | |
2333 | dz1 = -7; | |
2334 | b = (dz1 & 0x0f) | ((s->mouse_buttons & 0x18) << 1); | |
2335 | kbd_queue(s, b, 1); | |
2336 | break; | |
2337 | } | |
2338 | ||
2339 | /* update deltas */ | |
2340 | s->mouse_dx -= dx1; | |
2341 | s->mouse_dy -= dy1; | |
2342 | s->mouse_dz -= dz1; | |
2343 | } | |
2344 | ||
2345 | void kbd_mouse_event(int dx, int dy, int dz, int buttons_state) | |
2346 | { | |
2347 | KBDState *s = &kbd_state; | |
2348 | ||
2349 | /* check if deltas are recorded when disabled */ | |
2350 | if (!(s->mouse_status & MOUSE_STATUS_ENABLED)) | |
2351 | return; | |
2352 | ||
2353 | s->mouse_dx += dx; | |
2354 | s->mouse_dy -= dy; | |
2355 | s->mouse_dz += dz; | |
2356 | s->mouse_buttons = buttons_state; | |
2357 | ||
2358 | if (!(s->mouse_status & MOUSE_STATUS_REMOTE) && | |
2359 | (s->queues[1].count < (KBD_QUEUE_SIZE - 16))) { | |
2360 | for(;;) { | |
2361 | /* if not remote, send event. Multiple events are sent if | |
2362 | too big deltas */ | |
2363 | kbd_mouse_send_packet(s); | |
2364 | if (s->mouse_dx == 0 && s->mouse_dy == 0 && s->mouse_dz == 0) | |
2365 | break; | |
2366 | } | |
2367 | } | |
2368 | } | |
2369 | ||
2370 | static void kbd_write_mouse(KBDState *s, int val) | |
2371 | { | |
2372 | #ifdef DEBUG_MOUSE | |
2373 | printf("kbd: write mouse 0x%02x\n", val); | |
2374 | #endif | |
2375 | switch(s->mouse_write_cmd) { | |
2376 | default: | |
2377 | case -1: | |
2378 | /* mouse command */ | |
2379 | if (s->mouse_wrap) { | |
2380 | if (val == AUX_RESET_WRAP) { | |
2381 | s->mouse_wrap = 0; | |
2382 | kbd_queue(s, AUX_ACK, 1); | |
2383 | return; | |
2384 | } else if (val != AUX_RESET) { | |
2385 | kbd_queue(s, val, 1); | |
2386 | return; | |
2387 | } | |
2388 | } | |
2389 | switch(val) { | |
2390 | case AUX_SET_SCALE11: | |
2391 | s->mouse_status &= ~MOUSE_STATUS_SCALE21; | |
2392 | kbd_queue(s, AUX_ACK, 1); | |
2393 | break; | |
2394 | case AUX_SET_SCALE21: | |
2395 | s->mouse_status |= MOUSE_STATUS_SCALE21; | |
2396 | kbd_queue(s, AUX_ACK, 1); | |
2397 | break; | |
2398 | case AUX_SET_STREAM: | |
2399 | s->mouse_status &= ~MOUSE_STATUS_REMOTE; | |
2400 | kbd_queue(s, AUX_ACK, 1); | |
2401 | break; | |
2402 | case AUX_SET_WRAP: | |
2403 | s->mouse_wrap = 1; | |
2404 | kbd_queue(s, AUX_ACK, 1); | |
2405 | break; | |
2406 | case AUX_SET_REMOTE: | |
2407 | s->mouse_status |= MOUSE_STATUS_REMOTE; | |
2408 | kbd_queue(s, AUX_ACK, 1); | |
2409 | break; | |
2410 | case AUX_GET_TYPE: | |
2411 | kbd_queue(s, AUX_ACK, 1); | |
2412 | kbd_queue(s, s->mouse_type, 1); | |
2413 | break; | |
2414 | case AUX_SET_RES: | |
2415 | case AUX_SET_SAMPLE: | |
2416 | s->mouse_write_cmd = val; | |
2417 | kbd_queue(s, AUX_ACK, 1); | |
2418 | break; | |
2419 | case AUX_GET_SCALE: | |
2420 | kbd_queue(s, AUX_ACK, 1); | |
2421 | kbd_queue(s, s->mouse_status, 1); | |
2422 | kbd_queue(s, s->mouse_resolution, 1); | |
2423 | kbd_queue(s, s->mouse_sample_rate, 1); | |
2424 | break; | |
2425 | case AUX_POLL: | |
2426 | kbd_queue(s, AUX_ACK, 1); | |
2427 | kbd_mouse_send_packet(s); | |
2428 | break; | |
2429 | case AUX_ENABLE_DEV: | |
2430 | s->mouse_status |= MOUSE_STATUS_ENABLED; | |
2431 | kbd_queue(s, AUX_ACK, 1); | |
2432 | break; | |
2433 | case AUX_DISABLE_DEV: | |
2434 | s->mouse_status &= ~MOUSE_STATUS_ENABLED; | |
2435 | kbd_queue(s, AUX_ACK, 1); | |
2436 | break; | |
2437 | case AUX_SET_DEFAULT: | |
2438 | s->mouse_sample_rate = 100; | |
2439 | s->mouse_resolution = 2; | |
2440 | s->mouse_status = 0; | |
2441 | kbd_queue(s, AUX_ACK, 1); | |
2442 | break; | |
2443 | case AUX_RESET: | |
2444 | s->mouse_sample_rate = 100; | |
2445 | s->mouse_resolution = 2; | |
2446 | s->mouse_status = 0; | |
2447 | kbd_queue(s, AUX_ACK, 1); | |
2448 | kbd_queue(s, 0xaa, 1); | |
2449 | kbd_queue(s, s->mouse_type, 1); | |
2450 | break; | |
2451 | default: | |
2452 | break; | |
2453 | } | |
2454 | break; | |
2455 | case AUX_SET_SAMPLE: | |
2456 | s->mouse_sample_rate = val; | |
2457 | #if 0 | |
2458 | /* detect IMPS/2 or IMEX */ | |
2459 | switch(s->mouse_detect_state) { | |
2460 | default: | |
2461 | case 0: | |
2462 | if (val == 200) | |
2463 | s->mouse_detect_state = 1; | |
2464 | break; | |
2465 | case 1: | |
2466 | if (val == 100) | |
2467 | s->mouse_detect_state = 2; | |
2468 | else if (val == 200) | |
2469 | s->mouse_detect_state = 3; | |
2470 | else | |
2471 | s->mouse_detect_state = 0; | |
2472 | break; | |
2473 | case 2: | |
2474 | if (val == 80) | |
2475 | s->mouse_type = 3; /* IMPS/2 */ | |
2476 | s->mouse_detect_state = 0; | |
2477 | break; | |
2478 | case 3: | |
2479 | if (val == 80) | |
2480 | s->mouse_type = 4; /* IMEX */ | |
2481 | s->mouse_detect_state = 0; | |
2482 | break; | |
2483 | } | |
2484 | #endif | |
2485 | kbd_queue(s, AUX_ACK, 1); | |
2486 | s->mouse_write_cmd = -1; | |
2487 | break; | |
2488 | case AUX_SET_RES: | |
2489 | s->mouse_resolution = val; | |
2490 | kbd_queue(s, AUX_ACK, 1); | |
2491 | s->mouse_write_cmd = -1; | |
330d0414 FB |
2492 | break; |
2493 | } | |
330d0414 FB |
2494 | } |
2495 | ||
2496 | void kbd_write_data(CPUX86State *env, uint32_t addr, uint32_t val) | |
2497 | { | |
2498 | KBDState *s = &kbd_state; | |
2499 | ||
2500 | #ifdef DEBUG_KBD | |
2501 | printf("kbd: write data=0x%02x\n", val); | |
2502 | #endif | |
2503 | ||
2504 | switch(s->write_cmd) { | |
2505 | case 0: | |
2506 | kbd_write_keyboard(s, val); | |
2507 | break; | |
2508 | case KBD_CCMD_WRITE_MODE: | |
2509 | s->mode = val; | |
2510 | kbd_update_irq(s); | |
2511 | break; | |
2512 | case KBD_CCMD_WRITE_OBUF: | |
2513 | kbd_queue(s, val, 0); | |
2514 | break; | |
2515 | case KBD_CCMD_WRITE_AUX_OBUF: | |
2516 | kbd_queue(s, val, 1); | |
2517 | break; | |
2518 | case KBD_CCMD_WRITE_OUTPORT: | |
1f5476fc | 2519 | cpu_x86_set_a20(env, (val >> 1) & 1); |
330d0414 FB |
2520 | if (!(val & 1)) { |
2521 | reset_requested = 1; | |
2522 | cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT); | |
2523 | } | |
2524 | break; | |
313aa567 FB |
2525 | case KBD_CCMD_WRITE_MOUSE: |
2526 | kbd_write_mouse(s, val); | |
2527 | break; | |
cd4c3e88 FB |
2528 | default: |
2529 | break; | |
2530 | } | |
330d0414 FB |
2531 | s->write_cmd = 0; |
2532 | } | |
2533 | ||
2534 | void kbd_reset(KBDState *s) | |
2535 | { | |
2536 | KBDQueue *q; | |
2537 | int i; | |
2538 | ||
2539 | s->kbd_write_cmd = -1; | |
313aa567 | 2540 | s->mouse_write_cmd = -1; |
330d0414 | 2541 | s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT; |
313aa567 | 2542 | s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED; |
330d0414 FB |
2543 | for(i = 0; i < 2; i++) { |
2544 | q = &s->queues[i]; | |
2545 | q->rptr = 0; | |
2546 | q->wptr = 0; | |
2547 | q->count = 0; | |
2548 | } | |
cd4c3e88 FB |
2549 | } |
2550 | ||
2551 | void kbd_init(void) | |
2552 | { | |
330d0414 FB |
2553 | kbd_reset(&kbd_state); |
2554 | register_ioport_read(0x60, 1, kbd_read_data, 1); | |
2555 | register_ioport_write(0x60, 1, kbd_write_data, 1); | |
cd4c3e88 FB |
2556 | register_ioport_read(0x64, 1, kbd_read_status, 1); |
2557 | register_ioport_write(0x64, 1, kbd_write_command, 1); | |
2558 | } | |
2559 | ||
330d0414 FB |
2560 | /***********************************************************/ |
2561 | /* Bochs BIOS debug ports */ | |
2562 | ||
2563 | void bochs_bios_write(CPUX86State *env, uint32_t addr, uint32_t val) | |
2564 | { | |
2565 | switch(addr) { | |
2566 | /* Bochs BIOS messages */ | |
2567 | case 0x400: | |
2568 | case 0x401: | |
2569 | fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val); | |
2570 | exit(1); | |
2571 | case 0x402: | |
2572 | case 0x403: | |
2573 | #ifdef DEBUG_BIOS | |
2574 | fprintf(stderr, "%c", val); | |
2575 | #endif | |
2576 | break; | |
2577 | ||
2578 | /* LGPL'ed VGA BIOS messages */ | |
2579 | case 0x501: | |
2580 | case 0x502: | |
2581 | fprintf(stderr, "VGA BIOS panic, line %d\n", val); | |
2582 | exit(1); | |
2583 | case 0x500: | |
2584 | case 0x503: | |
2585 | #ifdef DEBUG_BIOS | |
2586 | fprintf(stderr, "%c", val); | |
2587 | #endif | |
2588 | break; | |
2589 | } | |
2590 | } | |
2591 | ||
2592 | void bochs_bios_init(void) | |
2593 | { | |
2594 | register_ioport_write(0x400, 1, bochs_bios_write, 2); | |
2595 | register_ioport_write(0x401, 1, bochs_bios_write, 2); | |
2596 | register_ioport_write(0x402, 1, bochs_bios_write, 1); | |
2597 | register_ioport_write(0x403, 1, bochs_bios_write, 1); | |
2598 | ||
2599 | register_ioport_write(0x501, 1, bochs_bios_write, 2); | |
2600 | register_ioport_write(0x502, 1, bochs_bios_write, 2); | |
2601 | register_ioport_write(0x500, 1, bochs_bios_write, 1); | |
2602 | register_ioport_write(0x503, 1, bochs_bios_write, 1); | |
2603 | } | |
2604 | ||
313aa567 FB |
2605 | /***********************************************************/ |
2606 | /* dumb display */ | |
2607 | ||
2608 | /* init terminal so that we can grab keys */ | |
2609 | static struct termios oldtty; | |
2610 | ||
2611 | static void term_exit(void) | |
2612 | { | |
2613 | tcsetattr (0, TCSANOW, &oldtty); | |
2614 | } | |
2615 | ||
2616 | static void term_init(void) | |
2617 | { | |
2618 | struct termios tty; | |
2619 | ||
2620 | tcgetattr (0, &tty); | |
2621 | oldtty = tty; | |
2622 | ||
2623 | tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP | |
2624 | |INLCR|IGNCR|ICRNL|IXON); | |
2625 | tty.c_oflag |= OPOST; | |
a20dd508 FB |
2626 | tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN); |
2627 | /* if graphical mode, we allow Ctrl-C handling */ | |
2628 | if (nographic) | |
2629 | tty.c_lflag &= ~ISIG; | |
313aa567 FB |
2630 | tty.c_cflag &= ~(CSIZE|PARENB); |
2631 | tty.c_cflag |= CS8; | |
2632 | tty.c_cc[VMIN] = 1; | |
2633 | tty.c_cc[VTIME] = 0; | |
2634 | ||
2635 | tcsetattr (0, TCSANOW, &tty); | |
2636 | ||
2637 | atexit(term_exit); | |
2638 | ||
2639 | fcntl(0, F_SETFL, O_NONBLOCK); | |
2640 | } | |
2641 | ||
2642 | static void dumb_update(DisplayState *ds, int x, int y, int w, int h) | |
2643 | { | |
2644 | } | |
2645 | ||
2646 | static void dumb_resize(DisplayState *ds, int w, int h) | |
2647 | { | |
2648 | } | |
2649 | ||
2650 | static void dumb_refresh(DisplayState *ds) | |
2651 | { | |
2652 | vga_update_display(); | |
2653 | } | |
2654 | ||
2655 | void dumb_display_init(DisplayState *ds) | |
2656 | { | |
2657 | ds->data = NULL; | |
2658 | ds->linesize = 0; | |
2659 | ds->depth = 0; | |
2660 | ds->dpy_update = dumb_update; | |
2661 | ds->dpy_resize = dumb_resize; | |
2662 | ds->dpy_refresh = dumb_refresh; | |
2663 | } | |
2664 | ||
3a51dee6 | 2665 | #if !defined(CONFIG_SOFTMMU) |
f1510b2c | 2666 | /***********************************************************/ |
0824d6fc FB |
2667 | /* cpu signal handler */ |
2668 | static void host_segv_handler(int host_signum, siginfo_t *info, | |
2669 | void *puc) | |
2670 | { | |
2671 | if (cpu_signal_handler(host_signum, info, puc)) | |
2672 | return; | |
2673 | term_exit(); | |
2674 | abort(); | |
2675 | } | |
3a51dee6 | 2676 | #endif |
0824d6fc FB |
2677 | |
2678 | static int timer_irq_pending; | |
87858c89 | 2679 | static int timer_irq_count; |
0824d6fc | 2680 | |
313aa567 FB |
2681 | static int timer_ms; |
2682 | static int gui_refresh_pending, gui_refresh_count; | |
2683 | ||
0824d6fc FB |
2684 | static void host_alarm_handler(int host_signum, siginfo_t *info, |
2685 | void *puc) | |
2686 | { | |
87858c89 FB |
2687 | /* NOTE: since usually the OS asks a 100 Hz clock, there can be |
2688 | some drift between cpu_get_ticks() and the interrupt time. So | |
2689 | we queue some interrupts to avoid missing some */ | |
2690 | timer_irq_count += pit_get_out_edges(&pit_channels[0]); | |
2691 | if (timer_irq_count) { | |
2692 | if (timer_irq_count > 2) | |
2693 | timer_irq_count = 2; | |
2694 | timer_irq_count--; | |
313aa567 FB |
2695 | timer_irq_pending = 1; |
2696 | } | |
2697 | gui_refresh_count += timer_ms; | |
2698 | if (gui_refresh_count >= GUI_REFRESH_INTERVAL) { | |
2699 | gui_refresh_count = 0; | |
2700 | gui_refresh_pending = 1; | |
2701 | } | |
2702 | ||
27503323 FB |
2703 | /* XXX: seems dangerous to run that here. */ |
2704 | DMA_run(); | |
2705 | SB16_run(); | |
2706 | ||
313aa567 | 2707 | if (gui_refresh_pending || timer_irq_pending) { |
87858c89 | 2708 | /* just exit from the cpu to have a chance to handle timers */ |
c9159e53 | 2709 | cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT); |
87858c89 | 2710 | } |
0824d6fc FB |
2711 | } |
2712 | ||
7f7f9873 FB |
2713 | #ifdef CONFIG_SOFTMMU |
2714 | void *get_mmap_addr(unsigned long size) | |
2715 | { | |
2716 | return NULL; | |
2717 | } | |
2718 | #else | |
33e3963e FB |
2719 | unsigned long mmap_addr = PHYS_RAM_BASE; |
2720 | ||
2721 | void *get_mmap_addr(unsigned long size) | |
2722 | { | |
2723 | unsigned long addr; | |
2724 | addr = mmap_addr; | |
2725 | mmap_addr += ((size + 4095) & ~4095) + 4096; | |
2726 | return (void *)addr; | |
2727 | } | |
7f7f9873 | 2728 | #endif |
33e3963e | 2729 | |
b4608c04 FB |
2730 | /* main execution loop */ |
2731 | ||
2732 | CPUState *cpu_gdbstub_get_env(void *opaque) | |
2733 | { | |
2734 | return global_env; | |
2735 | } | |
2736 | ||
4c3a88a2 | 2737 | int main_loop(void *opaque) |
b4608c04 | 2738 | { |
27c3f2cb FB |
2739 | struct pollfd ufds[3], *pf, *serial_ufd, *net_ufd, *gdb_ufd; |
2740 | int ret, n, timeout, serial_ok; | |
b4608c04 FB |
2741 | uint8_t ch; |
2742 | CPUState *env = global_env; | |
2743 | ||
a20dd508 | 2744 | if (!term_inited) { |
313aa567 FB |
2745 | /* initialize terminal only there so that the user has a |
2746 | chance to stop QEMU with Ctrl-C before the gdb connection | |
2747 | is launched */ | |
2748 | term_inited = 1; | |
2749 | term_init(); | |
2750 | } | |
2751 | ||
27c3f2cb | 2752 | serial_ok = 1; |
34865134 | 2753 | cpu_enable_ticks(); |
b4608c04 | 2754 | for(;;) { |
b4608c04 | 2755 | ret = cpu_x86_exec(env); |
34865134 FB |
2756 | if (reset_requested) { |
2757 | ret = EXCP_INTERRUPT; | |
cd4c3e88 | 2758 | break; |
34865134 FB |
2759 | } |
2760 | if (ret == EXCP_DEBUG) { | |
2761 | ret = EXCP_DEBUG; | |
2762 | break; | |
2763 | } | |
b4608c04 FB |
2764 | /* if hlt instruction, we wait until the next IRQ */ |
2765 | if (ret == EXCP_HLT) | |
2766 | timeout = 10; | |
2767 | else | |
2768 | timeout = 0; | |
2769 | /* poll any events */ | |
2770 | serial_ufd = NULL; | |
2771 | pf = ufds; | |
27c3f2cb | 2772 | if (serial_ok && !(serial_ports[0].lsr & UART_LSR_DR)) { |
b4608c04 FB |
2773 | serial_ufd = pf; |
2774 | pf->fd = 0; | |
2775 | pf->events = POLLIN; | |
2776 | pf++; | |
2777 | } | |
2778 | net_ufd = NULL; | |
2779 | if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) { | |
2780 | net_ufd = pf; | |
2781 | pf->fd = net_fd; | |
2782 | pf->events = POLLIN; | |
2783 | pf++; | |
2784 | } | |
2785 | gdb_ufd = NULL; | |
2786 | if (gdbstub_fd > 0) { | |
2787 | gdb_ufd = pf; | |
2788 | pf->fd = gdbstub_fd; | |
2789 | pf->events = POLLIN; | |
2790 | pf++; | |
2791 | } | |
2792 | ||
2793 | ret = poll(ufds, pf - ufds, timeout); | |
2794 | if (ret > 0) { | |
2795 | if (serial_ufd && (serial_ufd->revents & POLLIN)) { | |
2796 | n = read(0, &ch, 1); | |
2797 | if (n == 1) { | |
2798 | serial_received_byte(&serial_ports[0], ch); | |
27c3f2cb FB |
2799 | } else { |
2800 | /* Closed, stop polling. */ | |
2801 | serial_ok = 0; | |
b4608c04 FB |
2802 | } |
2803 | } | |
2804 | if (net_ufd && (net_ufd->revents & POLLIN)) { | |
2805 | uint8_t buf[MAX_ETH_FRAME_SIZE]; | |
2806 | ||
2807 | n = read(net_fd, buf, MAX_ETH_FRAME_SIZE); | |
2808 | if (n > 0) { | |
2809 | if (n < 60) { | |
2810 | memset(buf + n, 0, 60 - n); | |
2811 | n = 60; | |
2812 | } | |
2813 | ne2000_receive(&ne2000_state, buf, n); | |
2814 | } | |
2815 | } | |
2816 | if (gdb_ufd && (gdb_ufd->revents & POLLIN)) { | |
2817 | uint8_t buf[1]; | |
2818 | /* stop emulation if requested by gdb */ | |
2819 | n = read(gdbstub_fd, buf, 1); | |
34865134 FB |
2820 | if (n == 1) { |
2821 | ret = EXCP_INTERRUPT; | |
b4608c04 | 2822 | break; |
34865134 | 2823 | } |
b4608c04 FB |
2824 | } |
2825 | } | |
2826 | ||
2827 | /* timer IRQ */ | |
2828 | if (timer_irq_pending) { | |
2829 | pic_set_irq(0, 1); | |
2830 | pic_set_irq(0, 0); | |
2831 | timer_irq_pending = 0; | |
7dea1da4 FB |
2832 | /* XXX: RTC test */ |
2833 | if (cmos_data[RTC_REG_B] & 0x40) { | |
2834 | pic_set_irq(8, 1); | |
2835 | } | |
b4608c04 | 2836 | } |
313aa567 FB |
2837 | |
2838 | /* VGA */ | |
2839 | if (gui_refresh_pending) { | |
2840 | display_state.dpy_refresh(&display_state); | |
2841 | gui_refresh_pending = 0; | |
2842 | } | |
b4608c04 | 2843 | } |
34865134 FB |
2844 | cpu_disable_ticks(); |
2845 | return ret; | |
b4608c04 FB |
2846 | } |
2847 | ||
0824d6fc FB |
2848 | void help(void) |
2849 | { | |
a20dd508 | 2850 | printf("QEMU PC emulator version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n" |
0db63474 | 2851 | "usage: %s [options] [disk_image]\n" |
0824d6fc | 2852 | "\n" |
a20dd508 | 2853 | "'disk_image' is a raw hard image image for IDE hard disk 0\n" |
fc01f7e7 | 2854 | "\n" |
a20dd508 | 2855 | "Standard options:\n" |
36b486bb FB |
2856 | "-hda/-hdb file use 'file' as IDE hard disk 0/1 image\n" |
2857 | "-hdc/-hdd file use 'file' as IDE hard disk 2/3 image\n" | |
2858 | "-cdrom file use 'file' as IDE cdrom 2 image\n" | |
27503323 | 2859 | "-boot [c|d] boot on hard disk (c) or CD-ROM (d)\n" |
a20dd508 FB |
2860 | "-snapshot write to temporary files instead of disk image files\n" |
2861 | "-m megs set virtual RAM size to megs MB\n" | |
2862 | "-n script set network init script [default=%s]\n" | |
42f1e0e4 | 2863 | "-tun-fd fd this fd talks to tap/tun, use it.\n" |
a20dd508 FB |
2864 | "-nographic disable graphical output\n" |
2865 | "\n" | |
2866 | "Linux boot specific (does not require PC BIOS):\n" | |
2867 | "-kernel bzImage use 'bzImage' as kernel image\n" | |
2868 | "-append cmdline use 'cmdline' as kernel command line\n" | |
2869 | "-initrd file use 'file' as initial ram disk\n" | |
fc01f7e7 | 2870 | "\n" |
330d0414 | 2871 | "Debug/Expert options:\n" |
a20dd508 FB |
2872 | "-s wait gdb connection to port %d\n" |
2873 | "-p port change gdb connection port\n" | |
2874 | "-d output log in /tmp/vl.log\n" | |
2875 | "-hdachs c,h,s force hard disk 0 geometry (usually qemu can guess it)\n" | |
2876 | "-L path set the directory for the BIOS and VGA BIOS\n" | |
0824d6fc | 2877 | "\n" |
f1510b2c | 2878 | "During emulation, use C-a h to get terminal commands:\n", |
0db63474 FB |
2879 | #ifdef CONFIG_SOFTMMU |
2880 | "qemu", | |
2881 | #else | |
2882 | "qemu-fast", | |
2883 | #endif | |
2884 | DEFAULT_NETWORK_SCRIPT, | |
2885 | DEFAULT_GDBSTUB_PORT); | |
0824d6fc | 2886 | term_print_help(); |
0db63474 FB |
2887 | #ifndef CONFIG_SOFTMMU |
2888 | printf("\n" | |
2889 | "NOTE: this version of QEMU is faster but it needs slightly patched OSes to\n" | |
2890 | "work. Please use the 'qemu' executable to have a more accurate (but slower)\n" | |
2891 | "PC emulation.\n"); | |
2892 | #endif | |
0824d6fc FB |
2893 | exit(1); |
2894 | } | |
2895 | ||
fc01f7e7 FB |
2896 | struct option long_options[] = { |
2897 | { "initrd", 1, NULL, 0, }, | |
2898 | { "hda", 1, NULL, 0, }, | |
2899 | { "hdb", 1, NULL, 0, }, | |
33e3963e | 2900 | { "snapshot", 0, NULL, 0, }, |
330d0414 | 2901 | { "hdachs", 1, NULL, 0, }, |
a20dd508 FB |
2902 | { "nographic", 0, NULL, 0, }, |
2903 | { "kernel", 1, NULL, 0, }, | |
2904 | { "append", 1, NULL, 0, }, | |
42f1e0e4 | 2905 | { "tun-fd", 1, NULL, 0, }, |
36b486bb FB |
2906 | { "hdc", 1, NULL, 0, }, |
2907 | { "hdd", 1, NULL, 0, }, | |
2908 | { "cdrom", 1, NULL, 0, }, | |
2909 | { "boot", 1, NULL, 0, }, | |
fc01f7e7 FB |
2910 | { NULL, 0, NULL, 0 }, |
2911 | }; | |
2912 | ||
a20dd508 FB |
2913 | #ifdef CONFIG_SDL |
2914 | /* SDL use the pthreads and they modify sigaction. We don't | |
2915 | want that. */ | |
2916 | #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3) | |
2917 | extern void __libc_sigaction(); | |
2918 | #define sigaction(sig, act, oact) __libc_sigaction(sig, act, oact) | |
2919 | #else | |
2920 | extern void __sigaction(); | |
2921 | #define sigaction(sig, act, oact) __sigaction(sig, act, oact) | |
2922 | #endif | |
2923 | #endif /* CONFIG_SDL */ | |
2924 | ||
0824d6fc FB |
2925 | int main(int argc, char **argv) |
2926 | { | |
fc01f7e7 | 2927 | int c, ret, initrd_size, i, use_gdbstub, gdbstub_port, long_index; |
313aa567 | 2928 | int snapshot, linux_boot, total_ram_size; |
0824d6fc FB |
2929 | struct linux_params *params; |
2930 | struct sigaction act; | |
2931 | struct itimerval itv; | |
2932 | CPUX86State *env; | |
7f7f9873 | 2933 | const char *initrd_filename; |
fc01f7e7 | 2934 | const char *hd_filename[MAX_DISKS]; |
a20dd508 | 2935 | const char *kernel_filename, *kernel_cmdline; |
313aa567 FB |
2936 | DisplayState *ds = &display_state; |
2937 | ||
0824d6fc FB |
2938 | /* we never want that malloc() uses mmap() */ |
2939 | mallopt(M_MMAP_THRESHOLD, 4096 * 1024); | |
fc01f7e7 FB |
2940 | initrd_filename = NULL; |
2941 | for(i = 0; i < MAX_DISKS; i++) | |
2942 | hd_filename[i] = NULL; | |
0824d6fc | 2943 | phys_ram_size = 32 * 1024 * 1024; |
313aa567 | 2944 | vga_ram_size = VGA_RAM_SIZE; |
f1510b2c | 2945 | pstrcpy(network_script, sizeof(network_script), DEFAULT_NETWORK_SCRIPT); |
b4608c04 FB |
2946 | use_gdbstub = 0; |
2947 | gdbstub_port = DEFAULT_GDBSTUB_PORT; | |
33e3963e | 2948 | snapshot = 0; |
a20dd508 FB |
2949 | nographic = 0; |
2950 | kernel_filename = NULL; | |
2951 | kernel_cmdline = ""; | |
0824d6fc | 2952 | for(;;) { |
330d0414 | 2953 | c = getopt_long_only(argc, argv, "hm:dn:sp:L:", long_options, &long_index); |
0824d6fc FB |
2954 | if (c == -1) |
2955 | break; | |
2956 | switch(c) { | |
fc01f7e7 FB |
2957 | case 0: |
2958 | switch(long_index) { | |
2959 | case 0: | |
2960 | initrd_filename = optarg; | |
2961 | break; | |
2962 | case 1: | |
2963 | hd_filename[0] = optarg; | |
2964 | break; | |
2965 | case 2: | |
2966 | hd_filename[1] = optarg; | |
2967 | break; | |
33e3963e FB |
2968 | case 3: |
2969 | snapshot = 1; | |
2970 | break; | |
330d0414 FB |
2971 | case 4: |
2972 | { | |
2973 | int cyls, heads, secs; | |
2974 | const char *p; | |
2975 | p = optarg; | |
2976 | cyls = strtol(p, (char **)&p, 0); | |
2977 | if (*p != ',') | |
2978 | goto chs_fail; | |
2979 | p++; | |
2980 | heads = strtol(p, (char **)&p, 0); | |
2981 | if (*p != ',') | |
2982 | goto chs_fail; | |
2983 | p++; | |
2984 | secs = strtol(p, (char **)&p, 0); | |
2985 | if (*p != '\0') | |
2986 | goto chs_fail; | |
5391d806 | 2987 | ide_set_geometry(0, cyls, heads, secs); |
330d0414 FB |
2988 | chs_fail: ; |
2989 | } | |
2990 | break; | |
313aa567 | 2991 | case 5: |
a20dd508 FB |
2992 | nographic = 1; |
2993 | break; | |
2994 | case 6: | |
2995 | kernel_filename = optarg; | |
2996 | break; | |
2997 | case 7: | |
2998 | kernel_cmdline = optarg; | |
313aa567 | 2999 | break; |
42f1e0e4 FB |
3000 | case 8: |
3001 | net_fd = atoi(optarg); | |
3002 | break; | |
36b486bb FB |
3003 | case 9: |
3004 | hd_filename[2] = optarg; | |
3005 | break; | |
3006 | case 10: | |
3007 | hd_filename[3] = optarg; | |
3008 | break; | |
3009 | case 11: | |
3010 | hd_filename[2] = optarg; | |
5391d806 | 3011 | ide_set_cdrom(2, 1); |
36b486bb FB |
3012 | break; |
3013 | case 12: | |
3014 | boot_device = optarg[0]; | |
3015 | if (boot_device != 'c' && boot_device != 'd') { | |
3016 | fprintf(stderr, "qemu: invalid boot device '%c'\n", boot_device); | |
3017 | exit(1); | |
3018 | } | |
3019 | break; | |
fc01f7e7 FB |
3020 | } |
3021 | break; | |
0824d6fc FB |
3022 | case 'h': |
3023 | help(); | |
3024 | break; | |
3025 | case 'm': | |
3026 | phys_ram_size = atoi(optarg) * 1024 * 1024; | |
3027 | if (phys_ram_size <= 0) | |
3028 | help(); | |
7916e224 | 3029 | if (phys_ram_size > PHYS_RAM_MAX_SIZE) { |
36b486bb | 3030 | fprintf(stderr, "qemu: at most %d MB RAM can be simulated\n", |
7916e224 FB |
3031 | PHYS_RAM_MAX_SIZE / (1024 * 1024)); |
3032 | exit(1); | |
3033 | } | |
0824d6fc FB |
3034 | break; |
3035 | case 'd': | |
34865134 | 3036 | cpu_set_log(CPU_LOG_ALL); |
0824d6fc | 3037 | break; |
f1510b2c FB |
3038 | case 'n': |
3039 | pstrcpy(network_script, sizeof(network_script), optarg); | |
3040 | break; | |
b4608c04 FB |
3041 | case 's': |
3042 | use_gdbstub = 1; | |
3043 | break; | |
3044 | case 'p': | |
3045 | gdbstub_port = atoi(optarg); | |
3046 | break; | |
330d0414 | 3047 | case 'L': |
5a67135a | 3048 | bios_dir = optarg; |
330d0414 | 3049 | break; |
0824d6fc FB |
3050 | } |
3051 | } | |
330d0414 | 3052 | |
a20dd508 FB |
3053 | if (optind < argc) { |
3054 | hd_filename[0] = argv[optind++]; | |
3055 | } | |
3056 | ||
3057 | linux_boot = (kernel_filename != NULL); | |
330d0414 | 3058 | |
36b486bb | 3059 | if (!linux_boot && hd_filename[0] == '\0' && hd_filename[2] == '\0') |
0824d6fc FB |
3060 | help(); |
3061 | ||
3062 | /* init debug */ | |
b118d61e | 3063 | setvbuf(stdout, NULL, _IOLBF, 0); |
0824d6fc | 3064 | |
f1510b2c | 3065 | /* init network tun interface */ |
42f1e0e4 FB |
3066 | if (net_fd < 0) |
3067 | net_init(); | |
f1510b2c | 3068 | |
0824d6fc | 3069 | /* init the memory */ |
313aa567 | 3070 | total_ram_size = phys_ram_size + vga_ram_size; |
7f7f9873 FB |
3071 | |
3072 | #ifdef CONFIG_SOFTMMU | |
3073 | phys_ram_base = malloc(total_ram_size); | |
3074 | if (!phys_ram_base) { | |
3075 | fprintf(stderr, "Could not allocate physical memory\n"); | |
0824d6fc FB |
3076 | exit(1); |
3077 | } | |
7f7f9873 FB |
3078 | #else |
3079 | /* as we must map the same page at several addresses, we must use | |
3080 | a fd */ | |
3081 | { | |
3082 | const char *tmpdir; | |
3083 | ||
3084 | tmpdir = getenv("QEMU_TMPDIR"); | |
3085 | if (!tmpdir) | |
3086 | tmpdir = "/tmp"; | |
3087 | snprintf(phys_ram_file, sizeof(phys_ram_file), "%s/vlXXXXXX", tmpdir); | |
3088 | if (mkstemp(phys_ram_file) < 0) { | |
3089 | fprintf(stderr, "Could not create temporary memory file '%s'\n", | |
3090 | phys_ram_file); | |
3091 | exit(1); | |
3092 | } | |
3093 | phys_ram_fd = open(phys_ram_file, O_CREAT | O_TRUNC | O_RDWR, 0600); | |
3094 | if (phys_ram_fd < 0) { | |
3095 | fprintf(stderr, "Could not open temporary memory file '%s'\n", | |
3096 | phys_ram_file); | |
3097 | exit(1); | |
3098 | } | |
3099 | ftruncate(phys_ram_fd, total_ram_size); | |
3100 | unlink(phys_ram_file); | |
3101 | phys_ram_base = mmap(get_mmap_addr(total_ram_size), | |
3102 | total_ram_size, | |
3103 | PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED, | |
3104 | phys_ram_fd, 0); | |
3105 | if (phys_ram_base == MAP_FAILED) { | |
3106 | fprintf(stderr, "Could not map physical memory\n"); | |
3107 | exit(1); | |
3108 | } | |
3109 | } | |
3110 | #endif | |
0824d6fc | 3111 | |
33e3963e FB |
3112 | /* open the virtual block devices */ |
3113 | for(i = 0; i < MAX_DISKS; i++) { | |
3114 | if (hd_filename[i]) { | |
3115 | bs_table[i] = bdrv_open(hd_filename[i], snapshot); | |
3116 | if (!bs_table[i]) { | |
36b486bb | 3117 | fprintf(stderr, "qemu: could not open hard disk image '%s\n", |
33e3963e FB |
3118 | hd_filename[i]); |
3119 | exit(1); | |
3120 | } | |
3121 | } | |
3122 | } | |
3123 | ||
330d0414 FB |
3124 | /* init CPU state */ |
3125 | env = cpu_init(); | |
3126 | global_env = env; | |
3127 | cpu_single_env = env; | |
3128 | ||
3129 | init_ioports(); | |
0824d6fc | 3130 | |
313aa567 FB |
3131 | /* allocate RAM */ |
3132 | cpu_register_physical_memory(0, phys_ram_size, 0); | |
3133 | ||
330d0414 FB |
3134 | if (linux_boot) { |
3135 | /* now we can load the kernel */ | |
a20dd508 | 3136 | ret = load_kernel(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
330d0414 | 3137 | if (ret < 0) { |
36b486bb | 3138 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
a20dd508 | 3139 | kernel_filename); |
fc01f7e7 FB |
3140 | exit(1); |
3141 | } | |
330d0414 FB |
3142 | |
3143 | /* load initrd */ | |
3144 | initrd_size = 0; | |
3145 | if (initrd_filename) { | |
3146 | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); | |
3147 | if (initrd_size < 0) { | |
36b486bb | 3148 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
330d0414 FB |
3149 | initrd_filename); |
3150 | exit(1); | |
3151 | } | |
3152 | } | |
3153 | ||
3154 | /* init kernel params */ | |
3155 | params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR); | |
3156 | memset(params, 0, sizeof(struct linux_params)); | |
3157 | params->mount_root_rdonly = 0; | |
7f7f9873 FB |
3158 | stw_raw(¶ms->cl_magic, 0xA33F); |
3159 | stw_raw(¶ms->cl_offset, params->commandline - (uint8_t *)params); | |
3160 | stl_raw(¶ms->alt_mem_k, (phys_ram_size / 1024) - 1024); | |
a20dd508 | 3161 | pstrcat(params->commandline, sizeof(params->commandline), kernel_cmdline); |
330d0414 FB |
3162 | params->loader_type = 0x01; |
3163 | if (initrd_size > 0) { | |
7f7f9873 FB |
3164 | stl_raw(¶ms->initrd_start, INITRD_LOAD_ADDR); |
3165 | stl_raw(¶ms->initrd_size, initrd_size); | |
330d0414 FB |
3166 | } |
3167 | params->orig_video_lines = 25; | |
3168 | params->orig_video_cols = 80; | |
3169 | ||
3170 | /* setup basic memory access */ | |
3171 | env->cr[0] = 0x00000033; | |
3172 | cpu_x86_init_mmu(env); | |
3173 | ||
3174 | memset(params->idt_table, 0, sizeof(params->idt_table)); | |
3175 | ||
7f7f9873 FB |
3176 | stq_raw(¶ms->gdt_table[2], 0x00cf9a000000ffffLL); /* KERNEL_CS */ |
3177 | stq_raw(¶ms->gdt_table[3], 0x00cf92000000ffffLL); /* KERNEL_DS */ | |
dd6ee15c | 3178 | /* for newer kernels (2.6.0) CS/DS are at different addresses */ |
7f7f9873 FB |
3179 | stq_raw(¶ms->gdt_table[12], 0x00cf9a000000ffffLL); /* KERNEL_CS */ |
3180 | stq_raw(¶ms->gdt_table[13], 0x00cf92000000ffffLL); /* KERNEL_DS */ | |
330d0414 | 3181 | |
dd6ee15c | 3182 | env->idt.base = (void *)((uint8_t *)params->idt_table - phys_ram_base); |
330d0414 | 3183 | env->idt.limit = sizeof(params->idt_table) - 1; |
dd6ee15c | 3184 | env->gdt.base = (void *)((uint8_t *)params->gdt_table - phys_ram_base); |
330d0414 FB |
3185 | env->gdt.limit = sizeof(params->gdt_table) - 1; |
3186 | ||
2e255c6b FB |
3187 | cpu_x86_load_seg_cache(env, R_CS, KERNEL_CS, NULL, 0xffffffff, 0x00cf9a00); |
3188 | cpu_x86_load_seg_cache(env, R_DS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200); | |
3189 | cpu_x86_load_seg_cache(env, R_ES, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200); | |
3190 | cpu_x86_load_seg_cache(env, R_SS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200); | |
3191 | cpu_x86_load_seg_cache(env, R_FS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200); | |
3192 | cpu_x86_load_seg_cache(env, R_GS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200); | |
330d0414 FB |
3193 | |
3194 | env->eip = KERNEL_LOAD_ADDR; | |
3195 | env->regs[R_ESI] = KERNEL_PARAMS_ADDR; | |
3196 | env->eflags = 0x2; | |
0824d6fc | 3197 | |
330d0414 FB |
3198 | } else { |
3199 | char buf[1024]; | |
a20dd508 | 3200 | |
330d0414 FB |
3201 | /* RAW PC boot */ |
3202 | ||
3203 | /* BIOS load */ | |
5a67135a | 3204 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
330d0414 FB |
3205 | ret = load_image(buf, phys_ram_base + 0x000f0000); |
3206 | if (ret != 0x10000) { | |
36b486bb | 3207 | fprintf(stderr, "qemu: could not load PC bios '%s'\n", buf); |
330d0414 FB |
3208 | exit(1); |
3209 | } | |
3210 | ||
3211 | /* VGA BIOS load */ | |
5a67135a | 3212 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); |
330d0414 FB |
3213 | ret = load_image(buf, phys_ram_base + 0x000c0000); |
3214 | ||
3215 | /* setup basic memory access */ | |
3216 | env->cr[0] = 0x60000010; | |
3217 | cpu_x86_init_mmu(env); | |
3218 | ||
3219 | env->idt.limit = 0xffff; | |
3220 | env->gdt.limit = 0xffff; | |
3221 | env->ldt.limit = 0xffff; | |
7dea1da4 FB |
3222 | env->ldt.flags = DESC_P_MASK; |
3223 | env->tr.limit = 0xffff; | |
3224 | env->tr.flags = DESC_P_MASK; | |
330d0414 FB |
3225 | |
3226 | /* not correct (CS base=0xffff0000) */ | |
2e255c6b FB |
3227 | cpu_x86_load_seg_cache(env, R_CS, 0xf000, (uint8_t *)0x000f0000, 0xffff, 0); |
3228 | cpu_x86_load_seg_cache(env, R_DS, 0, NULL, 0xffff, 0); | |
3229 | cpu_x86_load_seg_cache(env, R_ES, 0, NULL, 0xffff, 0); | |
3230 | cpu_x86_load_seg_cache(env, R_SS, 0, NULL, 0xffff, 0); | |
3231 | cpu_x86_load_seg_cache(env, R_FS, 0, NULL, 0xffff, 0); | |
3232 | cpu_x86_load_seg_cache(env, R_GS, 0, NULL, 0xffff, 0); | |
330d0414 FB |
3233 | |
3234 | env->eip = 0xfff0; | |
3235 | env->regs[R_EDX] = 0x600; /* indicate P6 processor */ | |
3236 | ||
3237 | env->eflags = 0x2; | |
3238 | ||
3239 | bochs_bios_init(); | |
0824d6fc | 3240 | } |
0824d6fc | 3241 | |
313aa567 | 3242 | /* terminal init */ |
a20dd508 | 3243 | if (nographic) { |
313aa567 FB |
3244 | dumb_display_init(ds); |
3245 | } else { | |
3246 | #ifdef CONFIG_SDL | |
3247 | sdl_display_init(ds); | |
313aa567 FB |
3248 | #else |
3249 | dumb_display_init(ds); | |
3250 | #endif | |
3251 | } | |
0824d6fc | 3252 | /* init basic PC hardware */ |
fc01f7e7 | 3253 | register_ioport_write(0x80, 1, ioport80_write, 1); |
0824d6fc | 3254 | |
313aa567 FB |
3255 | vga_init(ds, phys_ram_base + phys_ram_size, phys_ram_size, |
3256 | vga_ram_size); | |
0824d6fc FB |
3257 | cmos_init(); |
3258 | pic_init(); | |
3259 | pit_init(); | |
3260 | serial_init(); | |
f1510b2c | 3261 | ne2000_init(); |
fc01f7e7 | 3262 | ide_init(); |
cd4c3e88 | 3263 | kbd_init(); |
27503323 FB |
3264 | AUD_init(); |
3265 | DMA_init(); | |
3266 | SB16_init(); | |
313aa567 | 3267 | |
0824d6fc FB |
3268 | /* setup cpu signal handlers for MMU / self modifying code handling */ |
3269 | sigfillset(&act.sa_mask); | |
3270 | act.sa_flags = SA_SIGINFO; | |
3a51dee6 | 3271 | #if !defined(CONFIG_SOFTMMU) |
0824d6fc FB |
3272 | act.sa_sigaction = host_segv_handler; |
3273 | sigaction(SIGSEGV, &act, NULL); | |
3274 | sigaction(SIGBUS, &act, NULL); | |
3a51dee6 | 3275 | #endif |
0824d6fc FB |
3276 | |
3277 | act.sa_sigaction = host_alarm_handler; | |
3278 | sigaction(SIGALRM, &act, NULL); | |
3279 | ||
0824d6fc | 3280 | itv.it_interval.tv_sec = 0; |
87858c89 | 3281 | itv.it_interval.tv_usec = 1000; |
0824d6fc FB |
3282 | itv.it_value.tv_sec = 0; |
3283 | itv.it_value.tv_usec = 10 * 1000; | |
3284 | setitimer(ITIMER_REAL, &itv, NULL); | |
87858c89 FB |
3285 | /* we probe the tick duration of the kernel to inform the user if |
3286 | the emulated kernel requested a too high timer frequency */ | |
3287 | getitimer(ITIMER_REAL, &itv); | |
313aa567 | 3288 | timer_ms = itv.it_interval.tv_usec / 1000; |
87858c89 FB |
3289 | pit_min_timer_count = ((uint64_t)itv.it_interval.tv_usec * PIT_FREQ) / |
3290 | 1000000; | |
7f7f9873 | 3291 | |
b4608c04 FB |
3292 | if (use_gdbstub) { |
3293 | cpu_gdbstub(NULL, main_loop, gdbstub_port); | |
3294 | } else { | |
3295 | main_loop(NULL); | |
0824d6fc | 3296 | } |
0824d6fc FB |
3297 | return 0; |
3298 | } |