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1 | /* | |
2 | * QEMU PC System Emulator | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "qemu/osdep.h" | |
26 | #include "qemu/units.h" | |
27 | #include "hw/hw.h" | |
28 | #include "hw/i386/pc.h" | |
29 | #include "hw/char/serial.h" | |
30 | #include "hw/char/parallel.h" | |
31 | #include "hw/i386/apic.h" | |
32 | #include "hw/i386/topology.h" | |
33 | #include "hw/i386/fw_cfg.h" | |
34 | #include "sysemu/cpus.h" | |
35 | #include "hw/block/fdc.h" | |
36 | #include "hw/ide.h" | |
37 | #include "hw/pci/pci.h" | |
38 | #include "hw/pci/pci_bus.h" | |
39 | #include "hw/nvram/fw_cfg.h" | |
40 | #include "hw/timer/hpet.h" | |
41 | #include "hw/firmware/smbios.h" | |
42 | #include "hw/loader.h" | |
43 | #include "elf.h" | |
44 | #include "multiboot.h" | |
45 | #include "hw/timer/mc146818rtc.h" | |
46 | #include "hw/dma/i8257.h" | |
47 | #include "hw/timer/i8254.h" | |
48 | #include "hw/input/i8042.h" | |
49 | #include "hw/audio/pcspk.h" | |
50 | #include "hw/pci/msi.h" | |
51 | #include "hw/sysbus.h" | |
52 | #include "sysemu/sysemu.h" | |
53 | #include "sysemu/tcg.h" | |
54 | #include "sysemu/numa.h" | |
55 | #include "sysemu/kvm.h" | |
56 | #include "sysemu/qtest.h" | |
57 | #include "kvm_i386.h" | |
58 | #include "hw/xen/xen.h" | |
59 | #include "hw/xen/start_info.h" | |
60 | #include "ui/qemu-spice.h" | |
61 | #include "exec/memory.h" | |
62 | #include "exec/address-spaces.h" | |
63 | #include "sysemu/arch_init.h" | |
64 | #include "qemu/bitmap.h" | |
65 | #include "qemu/config-file.h" | |
66 | #include "qemu/error-report.h" | |
67 | #include "qemu/option.h" | |
68 | #include "hw/acpi/acpi.h" | |
69 | #include "hw/acpi/cpu_hotplug.h" | |
70 | #include "hw/boards.h" | |
71 | #include "acpi-build.h" | |
72 | #include "hw/mem/pc-dimm.h" | |
73 | #include "qapi/error.h" | |
74 | #include "qapi/qapi-visit-common.h" | |
75 | #include "qapi/visitor.h" | |
76 | #include "qom/cpu.h" | |
77 | #include "hw/nmi.h" | |
78 | #include "hw/usb.h" | |
79 | #include "hw/i386/intel_iommu.h" | |
80 | #include "hw/net/ne2000-isa.h" | |
81 | #include "standard-headers/asm-x86/bootparam.h" | |
82 | #include "hw/virtio/virtio-pmem-pci.h" | |
83 | #include "hw/mem/memory-device.h" | |
84 | ||
85 | /* debug PC/ISA interrupts */ | |
86 | //#define DEBUG_IRQ | |
87 | ||
88 | #ifdef DEBUG_IRQ | |
89 | #define DPRINTF(fmt, ...) \ | |
90 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
91 | #else | |
92 | #define DPRINTF(fmt, ...) | |
93 | #endif | |
94 | ||
95 | #define E820_NR_ENTRIES 16 | |
96 | ||
97 | struct e820_entry { | |
98 | uint64_t address; | |
99 | uint64_t length; | |
100 | uint32_t type; | |
101 | } QEMU_PACKED __attribute((__aligned__(4))); | |
102 | ||
103 | struct e820_table { | |
104 | uint32_t count; | |
105 | struct e820_entry entry[E820_NR_ENTRIES]; | |
106 | } QEMU_PACKED __attribute((__aligned__(4))); | |
107 | ||
108 | static struct e820_table e820_reserve; | |
109 | static struct e820_entry *e820_table; | |
110 | static unsigned e820_entries; | |
111 | struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; | |
112 | ||
113 | /* Physical Address of PVH entry point read from kernel ELF NOTE */ | |
114 | static size_t pvh_start_addr; | |
115 | ||
116 | GlobalProperty pc_compat_4_0[] = {}; | |
117 | const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); | |
118 | ||
119 | GlobalProperty pc_compat_3_1[] = { | |
120 | { "intel-iommu", "dma-drain", "off" }, | |
121 | { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, | |
122 | { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, | |
123 | { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, | |
124 | { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
125 | { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, | |
126 | { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, | |
127 | { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
128 | { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, | |
129 | { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
130 | { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, | |
131 | { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, | |
132 | { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, | |
133 | { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, | |
134 | { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
135 | { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, | |
136 | { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
137 | { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, | |
138 | { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, | |
139 | { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, | |
140 | { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, | |
141 | }; | |
142 | const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); | |
143 | ||
144 | GlobalProperty pc_compat_3_0[] = { | |
145 | { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, | |
146 | { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, | |
147 | { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, | |
148 | }; | |
149 | const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); | |
150 | ||
151 | GlobalProperty pc_compat_2_12[] = { | |
152 | { TYPE_X86_CPU, "legacy-cache", "on" }, | |
153 | { TYPE_X86_CPU, "topoext", "off" }, | |
154 | { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, | |
155 | { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, | |
156 | }; | |
157 | const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); | |
158 | ||
159 | GlobalProperty pc_compat_2_11[] = { | |
160 | { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, | |
161 | { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, | |
162 | }; | |
163 | const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); | |
164 | ||
165 | GlobalProperty pc_compat_2_10[] = { | |
166 | { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, | |
167 | { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, | |
168 | { "q35-pcihost", "x-pci-hole64-fix", "off" }, | |
169 | }; | |
170 | const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); | |
171 | ||
172 | GlobalProperty pc_compat_2_9[] = { | |
173 | { "mch", "extended-tseg-mbytes", "0" }, | |
174 | }; | |
175 | const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); | |
176 | ||
177 | GlobalProperty pc_compat_2_8[] = { | |
178 | { TYPE_X86_CPU, "tcg-cpuid", "off" }, | |
179 | { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, | |
180 | { "ICH9-LPC", "x-smi-broadcast", "off" }, | |
181 | { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, | |
182 | { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, | |
183 | }; | |
184 | const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); | |
185 | ||
186 | GlobalProperty pc_compat_2_7[] = { | |
187 | { TYPE_X86_CPU, "l3-cache", "off" }, | |
188 | { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, | |
189 | { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, | |
190 | { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, | |
191 | { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, | |
192 | { "isa-pcspk", "migrate", "off" }, | |
193 | }; | |
194 | const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); | |
195 | ||
196 | GlobalProperty pc_compat_2_6[] = { | |
197 | { TYPE_X86_CPU, "cpuid-0xb", "off" }, | |
198 | { "vmxnet3", "romfile", "" }, | |
199 | { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, | |
200 | { "apic-common", "legacy-instance-id", "on", } | |
201 | }; | |
202 | const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); | |
203 | ||
204 | GlobalProperty pc_compat_2_5[] = {}; | |
205 | const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); | |
206 | ||
207 | GlobalProperty pc_compat_2_4[] = { | |
208 | PC_CPU_MODEL_IDS("2.4.0") | |
209 | { "Haswell-" TYPE_X86_CPU, "abm", "off" }, | |
210 | { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, | |
211 | { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, | |
212 | { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, | |
213 | { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, | |
214 | { TYPE_X86_CPU, "check", "off" }, | |
215 | { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, | |
216 | { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, | |
217 | { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, | |
218 | { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, | |
219 | { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
220 | { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
221 | { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, | |
222 | { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } | |
223 | }; | |
224 | const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); | |
225 | ||
226 | GlobalProperty pc_compat_2_3[] = { | |
227 | PC_CPU_MODEL_IDS("2.3.0") | |
228 | { TYPE_X86_CPU, "arat", "off" }, | |
229 | { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, | |
230 | { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, | |
231 | { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, | |
232 | { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, | |
233 | { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, | |
234 | { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, | |
235 | { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, | |
236 | { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
237 | { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
238 | { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
239 | { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
240 | { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
241 | { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
242 | { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
243 | { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
244 | { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
245 | { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
246 | { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, | |
247 | { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, | |
248 | }; | |
249 | const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); | |
250 | ||
251 | GlobalProperty pc_compat_2_2[] = { | |
252 | PC_CPU_MODEL_IDS("2.2.0") | |
253 | { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, | |
254 | { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, | |
255 | { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, | |
256 | { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, | |
257 | { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, | |
258 | { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, | |
259 | { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, | |
260 | { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, | |
261 | { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, | |
262 | { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, | |
263 | { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, | |
264 | { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, | |
265 | { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, | |
266 | { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, | |
267 | { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, | |
268 | { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, | |
269 | { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, | |
270 | { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, | |
271 | }; | |
272 | const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); | |
273 | ||
274 | GlobalProperty pc_compat_2_1[] = { | |
275 | PC_CPU_MODEL_IDS("2.1.0") | |
276 | { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, | |
277 | { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, | |
278 | }; | |
279 | const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); | |
280 | ||
281 | GlobalProperty pc_compat_2_0[] = { | |
282 | PC_CPU_MODEL_IDS("2.0.0") | |
283 | { "virtio-scsi-pci", "any_layout", "off" }, | |
284 | { "PIIX4_PM", "memory-hotplug-support", "off" }, | |
285 | { "apic", "version", "0x11" }, | |
286 | { "nec-usb-xhci", "superspeed-ports-first", "off" }, | |
287 | { "nec-usb-xhci", "force-pcie-endcap", "on" }, | |
288 | { "pci-serial", "prog_if", "0" }, | |
289 | { "pci-serial-2x", "prog_if", "0" }, | |
290 | { "pci-serial-4x", "prog_if", "0" }, | |
291 | { "virtio-net-pci", "guest_announce", "off" }, | |
292 | { "ICH9-LPC", "memory-hotplug-support", "off" }, | |
293 | { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, | |
294 | { "ioh3420", COMPAT_PROP_PCP, "off" }, | |
295 | }; | |
296 | const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); | |
297 | ||
298 | GlobalProperty pc_compat_1_7[] = { | |
299 | PC_CPU_MODEL_IDS("1.7.0") | |
300 | { TYPE_USB_DEVICE, "msos-desc", "no" }, | |
301 | { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, | |
302 | { "hpet", HPET_INTCAP, "4" }, | |
303 | }; | |
304 | const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); | |
305 | ||
306 | GlobalProperty pc_compat_1_6[] = { | |
307 | PC_CPU_MODEL_IDS("1.6.0") | |
308 | { "e1000", "mitigation", "off" }, | |
309 | { "qemu64-" TYPE_X86_CPU, "model", "2" }, | |
310 | { "qemu32-" TYPE_X86_CPU, "model", "3" }, | |
311 | { "i440FX-pcihost", "short_root_bus", "1" }, | |
312 | { "q35-pcihost", "short_root_bus", "1" }, | |
313 | }; | |
314 | const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); | |
315 | ||
316 | GlobalProperty pc_compat_1_5[] = { | |
317 | PC_CPU_MODEL_IDS("1.5.0") | |
318 | { "Conroe-" TYPE_X86_CPU, "model", "2" }, | |
319 | { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, | |
320 | { "Penryn-" TYPE_X86_CPU, "model", "2" }, | |
321 | { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, | |
322 | { "Nehalem-" TYPE_X86_CPU, "model", "2" }, | |
323 | { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, | |
324 | { "virtio-net-pci", "any_layout", "off" }, | |
325 | { TYPE_X86_CPU, "pmu", "on" }, | |
326 | { "i440FX-pcihost", "short_root_bus", "0" }, | |
327 | { "q35-pcihost", "short_root_bus", "0" }, | |
328 | }; | |
329 | const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); | |
330 | ||
331 | GlobalProperty pc_compat_1_4[] = { | |
332 | PC_CPU_MODEL_IDS("1.4.0") | |
333 | { "scsi-hd", "discard_granularity", "0" }, | |
334 | { "scsi-cd", "discard_granularity", "0" }, | |
335 | { "scsi-disk", "discard_granularity", "0" }, | |
336 | { "ide-hd", "discard_granularity", "0" }, | |
337 | { "ide-cd", "discard_granularity", "0" }, | |
338 | { "ide-drive", "discard_granularity", "0" }, | |
339 | { "virtio-blk-pci", "discard_granularity", "0" }, | |
340 | /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ | |
341 | { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, | |
342 | { "virtio-net-pci", "ctrl_guest_offloads", "off" }, | |
343 | { "e1000", "romfile", "pxe-e1000.rom" }, | |
344 | { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, | |
345 | { "pcnet", "romfile", "pxe-pcnet.rom" }, | |
346 | { "rtl8139", "romfile", "pxe-rtl8139.rom" }, | |
347 | { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, | |
348 | { "486-" TYPE_X86_CPU, "model", "0" }, | |
349 | { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, | |
350 | { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, | |
351 | }; | |
352 | const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); | |
353 | ||
354 | void gsi_handler(void *opaque, int n, int level) | |
355 | { | |
356 | GSIState *s = opaque; | |
357 | ||
358 | DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); | |
359 | if (n < ISA_NUM_IRQS) { | |
360 | qemu_set_irq(s->i8259_irq[n], level); | |
361 | } | |
362 | qemu_set_irq(s->ioapic_irq[n], level); | |
363 | } | |
364 | ||
365 | static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, | |
366 | unsigned size) | |
367 | { | |
368 | } | |
369 | ||
370 | static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) | |
371 | { | |
372 | return 0xffffffffffffffffULL; | |
373 | } | |
374 | ||
375 | /* MSDOS compatibility mode FPU exception support */ | |
376 | static qemu_irq ferr_irq; | |
377 | ||
378 | void pc_register_ferr_irq(qemu_irq irq) | |
379 | { | |
380 | ferr_irq = irq; | |
381 | } | |
382 | ||
383 | /* XXX: add IGNNE support */ | |
384 | void cpu_set_ferr(CPUX86State *s) | |
385 | { | |
386 | qemu_irq_raise(ferr_irq); | |
387 | } | |
388 | ||
389 | static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, | |
390 | unsigned size) | |
391 | { | |
392 | qemu_irq_lower(ferr_irq); | |
393 | } | |
394 | ||
395 | static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) | |
396 | { | |
397 | return 0xffffffffffffffffULL; | |
398 | } | |
399 | ||
400 | /* TSC handling */ | |
401 | uint64_t cpu_get_tsc(CPUX86State *env) | |
402 | { | |
403 | return cpu_get_ticks(); | |
404 | } | |
405 | ||
406 | /* IRQ handling */ | |
407 | int cpu_get_pic_interrupt(CPUX86State *env) | |
408 | { | |
409 | X86CPU *cpu = env_archcpu(env); | |
410 | int intno; | |
411 | ||
412 | if (!kvm_irqchip_in_kernel()) { | |
413 | intno = apic_get_interrupt(cpu->apic_state); | |
414 | if (intno >= 0) { | |
415 | return intno; | |
416 | } | |
417 | /* read the irq from the PIC */ | |
418 | if (!apic_accept_pic_intr(cpu->apic_state)) { | |
419 | return -1; | |
420 | } | |
421 | } | |
422 | ||
423 | intno = pic_read_irq(isa_pic); | |
424 | return intno; | |
425 | } | |
426 | ||
427 | static void pic_irq_request(void *opaque, int irq, int level) | |
428 | { | |
429 | CPUState *cs = first_cpu; | |
430 | X86CPU *cpu = X86_CPU(cs); | |
431 | ||
432 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); | |
433 | if (cpu->apic_state && !kvm_irqchip_in_kernel()) { | |
434 | CPU_FOREACH(cs) { | |
435 | cpu = X86_CPU(cs); | |
436 | if (apic_accept_pic_intr(cpu->apic_state)) { | |
437 | apic_deliver_pic_intr(cpu->apic_state, level); | |
438 | } | |
439 | } | |
440 | } else { | |
441 | if (level) { | |
442 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); | |
443 | } else { | |
444 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
445 | } | |
446 | } | |
447 | } | |
448 | ||
449 | /* PC cmos mappings */ | |
450 | ||
451 | #define REG_EQUIPMENT_BYTE 0x14 | |
452 | ||
453 | int cmos_get_fd_drive_type(FloppyDriveType fd0) | |
454 | { | |
455 | int val; | |
456 | ||
457 | switch (fd0) { | |
458 | case FLOPPY_DRIVE_TYPE_144: | |
459 | /* 1.44 Mb 3"5 drive */ | |
460 | val = 4; | |
461 | break; | |
462 | case FLOPPY_DRIVE_TYPE_288: | |
463 | /* 2.88 Mb 3"5 drive */ | |
464 | val = 5; | |
465 | break; | |
466 | case FLOPPY_DRIVE_TYPE_120: | |
467 | /* 1.2 Mb 5"5 drive */ | |
468 | val = 2; | |
469 | break; | |
470 | case FLOPPY_DRIVE_TYPE_NONE: | |
471 | default: | |
472 | val = 0; | |
473 | break; | |
474 | } | |
475 | return val; | |
476 | } | |
477 | ||
478 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, | |
479 | int16_t cylinders, int8_t heads, int8_t sectors) | |
480 | { | |
481 | rtc_set_memory(s, type_ofs, 47); | |
482 | rtc_set_memory(s, info_ofs, cylinders); | |
483 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
484 | rtc_set_memory(s, info_ofs + 2, heads); | |
485 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
486 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
487 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
488 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
489 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
490 | rtc_set_memory(s, info_ofs + 8, sectors); | |
491 | } | |
492 | ||
493 | /* convert boot_device letter to something recognizable by the bios */ | |
494 | static int boot_device2nibble(char boot_device) | |
495 | { | |
496 | switch(boot_device) { | |
497 | case 'a': | |
498 | case 'b': | |
499 | return 0x01; /* floppy boot */ | |
500 | case 'c': | |
501 | return 0x02; /* hard drive boot */ | |
502 | case 'd': | |
503 | return 0x03; /* CD-ROM boot */ | |
504 | case 'n': | |
505 | return 0x04; /* Network boot */ | |
506 | } | |
507 | return 0; | |
508 | } | |
509 | ||
510 | static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) | |
511 | { | |
512 | #define PC_MAX_BOOT_DEVICES 3 | |
513 | int nbds, bds[3] = { 0, }; | |
514 | int i; | |
515 | ||
516 | nbds = strlen(boot_device); | |
517 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
518 | error_setg(errp, "Too many boot devices for PC"); | |
519 | return; | |
520 | } | |
521 | for (i = 0; i < nbds; i++) { | |
522 | bds[i] = boot_device2nibble(boot_device[i]); | |
523 | if (bds[i] == 0) { | |
524 | error_setg(errp, "Invalid boot device for PC: '%c'", | |
525 | boot_device[i]); | |
526 | return; | |
527 | } | |
528 | } | |
529 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
530 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); | |
531 | } | |
532 | ||
533 | static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) | |
534 | { | |
535 | set_boot_dev(opaque, boot_device, errp); | |
536 | } | |
537 | ||
538 | static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) | |
539 | { | |
540 | int val, nb, i; | |
541 | FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, | |
542 | FLOPPY_DRIVE_TYPE_NONE }; | |
543 | ||
544 | /* floppy type */ | |
545 | if (floppy) { | |
546 | for (i = 0; i < 2; i++) { | |
547 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); | |
548 | } | |
549 | } | |
550 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
551 | cmos_get_fd_drive_type(fd_type[1]); | |
552 | rtc_set_memory(rtc_state, 0x10, val); | |
553 | ||
554 | val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); | |
555 | nb = 0; | |
556 | if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { | |
557 | nb++; | |
558 | } | |
559 | if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { | |
560 | nb++; | |
561 | } | |
562 | switch (nb) { | |
563 | case 0: | |
564 | break; | |
565 | case 1: | |
566 | val |= 0x01; /* 1 drive, ready for boot */ | |
567 | break; | |
568 | case 2: | |
569 | val |= 0x41; /* 2 drives, ready for boot */ | |
570 | break; | |
571 | } | |
572 | rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); | |
573 | } | |
574 | ||
575 | typedef struct pc_cmos_init_late_arg { | |
576 | ISADevice *rtc_state; | |
577 | BusState *idebus[2]; | |
578 | } pc_cmos_init_late_arg; | |
579 | ||
580 | typedef struct check_fdc_state { | |
581 | ISADevice *floppy; | |
582 | bool multiple; | |
583 | } CheckFdcState; | |
584 | ||
585 | static int check_fdc(Object *obj, void *opaque) | |
586 | { | |
587 | CheckFdcState *state = opaque; | |
588 | Object *fdc; | |
589 | uint32_t iobase; | |
590 | Error *local_err = NULL; | |
591 | ||
592 | fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); | |
593 | if (!fdc) { | |
594 | return 0; | |
595 | } | |
596 | ||
597 | iobase = object_property_get_uint(obj, "iobase", &local_err); | |
598 | if (local_err || iobase != 0x3f0) { | |
599 | error_free(local_err); | |
600 | return 0; | |
601 | } | |
602 | ||
603 | if (state->floppy) { | |
604 | state->multiple = true; | |
605 | } else { | |
606 | state->floppy = ISA_DEVICE(obj); | |
607 | } | |
608 | return 0; | |
609 | } | |
610 | ||
611 | static const char * const fdc_container_path[] = { | |
612 | "/unattached", "/peripheral", "/peripheral-anon" | |
613 | }; | |
614 | ||
615 | /* | |
616 | * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers | |
617 | * and ACPI objects. | |
618 | */ | |
619 | ISADevice *pc_find_fdc0(void) | |
620 | { | |
621 | int i; | |
622 | Object *container; | |
623 | CheckFdcState state = { 0 }; | |
624 | ||
625 | for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { | |
626 | container = container_get(qdev_get_machine(), fdc_container_path[i]); | |
627 | object_child_foreach(container, check_fdc, &state); | |
628 | } | |
629 | ||
630 | if (state.multiple) { | |
631 | warn_report("multiple floppy disk controllers with " | |
632 | "iobase=0x3f0 have been found"); | |
633 | error_printf("the one being picked for CMOS setup might not reflect " | |
634 | "your intent"); | |
635 | } | |
636 | ||
637 | return state.floppy; | |
638 | } | |
639 | ||
640 | static void pc_cmos_init_late(void *opaque) | |
641 | { | |
642 | pc_cmos_init_late_arg *arg = opaque; | |
643 | ISADevice *s = arg->rtc_state; | |
644 | int16_t cylinders; | |
645 | int8_t heads, sectors; | |
646 | int val; | |
647 | int i, trans; | |
648 | ||
649 | val = 0; | |
650 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, | |
651 | &cylinders, &heads, §ors) >= 0) { | |
652 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); | |
653 | val |= 0xf0; | |
654 | } | |
655 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, | |
656 | &cylinders, &heads, §ors) >= 0) { | |
657 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); | |
658 | val |= 0x0f; | |
659 | } | |
660 | rtc_set_memory(s, 0x12, val); | |
661 | ||
662 | val = 0; | |
663 | for (i = 0; i < 4; i++) { | |
664 | /* NOTE: ide_get_geometry() returns the physical | |
665 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
666 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
667 | geometry can be different if a translation is done. */ | |
668 | if (arg->idebus[i / 2] && | |
669 | ide_get_geometry(arg->idebus[i / 2], i % 2, | |
670 | &cylinders, &heads, §ors) >= 0) { | |
671 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; | |
672 | assert((trans & ~3) == 0); | |
673 | val |= trans << (i * 2); | |
674 | } | |
675 | } | |
676 | rtc_set_memory(s, 0x39, val); | |
677 | ||
678 | pc_cmos_init_floppy(s, pc_find_fdc0()); | |
679 | ||
680 | qemu_unregister_reset(pc_cmos_init_late, opaque); | |
681 | } | |
682 | ||
683 | void pc_cmos_init(PCMachineState *pcms, | |
684 | BusState *idebus0, BusState *idebus1, | |
685 | ISADevice *s) | |
686 | { | |
687 | int val; | |
688 | static pc_cmos_init_late_arg arg; | |
689 | ||
690 | /* various important CMOS locations needed by PC/Bochs bios */ | |
691 | ||
692 | /* memory size */ | |
693 | /* base memory (first MiB) */ | |
694 | val = MIN(pcms->below_4g_mem_size / KiB, 640); | |
695 | rtc_set_memory(s, 0x15, val); | |
696 | rtc_set_memory(s, 0x16, val >> 8); | |
697 | /* extended memory (next 64MiB) */ | |
698 | if (pcms->below_4g_mem_size > 1 * MiB) { | |
699 | val = (pcms->below_4g_mem_size - 1 * MiB) / KiB; | |
700 | } else { | |
701 | val = 0; | |
702 | } | |
703 | if (val > 65535) | |
704 | val = 65535; | |
705 | rtc_set_memory(s, 0x17, val); | |
706 | rtc_set_memory(s, 0x18, val >> 8); | |
707 | rtc_set_memory(s, 0x30, val); | |
708 | rtc_set_memory(s, 0x31, val >> 8); | |
709 | /* memory between 16MiB and 4GiB */ | |
710 | if (pcms->below_4g_mem_size > 16 * MiB) { | |
711 | val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB); | |
712 | } else { | |
713 | val = 0; | |
714 | } | |
715 | if (val > 65535) | |
716 | val = 65535; | |
717 | rtc_set_memory(s, 0x34, val); | |
718 | rtc_set_memory(s, 0x35, val >> 8); | |
719 | /* memory above 4GiB */ | |
720 | val = pcms->above_4g_mem_size / 65536; | |
721 | rtc_set_memory(s, 0x5b, val); | |
722 | rtc_set_memory(s, 0x5c, val >> 8); | |
723 | rtc_set_memory(s, 0x5d, val >> 16); | |
724 | ||
725 | object_property_add_link(OBJECT(pcms), "rtc_state", | |
726 | TYPE_ISA_DEVICE, | |
727 | (Object **)&pcms->rtc, | |
728 | object_property_allow_set_link, | |
729 | OBJ_PROP_LINK_STRONG, &error_abort); | |
730 | object_property_set_link(OBJECT(pcms), OBJECT(s), | |
731 | "rtc_state", &error_abort); | |
732 | ||
733 | set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); | |
734 | ||
735 | val = 0; | |
736 | val |= 0x02; /* FPU is there */ | |
737 | val |= 0x04; /* PS/2 mouse installed */ | |
738 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
739 | ||
740 | /* hard drives and FDC */ | |
741 | arg.rtc_state = s; | |
742 | arg.idebus[0] = idebus0; | |
743 | arg.idebus[1] = idebus1; | |
744 | qemu_register_reset(pc_cmos_init_late, &arg); | |
745 | } | |
746 | ||
747 | #define TYPE_PORT92 "port92" | |
748 | #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) | |
749 | ||
750 | /* port 92 stuff: could be split off */ | |
751 | typedef struct Port92State { | |
752 | ISADevice parent_obj; | |
753 | ||
754 | MemoryRegion io; | |
755 | uint8_t outport; | |
756 | qemu_irq a20_out; | |
757 | } Port92State; | |
758 | ||
759 | static void port92_write(void *opaque, hwaddr addr, uint64_t val, | |
760 | unsigned size) | |
761 | { | |
762 | Port92State *s = opaque; | |
763 | int oldval = s->outport; | |
764 | ||
765 | DPRINTF("port92: write 0x%02" PRIx64 "\n", val); | |
766 | s->outport = val; | |
767 | qemu_set_irq(s->a20_out, (val >> 1) & 1); | |
768 | if ((val & 1) && !(oldval & 1)) { | |
769 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | |
770 | } | |
771 | } | |
772 | ||
773 | static uint64_t port92_read(void *opaque, hwaddr addr, | |
774 | unsigned size) | |
775 | { | |
776 | Port92State *s = opaque; | |
777 | uint32_t ret; | |
778 | ||
779 | ret = s->outport; | |
780 | DPRINTF("port92: read 0x%02x\n", ret); | |
781 | return ret; | |
782 | } | |
783 | ||
784 | static void port92_init(ISADevice *dev, qemu_irq a20_out) | |
785 | { | |
786 | qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); | |
787 | } | |
788 | ||
789 | static const VMStateDescription vmstate_port92_isa = { | |
790 | .name = "port92", | |
791 | .version_id = 1, | |
792 | .minimum_version_id = 1, | |
793 | .fields = (VMStateField[]) { | |
794 | VMSTATE_UINT8(outport, Port92State), | |
795 | VMSTATE_END_OF_LIST() | |
796 | } | |
797 | }; | |
798 | ||
799 | static void port92_reset(DeviceState *d) | |
800 | { | |
801 | Port92State *s = PORT92(d); | |
802 | ||
803 | s->outport &= ~1; | |
804 | } | |
805 | ||
806 | static const MemoryRegionOps port92_ops = { | |
807 | .read = port92_read, | |
808 | .write = port92_write, | |
809 | .impl = { | |
810 | .min_access_size = 1, | |
811 | .max_access_size = 1, | |
812 | }, | |
813 | .endianness = DEVICE_LITTLE_ENDIAN, | |
814 | }; | |
815 | ||
816 | static void port92_initfn(Object *obj) | |
817 | { | |
818 | Port92State *s = PORT92(obj); | |
819 | ||
820 | memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); | |
821 | ||
822 | s->outport = 0; | |
823 | ||
824 | qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); | |
825 | } | |
826 | ||
827 | static void port92_realizefn(DeviceState *dev, Error **errp) | |
828 | { | |
829 | ISADevice *isadev = ISA_DEVICE(dev); | |
830 | Port92State *s = PORT92(dev); | |
831 | ||
832 | isa_register_ioport(isadev, &s->io, 0x92); | |
833 | } | |
834 | ||
835 | static void port92_class_initfn(ObjectClass *klass, void *data) | |
836 | { | |
837 | DeviceClass *dc = DEVICE_CLASS(klass); | |
838 | ||
839 | dc->realize = port92_realizefn; | |
840 | dc->reset = port92_reset; | |
841 | dc->vmsd = &vmstate_port92_isa; | |
842 | /* | |
843 | * Reason: unlike ordinary ISA devices, this one needs additional | |
844 | * wiring: its A20 output line needs to be wired up by | |
845 | * port92_init(). | |
846 | */ | |
847 | dc->user_creatable = false; | |
848 | } | |
849 | ||
850 | static const TypeInfo port92_info = { | |
851 | .name = TYPE_PORT92, | |
852 | .parent = TYPE_ISA_DEVICE, | |
853 | .instance_size = sizeof(Port92State), | |
854 | .instance_init = port92_initfn, | |
855 | .class_init = port92_class_initfn, | |
856 | }; | |
857 | ||
858 | static void port92_register_types(void) | |
859 | { | |
860 | type_register_static(&port92_info); | |
861 | } | |
862 | ||
863 | type_init(port92_register_types) | |
864 | ||
865 | static void handle_a20_line_change(void *opaque, int irq, int level) | |
866 | { | |
867 | X86CPU *cpu = opaque; | |
868 | ||
869 | /* XXX: send to all CPUs ? */ | |
870 | /* XXX: add logic to handle multiple A20 line sources */ | |
871 | x86_cpu_set_a20(cpu, level); | |
872 | } | |
873 | ||
874 | int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) | |
875 | { | |
876 | int index = le32_to_cpu(e820_reserve.count); | |
877 | struct e820_entry *entry; | |
878 | ||
879 | if (type != E820_RAM) { | |
880 | /* old FW_CFG_E820_TABLE entry -- reservations only */ | |
881 | if (index >= E820_NR_ENTRIES) { | |
882 | return -EBUSY; | |
883 | } | |
884 | entry = &e820_reserve.entry[index++]; | |
885 | ||
886 | entry->address = cpu_to_le64(address); | |
887 | entry->length = cpu_to_le64(length); | |
888 | entry->type = cpu_to_le32(type); | |
889 | ||
890 | e820_reserve.count = cpu_to_le32(index); | |
891 | } | |
892 | ||
893 | /* new "etc/e820" file -- include ram too */ | |
894 | e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); | |
895 | e820_table[e820_entries].address = cpu_to_le64(address); | |
896 | e820_table[e820_entries].length = cpu_to_le64(length); | |
897 | e820_table[e820_entries].type = cpu_to_le32(type); | |
898 | e820_entries++; | |
899 | ||
900 | return e820_entries; | |
901 | } | |
902 | ||
903 | int e820_get_num_entries(void) | |
904 | { | |
905 | return e820_entries; | |
906 | } | |
907 | ||
908 | bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) | |
909 | { | |
910 | if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { | |
911 | *address = le64_to_cpu(e820_table[idx].address); | |
912 | *length = le64_to_cpu(e820_table[idx].length); | |
913 | return true; | |
914 | } | |
915 | return false; | |
916 | } | |
917 | ||
918 | /* Calculates initial APIC ID for a specific CPU index | |
919 | * | |
920 | * Currently we need to be able to calculate the APIC ID from the CPU index | |
921 | * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have | |
922 | * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of | |
923 | * all CPUs up to max_cpus. | |
924 | */ | |
925 | static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms, | |
926 | unsigned int cpu_index) | |
927 | { | |
928 | MachineState *ms = MACHINE(pcms); | |
929 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
930 | uint32_t correct_id; | |
931 | static bool warned; | |
932 | ||
933 | correct_id = x86_apicid_from_cpu_idx(ms->smp.cores, | |
934 | ms->smp.threads, cpu_index); | |
935 | if (pcmc->compat_apic_id_mode) { | |
936 | if (cpu_index != correct_id && !warned && !qtest_enabled()) { | |
937 | error_report("APIC IDs set in compatibility mode, " | |
938 | "CPU topology won't match the configuration"); | |
939 | warned = true; | |
940 | } | |
941 | return cpu_index; | |
942 | } else { | |
943 | return correct_id; | |
944 | } | |
945 | } | |
946 | ||
947 | static void pc_build_smbios(PCMachineState *pcms) | |
948 | { | |
949 | uint8_t *smbios_tables, *smbios_anchor; | |
950 | size_t smbios_tables_len, smbios_anchor_len; | |
951 | struct smbios_phys_mem_area *mem_array; | |
952 | unsigned i, array_count; | |
953 | MachineState *ms = MACHINE(pcms); | |
954 | X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); | |
955 | ||
956 | /* tell smbios about cpuid version and features */ | |
957 | smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); | |
958 | ||
959 | smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len); | |
960 | if (smbios_tables) { | |
961 | fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES, | |
962 | smbios_tables, smbios_tables_len); | |
963 | } | |
964 | ||
965 | /* build the array of physical mem area from e820 table */ | |
966 | mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); | |
967 | for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { | |
968 | uint64_t addr, len; | |
969 | ||
970 | if (e820_get_entry(i, E820_RAM, &addr, &len)) { | |
971 | mem_array[array_count].address = addr; | |
972 | mem_array[array_count].length = len; | |
973 | array_count++; | |
974 | } | |
975 | } | |
976 | smbios_get_tables(ms, mem_array, array_count, | |
977 | &smbios_tables, &smbios_tables_len, | |
978 | &smbios_anchor, &smbios_anchor_len); | |
979 | g_free(mem_array); | |
980 | ||
981 | if (smbios_anchor) { | |
982 | fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables", | |
983 | smbios_tables, smbios_tables_len); | |
984 | fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor", | |
985 | smbios_anchor, smbios_anchor_len); | |
986 | } | |
987 | } | |
988 | ||
989 | static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) | |
990 | { | |
991 | FWCfgState *fw_cfg; | |
992 | uint64_t *numa_fw_cfg; | |
993 | int i; | |
994 | const CPUArchIdList *cpus; | |
995 | MachineClass *mc = MACHINE_GET_CLASS(pcms); | |
996 | ||
997 | fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); | |
998 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); | |
999 | ||
1000 | /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: | |
1001 | * | |
1002 | * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for | |
1003 | * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, | |
1004 | * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface | |
1005 | * for CPU hotplug also uses APIC ID and not "CPU index". | |
1006 | * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", | |
1007 | * but the "limit to the APIC ID values SeaBIOS may see". | |
1008 | * | |
1009 | * So for compatibility reasons with old BIOSes we are stuck with | |
1010 | * "etc/max-cpus" actually being apic_id_limit | |
1011 | */ | |
1012 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); | |
1013 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); | |
1014 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, | |
1015 | acpi_tables, acpi_tables_len); | |
1016 | fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); | |
1017 | ||
1018 | fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, | |
1019 | &e820_reserve, sizeof(e820_reserve)); | |
1020 | fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, | |
1021 | sizeof(struct e820_entry) * e820_entries); | |
1022 | ||
1023 | fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); | |
1024 | /* allocate memory for the NUMA channel: one (64bit) word for the number | |
1025 | * of nodes, one word for each VCPU->node and one word for each node to | |
1026 | * hold the amount of memory. | |
1027 | */ | |
1028 | numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); | |
1029 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); | |
1030 | cpus = mc->possible_cpu_arch_ids(MACHINE(pcms)); | |
1031 | for (i = 0; i < cpus->len; i++) { | |
1032 | unsigned int apic_id = cpus->cpus[i].arch_id; | |
1033 | assert(apic_id < pcms->apic_id_limit); | |
1034 | numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); | |
1035 | } | |
1036 | for (i = 0; i < nb_numa_nodes; i++) { | |
1037 | numa_fw_cfg[pcms->apic_id_limit + 1 + i] = | |
1038 | cpu_to_le64(numa_info[i].node_mem); | |
1039 | } | |
1040 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, | |
1041 | (1 + pcms->apic_id_limit + nb_numa_nodes) * | |
1042 | sizeof(*numa_fw_cfg)); | |
1043 | ||
1044 | return fw_cfg; | |
1045 | } | |
1046 | ||
1047 | static long get_file_size(FILE *f) | |
1048 | { | |
1049 | long where, size; | |
1050 | ||
1051 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
1052 | ||
1053 | where = ftell(f); | |
1054 | fseek(f, 0, SEEK_END); | |
1055 | size = ftell(f); | |
1056 | fseek(f, where, SEEK_SET); | |
1057 | ||
1058 | return size; | |
1059 | } | |
1060 | ||
1061 | struct setup_data { | |
1062 | uint64_t next; | |
1063 | uint32_t type; | |
1064 | uint32_t len; | |
1065 | uint8_t data[0]; | |
1066 | } __attribute__((packed)); | |
1067 | ||
1068 | ||
1069 | /* | |
1070 | * The entry point into the kernel for PVH boot is different from | |
1071 | * the native entry point. The PVH entry is defined by the x86/HVM | |
1072 | * direct boot ABI and is available in an ELFNOTE in the kernel binary. | |
1073 | * | |
1074 | * This function is passed to load_elf() when it is called from | |
1075 | * load_elfboot() which then additionally checks for an ELF Note of | |
1076 | * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to | |
1077 | * parse the PVH entry address from the ELF Note. | |
1078 | * | |
1079 | * Due to trickery in elf_opts.h, load_elf() is actually available as | |
1080 | * load_elf32() or load_elf64() and this routine needs to be able | |
1081 | * to deal with being called as 32 or 64 bit. | |
1082 | * | |
1083 | * The address of the PVH entry point is saved to the 'pvh_start_addr' | |
1084 | * global variable. (although the entry point is 32-bit, the kernel | |
1085 | * binary can be either 32-bit or 64-bit). | |
1086 | */ | |
1087 | static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64) | |
1088 | { | |
1089 | size_t *elf_note_data_addr; | |
1090 | ||
1091 | /* Check if ELF Note header passed in is valid */ | |
1092 | if (arg1 == NULL) { | |
1093 | return 0; | |
1094 | } | |
1095 | ||
1096 | if (is64) { | |
1097 | struct elf64_note *nhdr64 = (struct elf64_note *)arg1; | |
1098 | uint64_t nhdr_size64 = sizeof(struct elf64_note); | |
1099 | uint64_t phdr_align = *(uint64_t *)arg2; | |
1100 | uint64_t nhdr_namesz = nhdr64->n_namesz; | |
1101 | ||
1102 | elf_note_data_addr = | |
1103 | ((void *)nhdr64) + nhdr_size64 + | |
1104 | QEMU_ALIGN_UP(nhdr_namesz, phdr_align); | |
1105 | } else { | |
1106 | struct elf32_note *nhdr32 = (struct elf32_note *)arg1; | |
1107 | uint32_t nhdr_size32 = sizeof(struct elf32_note); | |
1108 | uint32_t phdr_align = *(uint32_t *)arg2; | |
1109 | uint32_t nhdr_namesz = nhdr32->n_namesz; | |
1110 | ||
1111 | elf_note_data_addr = | |
1112 | ((void *)nhdr32) + nhdr_size32 + | |
1113 | QEMU_ALIGN_UP(nhdr_namesz, phdr_align); | |
1114 | } | |
1115 | ||
1116 | pvh_start_addr = *elf_note_data_addr; | |
1117 | ||
1118 | return pvh_start_addr; | |
1119 | } | |
1120 | ||
1121 | static bool load_elfboot(const char *kernel_filename, | |
1122 | int kernel_file_size, | |
1123 | uint8_t *header, | |
1124 | size_t pvh_xen_start_addr, | |
1125 | FWCfgState *fw_cfg) | |
1126 | { | |
1127 | uint32_t flags = 0; | |
1128 | uint32_t mh_load_addr = 0; | |
1129 | uint32_t elf_kernel_size = 0; | |
1130 | uint64_t elf_entry; | |
1131 | uint64_t elf_low, elf_high; | |
1132 | int kernel_size; | |
1133 | ||
1134 | if (ldl_p(header) != 0x464c457f) { | |
1135 | return false; /* no elfboot */ | |
1136 | } | |
1137 | ||
1138 | bool elf_is64 = header[EI_CLASS] == ELFCLASS64; | |
1139 | flags = elf_is64 ? | |
1140 | ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags; | |
1141 | ||
1142 | if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */ | |
1143 | error_report("elfboot unsupported flags = %x", flags); | |
1144 | exit(1); | |
1145 | } | |
1146 | ||
1147 | uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY; | |
1148 | kernel_size = load_elf(kernel_filename, read_pvh_start_addr, | |
1149 | NULL, &elf_note_type, &elf_entry, | |
1150 | &elf_low, &elf_high, 0, I386_ELF_MACHINE, | |
1151 | 0, 0); | |
1152 | ||
1153 | if (kernel_size < 0) { | |
1154 | error_report("Error while loading elf kernel"); | |
1155 | exit(1); | |
1156 | } | |
1157 | mh_load_addr = elf_low; | |
1158 | elf_kernel_size = elf_high - elf_low; | |
1159 | ||
1160 | if (pvh_start_addr == 0) { | |
1161 | error_report("Error loading uncompressed kernel without PVH ELF Note"); | |
1162 | exit(1); | |
1163 | } | |
1164 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr); | |
1165 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr); | |
1166 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size); | |
1167 | ||
1168 | return true; | |
1169 | } | |
1170 | ||
1171 | static void load_linux(PCMachineState *pcms, | |
1172 | FWCfgState *fw_cfg) | |
1173 | { | |
1174 | uint16_t protocol; | |
1175 | int setup_size, kernel_size, cmdline_size; | |
1176 | int dtb_size, setup_data_offset; | |
1177 | uint32_t initrd_max; | |
1178 | uint8_t header[8192], *setup, *kernel; | |
1179 | hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; | |
1180 | FILE *f; | |
1181 | char *vmode; | |
1182 | MachineState *machine = MACHINE(pcms); | |
1183 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
1184 | struct setup_data *setup_data; | |
1185 | const char *kernel_filename = machine->kernel_filename; | |
1186 | const char *initrd_filename = machine->initrd_filename; | |
1187 | const char *dtb_filename = machine->dtb; | |
1188 | const char *kernel_cmdline = machine->kernel_cmdline; | |
1189 | ||
1190 | /* Align to 16 bytes as a paranoia measure */ | |
1191 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
1192 | ||
1193 | /* load the kernel header */ | |
1194 | f = fopen(kernel_filename, "rb"); | |
1195 | if (!f || !(kernel_size = get_file_size(f)) || | |
1196 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != | |
1197 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
1198 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", | |
1199 | kernel_filename, strerror(errno)); | |
1200 | exit(1); | |
1201 | } | |
1202 | ||
1203 | /* kernel protocol version */ | |
1204 | #if 0 | |
1205 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); | |
1206 | #endif | |
1207 | if (ldl_p(header+0x202) == 0x53726448) { | |
1208 | protocol = lduw_p(header+0x206); | |
1209 | } else { | |
1210 | /* | |
1211 | * This could be a multiboot kernel. If it is, let's stop treating it | |
1212 | * like a Linux kernel. | |
1213 | * Note: some multiboot images could be in the ELF format (the same of | |
1214 | * PVH), so we try multiboot first since we check the multiboot magic | |
1215 | * header before to load it. | |
1216 | */ | |
1217 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, | |
1218 | kernel_cmdline, kernel_size, header)) { | |
1219 | return; | |
1220 | } | |
1221 | /* | |
1222 | * Check if the file is an uncompressed kernel file (ELF) and load it, | |
1223 | * saving the PVH entry point used by the x86/HVM direct boot ABI. | |
1224 | * If load_elfboot() is successful, populate the fw_cfg info. | |
1225 | */ | |
1226 | if (pcmc->pvh_enabled && | |
1227 | load_elfboot(kernel_filename, kernel_size, | |
1228 | header, pvh_start_addr, fw_cfg)) { | |
1229 | fclose(f); | |
1230 | ||
1231 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, | |
1232 | strlen(kernel_cmdline) + 1); | |
1233 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); | |
1234 | ||
1235 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header)); | |
1236 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, | |
1237 | header, sizeof(header)); | |
1238 | ||
1239 | /* load initrd */ | |
1240 | if (initrd_filename) { | |
1241 | gsize initrd_size; | |
1242 | gchar *initrd_data; | |
1243 | GError *gerr = NULL; | |
1244 | ||
1245 | if (!g_file_get_contents(initrd_filename, &initrd_data, | |
1246 | &initrd_size, &gerr)) { | |
1247 | fprintf(stderr, "qemu: error reading initrd %s: %s\n", | |
1248 | initrd_filename, gerr->message); | |
1249 | exit(1); | |
1250 | } | |
1251 | ||
1252 | initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; | |
1253 | if (initrd_size >= initrd_max) { | |
1254 | fprintf(stderr, "qemu: initrd is too large, cannot support." | |
1255 | "(max: %"PRIu32", need %"PRId64")\n", | |
1256 | initrd_max, (uint64_t)initrd_size); | |
1257 | exit(1); | |
1258 | } | |
1259 | ||
1260 | initrd_addr = (initrd_max - initrd_size) & ~4095; | |
1261 | ||
1262 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
1263 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
1264 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, | |
1265 | initrd_size); | |
1266 | } | |
1267 | ||
1268 | option_rom[nb_option_roms].bootindex = 0; | |
1269 | option_rom[nb_option_roms].name = "pvh.bin"; | |
1270 | nb_option_roms++; | |
1271 | ||
1272 | return; | |
1273 | } | |
1274 | protocol = 0; | |
1275 | } | |
1276 | ||
1277 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
1278 | /* Low kernel */ | |
1279 | real_addr = 0x90000; | |
1280 | cmdline_addr = 0x9a000 - cmdline_size; | |
1281 | prot_addr = 0x10000; | |
1282 | } else if (protocol < 0x202) { | |
1283 | /* High but ancient kernel */ | |
1284 | real_addr = 0x90000; | |
1285 | cmdline_addr = 0x9a000 - cmdline_size; | |
1286 | prot_addr = 0x100000; | |
1287 | } else { | |
1288 | /* High and recent kernel */ | |
1289 | real_addr = 0x10000; | |
1290 | cmdline_addr = 0x20000; | |
1291 | prot_addr = 0x100000; | |
1292 | } | |
1293 | ||
1294 | #if 0 | |
1295 | fprintf(stderr, | |
1296 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" | |
1297 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
1298 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
1299 | real_addr, | |
1300 | cmdline_addr, | |
1301 | prot_addr); | |
1302 | #endif | |
1303 | ||
1304 | /* highest address for loading the initrd */ | |
1305 | if (protocol >= 0x20c && | |
1306 | lduw_p(header+0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { | |
1307 | /* | |
1308 | * Linux has supported initrd up to 4 GB for a very long time (2007, | |
1309 | * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), | |
1310 | * though it only sets initrd_max to 2 GB to "work around bootloader | |
1311 | * bugs". Luckily, QEMU firmware(which does something like bootloader) | |
1312 | * has supported this. | |
1313 | * | |
1314 | * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can | |
1315 | * be loaded into any address. | |
1316 | * | |
1317 | * In addition, initrd_max is uint32_t simply because QEMU doesn't | |
1318 | * support the 64-bit boot protocol (specifically the ext_ramdisk_image | |
1319 | * field). | |
1320 | * | |
1321 | * Therefore here just limit initrd_max to UINT32_MAX simply as well. | |
1322 | */ | |
1323 | initrd_max = UINT32_MAX; | |
1324 | } else if (protocol >= 0x203) { | |
1325 | initrd_max = ldl_p(header+0x22c); | |
1326 | } else { | |
1327 | initrd_max = 0x37ffffff; | |
1328 | } | |
1329 | ||
1330 | if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { | |
1331 | initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; | |
1332 | } | |
1333 | ||
1334 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); | |
1335 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); | |
1336 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); | |
1337 | ||
1338 | if (protocol >= 0x202) { | |
1339 | stl_p(header+0x228, cmdline_addr); | |
1340 | } else { | |
1341 | stw_p(header+0x20, 0xA33F); | |
1342 | stw_p(header+0x22, cmdline_addr-real_addr); | |
1343 | } | |
1344 | ||
1345 | /* handle vga= parameter */ | |
1346 | vmode = strstr(kernel_cmdline, "vga="); | |
1347 | if (vmode) { | |
1348 | unsigned int video_mode; | |
1349 | /* skip "vga=" */ | |
1350 | vmode += 4; | |
1351 | if (!strncmp(vmode, "normal", 6)) { | |
1352 | video_mode = 0xffff; | |
1353 | } else if (!strncmp(vmode, "ext", 3)) { | |
1354 | video_mode = 0xfffe; | |
1355 | } else if (!strncmp(vmode, "ask", 3)) { | |
1356 | video_mode = 0xfffd; | |
1357 | } else { | |
1358 | video_mode = strtol(vmode, NULL, 0); | |
1359 | } | |
1360 | stw_p(header+0x1fa, video_mode); | |
1361 | } | |
1362 | ||
1363 | /* loader type */ | |
1364 | /* High nybble = B reserved for QEMU; low nybble is revision number. | |
1365 | If this code is substantially changed, you may want to consider | |
1366 | incrementing the revision. */ | |
1367 | if (protocol >= 0x200) { | |
1368 | header[0x210] = 0xB0; | |
1369 | } | |
1370 | /* heap */ | |
1371 | if (protocol >= 0x201) { | |
1372 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ | |
1373 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
1374 | } | |
1375 | ||
1376 | /* load initrd */ | |
1377 | if (initrd_filename) { | |
1378 | gsize initrd_size; | |
1379 | gchar *initrd_data; | |
1380 | GError *gerr = NULL; | |
1381 | ||
1382 | if (protocol < 0x200) { | |
1383 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
1384 | exit(1); | |
1385 | } | |
1386 | ||
1387 | if (!g_file_get_contents(initrd_filename, &initrd_data, | |
1388 | &initrd_size, &gerr)) { | |
1389 | fprintf(stderr, "qemu: error reading initrd %s: %s\n", | |
1390 | initrd_filename, gerr->message); | |
1391 | exit(1); | |
1392 | } | |
1393 | if (initrd_size >= initrd_max) { | |
1394 | fprintf(stderr, "qemu: initrd is too large, cannot support." | |
1395 | "(max: %"PRIu32", need %"PRId64")\n", | |
1396 | initrd_max, (uint64_t)initrd_size); | |
1397 | exit(1); | |
1398 | } | |
1399 | ||
1400 | initrd_addr = (initrd_max-initrd_size) & ~4095; | |
1401 | ||
1402 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
1403 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
1404 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
1405 | ||
1406 | stl_p(header+0x218, initrd_addr); | |
1407 | stl_p(header+0x21c, initrd_size); | |
1408 | } | |
1409 | ||
1410 | /* load kernel and setup */ | |
1411 | setup_size = header[0x1f1]; | |
1412 | if (setup_size == 0) { | |
1413 | setup_size = 4; | |
1414 | } | |
1415 | setup_size = (setup_size+1)*512; | |
1416 | if (setup_size > kernel_size) { | |
1417 | fprintf(stderr, "qemu: invalid kernel header\n"); | |
1418 | exit(1); | |
1419 | } | |
1420 | kernel_size -= setup_size; | |
1421 | ||
1422 | setup = g_malloc(setup_size); | |
1423 | kernel = g_malloc(kernel_size); | |
1424 | fseek(f, 0, SEEK_SET); | |
1425 | if (fread(setup, 1, setup_size, f) != setup_size) { | |
1426 | fprintf(stderr, "fread() failed\n"); | |
1427 | exit(1); | |
1428 | } | |
1429 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
1430 | fprintf(stderr, "fread() failed\n"); | |
1431 | exit(1); | |
1432 | } | |
1433 | fclose(f); | |
1434 | ||
1435 | /* append dtb to kernel */ | |
1436 | if (dtb_filename) { | |
1437 | if (protocol < 0x209) { | |
1438 | fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); | |
1439 | exit(1); | |
1440 | } | |
1441 | ||
1442 | dtb_size = get_image_size(dtb_filename); | |
1443 | if (dtb_size <= 0) { | |
1444 | fprintf(stderr, "qemu: error reading dtb %s: %s\n", | |
1445 | dtb_filename, strerror(errno)); | |
1446 | exit(1); | |
1447 | } | |
1448 | ||
1449 | setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); | |
1450 | kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; | |
1451 | kernel = g_realloc(kernel, kernel_size); | |
1452 | ||
1453 | stq_p(header+0x250, prot_addr + setup_data_offset); | |
1454 | ||
1455 | setup_data = (struct setup_data *)(kernel + setup_data_offset); | |
1456 | setup_data->next = 0; | |
1457 | setup_data->type = cpu_to_le32(SETUP_DTB); | |
1458 | setup_data->len = cpu_to_le32(dtb_size); | |
1459 | ||
1460 | load_image_size(dtb_filename, setup_data->data, dtb_size); | |
1461 | } | |
1462 | ||
1463 | memcpy(setup, header, MIN(sizeof(header), setup_size)); | |
1464 | ||
1465 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
1466 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
1467 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
1468 | ||
1469 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
1470 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
1471 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
1472 | ||
1473 | option_rom[nb_option_roms].bootindex = 0; | |
1474 | option_rom[nb_option_roms].name = "linuxboot.bin"; | |
1475 | if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { | |
1476 | option_rom[nb_option_roms].name = "linuxboot_dma.bin"; | |
1477 | } | |
1478 | nb_option_roms++; | |
1479 | } | |
1480 | ||
1481 | #define NE2000_NB_MAX 6 | |
1482 | ||
1483 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, | |
1484 | 0x280, 0x380 }; | |
1485 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
1486 | ||
1487 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) | |
1488 | { | |
1489 | static int nb_ne2k = 0; | |
1490 | ||
1491 | if (nb_ne2k == NE2000_NB_MAX) | |
1492 | return; | |
1493 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], | |
1494 | ne2000_irq[nb_ne2k], nd); | |
1495 | nb_ne2k++; | |
1496 | } | |
1497 | ||
1498 | DeviceState *cpu_get_current_apic(void) | |
1499 | { | |
1500 | if (current_cpu) { | |
1501 | X86CPU *cpu = X86_CPU(current_cpu); | |
1502 | return cpu->apic_state; | |
1503 | } else { | |
1504 | return NULL; | |
1505 | } | |
1506 | } | |
1507 | ||
1508 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) | |
1509 | { | |
1510 | X86CPU *cpu = opaque; | |
1511 | ||
1512 | if (level) { | |
1513 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); | |
1514 | } | |
1515 | } | |
1516 | ||
1517 | static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp) | |
1518 | { | |
1519 | Object *cpu = NULL; | |
1520 | Error *local_err = NULL; | |
1521 | ||
1522 | cpu = object_new(typename); | |
1523 | ||
1524 | object_property_set_uint(cpu, apic_id, "apic-id", &local_err); | |
1525 | object_property_set_bool(cpu, true, "realized", &local_err); | |
1526 | ||
1527 | object_unref(cpu); | |
1528 | error_propagate(errp, local_err); | |
1529 | } | |
1530 | ||
1531 | void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp) | |
1532 | { | |
1533 | PCMachineState *pcms = PC_MACHINE(ms); | |
1534 | int64_t apic_id = x86_cpu_apic_id_from_index(pcms, id); | |
1535 | Error *local_err = NULL; | |
1536 | ||
1537 | if (id < 0) { | |
1538 | error_setg(errp, "Invalid CPU id: %" PRIi64, id); | |
1539 | return; | |
1540 | } | |
1541 | ||
1542 | if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { | |
1543 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
1544 | ", resulting APIC ID (%" PRIi64 ") is too large", | |
1545 | id, apic_id); | |
1546 | return; | |
1547 | } | |
1548 | ||
1549 | pc_new_cpu(ms->cpu_type, apic_id, &local_err); | |
1550 | if (local_err) { | |
1551 | error_propagate(errp, local_err); | |
1552 | return; | |
1553 | } | |
1554 | } | |
1555 | ||
1556 | void pc_cpus_init(PCMachineState *pcms) | |
1557 | { | |
1558 | int i; | |
1559 | const CPUArchIdList *possible_cpus; | |
1560 | MachineState *ms = MACHINE(pcms); | |
1561 | MachineClass *mc = MACHINE_GET_CLASS(pcms); | |
1562 | ||
1563 | /* Calculates the limit to CPU APIC ID values | |
1564 | * | |
1565 | * Limit for the APIC ID value, so that all | |
1566 | * CPU APIC IDs are < pcms->apic_id_limit. | |
1567 | * | |
1568 | * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). | |
1569 | */ | |
1570 | pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms, | |
1571 | ms->smp.max_cpus - 1) + 1; | |
1572 | possible_cpus = mc->possible_cpu_arch_ids(ms); | |
1573 | for (i = 0; i < ms->smp.cpus; i++) { | |
1574 | pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id, | |
1575 | &error_fatal); | |
1576 | } | |
1577 | } | |
1578 | ||
1579 | static void pc_build_feature_control_file(PCMachineState *pcms) | |
1580 | { | |
1581 | MachineState *ms = MACHINE(pcms); | |
1582 | X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); | |
1583 | CPUX86State *env = &cpu->env; | |
1584 | uint32_t unused, ecx, edx; | |
1585 | uint64_t feature_control_bits = 0; | |
1586 | uint64_t *val; | |
1587 | ||
1588 | cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); | |
1589 | if (ecx & CPUID_EXT_VMX) { | |
1590 | feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
1591 | } | |
1592 | ||
1593 | if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == | |
1594 | (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && | |
1595 | (env->mcg_cap & MCG_LMCE_P)) { | |
1596 | feature_control_bits |= FEATURE_CONTROL_LMCE; | |
1597 | } | |
1598 | ||
1599 | if (!feature_control_bits) { | |
1600 | return; | |
1601 | } | |
1602 | ||
1603 | val = g_malloc(sizeof(*val)); | |
1604 | *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); | |
1605 | fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); | |
1606 | } | |
1607 | ||
1608 | static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) | |
1609 | { | |
1610 | if (cpus_count > 0xff) { | |
1611 | /* If the number of CPUs can't be represented in 8 bits, the | |
1612 | * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just | |
1613 | * to make old BIOSes fail more predictably. | |
1614 | */ | |
1615 | rtc_set_memory(rtc, 0x5f, 0); | |
1616 | } else { | |
1617 | rtc_set_memory(rtc, 0x5f, cpus_count - 1); | |
1618 | } | |
1619 | } | |
1620 | ||
1621 | static | |
1622 | void pc_machine_done(Notifier *notifier, void *data) | |
1623 | { | |
1624 | PCMachineState *pcms = container_of(notifier, | |
1625 | PCMachineState, machine_done); | |
1626 | PCIBus *bus = pcms->bus; | |
1627 | ||
1628 | /* set the number of CPUs */ | |
1629 | rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); | |
1630 | ||
1631 | if (bus) { | |
1632 | int extra_hosts = 0; | |
1633 | ||
1634 | QLIST_FOREACH(bus, &bus->child, sibling) { | |
1635 | /* look for expander root buses */ | |
1636 | if (pci_bus_is_root(bus)) { | |
1637 | extra_hosts++; | |
1638 | } | |
1639 | } | |
1640 | if (extra_hosts && pcms->fw_cfg) { | |
1641 | uint64_t *val = g_malloc(sizeof(*val)); | |
1642 | *val = cpu_to_le64(extra_hosts); | |
1643 | fw_cfg_add_file(pcms->fw_cfg, | |
1644 | "etc/extra-pci-roots", val, sizeof(*val)); | |
1645 | } | |
1646 | } | |
1647 | ||
1648 | acpi_setup(); | |
1649 | if (pcms->fw_cfg) { | |
1650 | pc_build_smbios(pcms); | |
1651 | pc_build_feature_control_file(pcms); | |
1652 | /* update FW_CFG_NB_CPUS to account for -device added CPUs */ | |
1653 | fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); | |
1654 | } | |
1655 | ||
1656 | if (pcms->apic_id_limit > 255 && !xen_enabled()) { | |
1657 | IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); | |
1658 | ||
1659 | if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || | |
1660 | iommu->intr_eim != ON_OFF_AUTO_ON) { | |
1661 | error_report("current -smp configuration requires " | |
1662 | "Extended Interrupt Mode enabled. " | |
1663 | "You can add an IOMMU using: " | |
1664 | "-device intel-iommu,intremap=on,eim=on"); | |
1665 | exit(EXIT_FAILURE); | |
1666 | } | |
1667 | } | |
1668 | } | |
1669 | ||
1670 | void pc_guest_info_init(PCMachineState *pcms) | |
1671 | { | |
1672 | int i; | |
1673 | ||
1674 | pcms->apic_xrupt_override = kvm_allows_irq0_override(); | |
1675 | pcms->numa_nodes = nb_numa_nodes; | |
1676 | pcms->node_mem = g_malloc0(pcms->numa_nodes * | |
1677 | sizeof *pcms->node_mem); | |
1678 | for (i = 0; i < nb_numa_nodes; i++) { | |
1679 | pcms->node_mem[i] = numa_info[i].node_mem; | |
1680 | } | |
1681 | ||
1682 | pcms->machine_done.notify = pc_machine_done; | |
1683 | qemu_add_machine_init_done_notifier(&pcms->machine_done); | |
1684 | } | |
1685 | ||
1686 | /* setup pci memory address space mapping into system address space */ | |
1687 | void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, | |
1688 | MemoryRegion *pci_address_space) | |
1689 | { | |
1690 | /* Set to lower priority than RAM */ | |
1691 | memory_region_add_subregion_overlap(system_memory, 0x0, | |
1692 | pci_address_space, -1); | |
1693 | } | |
1694 | ||
1695 | void xen_load_linux(PCMachineState *pcms) | |
1696 | { | |
1697 | int i; | |
1698 | FWCfgState *fw_cfg; | |
1699 | ||
1700 | assert(MACHINE(pcms)->kernel_filename != NULL); | |
1701 | ||
1702 | fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); | |
1703 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); | |
1704 | rom_set_fw(fw_cfg); | |
1705 | ||
1706 | load_linux(pcms, fw_cfg); | |
1707 | for (i = 0; i < nb_option_roms; i++) { | |
1708 | assert(!strcmp(option_rom[i].name, "linuxboot.bin") || | |
1709 | !strcmp(option_rom[i].name, "linuxboot_dma.bin") || | |
1710 | !strcmp(option_rom[i].name, "pvh.bin") || | |
1711 | !strcmp(option_rom[i].name, "multiboot.bin")); | |
1712 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); | |
1713 | } | |
1714 | pcms->fw_cfg = fw_cfg; | |
1715 | } | |
1716 | ||
1717 | void pc_memory_init(PCMachineState *pcms, | |
1718 | MemoryRegion *system_memory, | |
1719 | MemoryRegion *rom_memory, | |
1720 | MemoryRegion **ram_memory) | |
1721 | { | |
1722 | int linux_boot, i; | |
1723 | MemoryRegion *ram, *option_rom_mr; | |
1724 | MemoryRegion *ram_below_4g, *ram_above_4g; | |
1725 | FWCfgState *fw_cfg; | |
1726 | MachineState *machine = MACHINE(pcms); | |
1727 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
1728 | ||
1729 | assert(machine->ram_size == pcms->below_4g_mem_size + | |
1730 | pcms->above_4g_mem_size); | |
1731 | ||
1732 | linux_boot = (machine->kernel_filename != NULL); | |
1733 | ||
1734 | /* Allocate RAM. We allocate it as a single memory region and use | |
1735 | * aliases to address portions of it, mostly for backwards compatibility | |
1736 | * with older qemus that used qemu_ram_alloc(). | |
1737 | */ | |
1738 | ram = g_malloc(sizeof(*ram)); | |
1739 | memory_region_allocate_system_memory(ram, NULL, "pc.ram", | |
1740 | machine->ram_size); | |
1741 | *ram_memory = ram; | |
1742 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); | |
1743 | memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, | |
1744 | 0, pcms->below_4g_mem_size); | |
1745 | memory_region_add_subregion(system_memory, 0, ram_below_4g); | |
1746 | e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); | |
1747 | if (pcms->above_4g_mem_size > 0) { | |
1748 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); | |
1749 | memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, | |
1750 | pcms->below_4g_mem_size, | |
1751 | pcms->above_4g_mem_size); | |
1752 | memory_region_add_subregion(system_memory, 0x100000000ULL, | |
1753 | ram_above_4g); | |
1754 | e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); | |
1755 | } | |
1756 | ||
1757 | if (!pcmc->has_reserved_memory && | |
1758 | (machine->ram_slots || | |
1759 | (machine->maxram_size > machine->ram_size))) { | |
1760 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
1761 | ||
1762 | error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", | |
1763 | mc->name); | |
1764 | exit(EXIT_FAILURE); | |
1765 | } | |
1766 | ||
1767 | /* always allocate the device memory information */ | |
1768 | machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); | |
1769 | ||
1770 | /* initialize device memory address space */ | |
1771 | if (pcmc->has_reserved_memory && | |
1772 | (machine->ram_size < machine->maxram_size)) { | |
1773 | ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; | |
1774 | ||
1775 | if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { | |
1776 | error_report("unsupported amount of memory slots: %"PRIu64, | |
1777 | machine->ram_slots); | |
1778 | exit(EXIT_FAILURE); | |
1779 | } | |
1780 | ||
1781 | if (QEMU_ALIGN_UP(machine->maxram_size, | |
1782 | TARGET_PAGE_SIZE) != machine->maxram_size) { | |
1783 | error_report("maximum memory size must by aligned to multiple of " | |
1784 | "%d bytes", TARGET_PAGE_SIZE); | |
1785 | exit(EXIT_FAILURE); | |
1786 | } | |
1787 | ||
1788 | machine->device_memory->base = | |
1789 | ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB); | |
1790 | ||
1791 | if (pcmc->enforce_aligned_dimm) { | |
1792 | /* size device region assuming 1G page max alignment per slot */ | |
1793 | device_mem_size += (1 * GiB) * machine->ram_slots; | |
1794 | } | |
1795 | ||
1796 | if ((machine->device_memory->base + device_mem_size) < | |
1797 | device_mem_size) { | |
1798 | error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, | |
1799 | machine->maxram_size); | |
1800 | exit(EXIT_FAILURE); | |
1801 | } | |
1802 | ||
1803 | memory_region_init(&machine->device_memory->mr, OBJECT(pcms), | |
1804 | "device-memory", device_mem_size); | |
1805 | memory_region_add_subregion(system_memory, machine->device_memory->base, | |
1806 | &machine->device_memory->mr); | |
1807 | } | |
1808 | ||
1809 | /* Initialize PC system firmware */ | |
1810 | pc_system_firmware_init(pcms, rom_memory); | |
1811 | ||
1812 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); | |
1813 | memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, | |
1814 | &error_fatal); | |
1815 | if (pcmc->pci_enabled) { | |
1816 | memory_region_set_readonly(option_rom_mr, true); | |
1817 | } | |
1818 | memory_region_add_subregion_overlap(rom_memory, | |
1819 | PC_ROM_MIN_VGA, | |
1820 | option_rom_mr, | |
1821 | 1); | |
1822 | ||
1823 | fw_cfg = bochs_bios_init(&address_space_memory, pcms); | |
1824 | ||
1825 | rom_set_fw(fw_cfg); | |
1826 | ||
1827 | if (pcmc->has_reserved_memory && machine->device_memory->base) { | |
1828 | uint64_t *val = g_malloc(sizeof(*val)); | |
1829 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
1830 | uint64_t res_mem_end = machine->device_memory->base; | |
1831 | ||
1832 | if (!pcmc->broken_reserved_end) { | |
1833 | res_mem_end += memory_region_size(&machine->device_memory->mr); | |
1834 | } | |
1835 | *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); | |
1836 | fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); | |
1837 | } | |
1838 | ||
1839 | if (linux_boot) { | |
1840 | load_linux(pcms, fw_cfg); | |
1841 | } | |
1842 | ||
1843 | for (i = 0; i < nb_option_roms; i++) { | |
1844 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); | |
1845 | } | |
1846 | pcms->fw_cfg = fw_cfg; | |
1847 | ||
1848 | /* Init default IOAPIC address space */ | |
1849 | pcms->ioapic_as = &address_space_memory; | |
1850 | } | |
1851 | ||
1852 | /* | |
1853 | * The 64bit pci hole starts after "above 4G RAM" and | |
1854 | * potentially the space reserved for memory hotplug. | |
1855 | */ | |
1856 | uint64_t pc_pci_hole64_start(void) | |
1857 | { | |
1858 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); | |
1859 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
1860 | MachineState *ms = MACHINE(pcms); | |
1861 | uint64_t hole64_start = 0; | |
1862 | ||
1863 | if (pcmc->has_reserved_memory && ms->device_memory->base) { | |
1864 | hole64_start = ms->device_memory->base; | |
1865 | if (!pcmc->broken_reserved_end) { | |
1866 | hole64_start += memory_region_size(&ms->device_memory->mr); | |
1867 | } | |
1868 | } else { | |
1869 | hole64_start = 0x100000000ULL + pcms->above_4g_mem_size; | |
1870 | } | |
1871 | ||
1872 | return ROUND_UP(hole64_start, 1 * GiB); | |
1873 | } | |
1874 | ||
1875 | qemu_irq pc_allocate_cpu_irq(void) | |
1876 | { | |
1877 | return qemu_allocate_irq(pic_irq_request, NULL, 0); | |
1878 | } | |
1879 | ||
1880 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) | |
1881 | { | |
1882 | DeviceState *dev = NULL; | |
1883 | ||
1884 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); | |
1885 | if (pci_bus) { | |
1886 | PCIDevice *pcidev = pci_vga_init(pci_bus); | |
1887 | dev = pcidev ? &pcidev->qdev : NULL; | |
1888 | } else if (isa_bus) { | |
1889 | ISADevice *isadev = isa_vga_init(isa_bus); | |
1890 | dev = isadev ? DEVICE(isadev) : NULL; | |
1891 | } | |
1892 | rom_reset_order_override(); | |
1893 | return dev; | |
1894 | } | |
1895 | ||
1896 | static const MemoryRegionOps ioport80_io_ops = { | |
1897 | .write = ioport80_write, | |
1898 | .read = ioport80_read, | |
1899 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1900 | .impl = { | |
1901 | .min_access_size = 1, | |
1902 | .max_access_size = 1, | |
1903 | }, | |
1904 | }; | |
1905 | ||
1906 | static const MemoryRegionOps ioportF0_io_ops = { | |
1907 | .write = ioportF0_write, | |
1908 | .read = ioportF0_read, | |
1909 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1910 | .impl = { | |
1911 | .min_access_size = 1, | |
1912 | .max_access_size = 1, | |
1913 | }, | |
1914 | }; | |
1915 | ||
1916 | static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) | |
1917 | { | |
1918 | int i; | |
1919 | DriveInfo *fd[MAX_FD]; | |
1920 | qemu_irq *a20_line; | |
1921 | ISADevice *i8042, *port92, *vmmouse; | |
1922 | ||
1923 | serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); | |
1924 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); | |
1925 | ||
1926 | for (i = 0; i < MAX_FD; i++) { | |
1927 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1928 | create_fdctrl |= !!fd[i]; | |
1929 | } | |
1930 | if (create_fdctrl) { | |
1931 | fdctrl_init_isa(isa_bus, fd); | |
1932 | } | |
1933 | ||
1934 | i8042 = isa_create_simple(isa_bus, "i8042"); | |
1935 | if (!no_vmport) { | |
1936 | vmport_init(isa_bus); | |
1937 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1938 | } else { | |
1939 | vmmouse = NULL; | |
1940 | } | |
1941 | if (vmmouse) { | |
1942 | DeviceState *dev = DEVICE(vmmouse); | |
1943 | qdev_prop_set_ptr(dev, "ps2_mouse", i8042); | |
1944 | qdev_init_nofail(dev); | |
1945 | } | |
1946 | port92 = isa_create_simple(isa_bus, "port92"); | |
1947 | ||
1948 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); | |
1949 | i8042_setup_a20_line(i8042, a20_line[0]); | |
1950 | port92_init(port92, a20_line[1]); | |
1951 | g_free(a20_line); | |
1952 | } | |
1953 | ||
1954 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, | |
1955 | ISADevice **rtc_state, | |
1956 | bool create_fdctrl, | |
1957 | bool no_vmport, | |
1958 | bool has_pit, | |
1959 | uint32_t hpet_irqs) | |
1960 | { | |
1961 | int i; | |
1962 | DeviceState *hpet = NULL; | |
1963 | int pit_isa_irq = 0; | |
1964 | qemu_irq pit_alt_irq = NULL; | |
1965 | qemu_irq rtc_irq = NULL; | |
1966 | ISADevice *pit = NULL; | |
1967 | MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); | |
1968 | MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); | |
1969 | ||
1970 | memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); | |
1971 | memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); | |
1972 | ||
1973 | memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); | |
1974 | memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); | |
1975 | ||
1976 | /* | |
1977 | * Check if an HPET shall be created. | |
1978 | * | |
1979 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
1980 | * when the HPET wants to take over. Thus we have to disable the latter. | |
1981 | */ | |
1982 | if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { | |
1983 | /* In order to set property, here not using sysbus_try_create_simple */ | |
1984 | hpet = qdev_try_create(NULL, TYPE_HPET); | |
1985 | if (hpet) { | |
1986 | /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 | |
1987 | * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, | |
1988 | * IRQ8 and IRQ2. | |
1989 | */ | |
1990 | uint8_t compat = object_property_get_uint(OBJECT(hpet), | |
1991 | HPET_INTCAP, NULL); | |
1992 | if (!compat) { | |
1993 | qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); | |
1994 | } | |
1995 | qdev_init_nofail(hpet); | |
1996 | sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); | |
1997 | ||
1998 | for (i = 0; i < GSI_NUM_PINS; i++) { | |
1999 | sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); | |
2000 | } | |
2001 | pit_isa_irq = -1; | |
2002 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
2003 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
2004 | } | |
2005 | } | |
2006 | *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); | |
2007 | ||
2008 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
2009 | ||
2010 | if (!xen_enabled() && has_pit) { | |
2011 | if (kvm_pit_in_kernel()) { | |
2012 | pit = kvm_pit_init(isa_bus, 0x40); | |
2013 | } else { | |
2014 | pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); | |
2015 | } | |
2016 | if (hpet) { | |
2017 | /* connect PIT to output control line of the HPET */ | |
2018 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); | |
2019 | } | |
2020 | pcspk_init(isa_bus, pit); | |
2021 | } | |
2022 | ||
2023 | i8257_dma_init(isa_bus, 0); | |
2024 | ||
2025 | /* Super I/O */ | |
2026 | pc_superio_init(isa_bus, create_fdctrl, no_vmport); | |
2027 | } | |
2028 | ||
2029 | void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) | |
2030 | { | |
2031 | int i; | |
2032 | ||
2033 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); | |
2034 | for (i = 0; i < nb_nics; i++) { | |
2035 | NICInfo *nd = &nd_table[i]; | |
2036 | const char *model = nd->model ? nd->model : pcmc->default_nic_model; | |
2037 | ||
2038 | if (g_str_equal(model, "ne2k_isa")) { | |
2039 | pc_init_ne2k_isa(isa_bus, nd); | |
2040 | } else { | |
2041 | pci_nic_init_nofail(nd, pci_bus, model, NULL); | |
2042 | } | |
2043 | } | |
2044 | rom_reset_order_override(); | |
2045 | } | |
2046 | ||
2047 | void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) | |
2048 | { | |
2049 | DeviceState *dev; | |
2050 | SysBusDevice *d; | |
2051 | unsigned int i; | |
2052 | ||
2053 | if (kvm_ioapic_in_kernel()) { | |
2054 | dev = qdev_create(NULL, TYPE_KVM_IOAPIC); | |
2055 | } else { | |
2056 | dev = qdev_create(NULL, TYPE_IOAPIC); | |
2057 | } | |
2058 | if (parent_name) { | |
2059 | object_property_add_child(object_resolve_path(parent_name, NULL), | |
2060 | "ioapic", OBJECT(dev), NULL); | |
2061 | } | |
2062 | qdev_init_nofail(dev); | |
2063 | d = SYS_BUS_DEVICE(dev); | |
2064 | sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); | |
2065 | ||
2066 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
2067 | gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); | |
2068 | } | |
2069 | } | |
2070 | ||
2071 | static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
2072 | Error **errp) | |
2073 | { | |
2074 | const PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
2075 | const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
2076 | const MachineState *ms = MACHINE(hotplug_dev); | |
2077 | const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); | |
2078 | const uint64_t legacy_align = TARGET_PAGE_SIZE; | |
2079 | Error *local_err = NULL; | |
2080 | ||
2081 | /* | |
2082 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
2083 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
2084 | * addition to cover this case. | |
2085 | */ | |
2086 | if (!pcms->acpi_dev || !acpi_enabled) { | |
2087 | error_setg(errp, | |
2088 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); | |
2089 | return; | |
2090 | } | |
2091 | ||
2092 | if (is_nvdimm && !ms->nvdimms_state->is_enabled) { | |
2093 | error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); | |
2094 | return; | |
2095 | } | |
2096 | ||
2097 | hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err); | |
2098 | if (local_err) { | |
2099 | error_propagate(errp, local_err); | |
2100 | return; | |
2101 | } | |
2102 | ||
2103 | pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), | |
2104 | pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); | |
2105 | } | |
2106 | ||
2107 | static void pc_memory_plug(HotplugHandler *hotplug_dev, | |
2108 | DeviceState *dev, Error **errp) | |
2109 | { | |
2110 | Error *local_err = NULL; | |
2111 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
2112 | MachineState *ms = MACHINE(hotplug_dev); | |
2113 | bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); | |
2114 | ||
2115 | pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); | |
2116 | if (local_err) { | |
2117 | goto out; | |
2118 | } | |
2119 | ||
2120 | if (is_nvdimm) { | |
2121 | nvdimm_plug(ms->nvdimms_state); | |
2122 | } | |
2123 | ||
2124 | hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); | |
2125 | out: | |
2126 | error_propagate(errp, local_err); | |
2127 | } | |
2128 | ||
2129 | static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, | |
2130 | DeviceState *dev, Error **errp) | |
2131 | { | |
2132 | Error *local_err = NULL; | |
2133 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
2134 | ||
2135 | /* | |
2136 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
2137 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
2138 | * addition to cover this case. | |
2139 | */ | |
2140 | if (!pcms->acpi_dev || !acpi_enabled) { | |
2141 | error_setg(&local_err, | |
2142 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); | |
2143 | goto out; | |
2144 | } | |
2145 | ||
2146 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { | |
2147 | error_setg(&local_err, | |
2148 | "nvdimm device hot unplug is not supported yet."); | |
2149 | goto out; | |
2150 | } | |
2151 | ||
2152 | hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, | |
2153 | &local_err); | |
2154 | out: | |
2155 | error_propagate(errp, local_err); | |
2156 | } | |
2157 | ||
2158 | static void pc_memory_unplug(HotplugHandler *hotplug_dev, | |
2159 | DeviceState *dev, Error **errp) | |
2160 | { | |
2161 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
2162 | Error *local_err = NULL; | |
2163 | ||
2164 | hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
2165 | if (local_err) { | |
2166 | goto out; | |
2167 | } | |
2168 | ||
2169 | pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); | |
2170 | object_property_set_bool(OBJECT(dev), false, "realized", NULL); | |
2171 | out: | |
2172 | error_propagate(errp, local_err); | |
2173 | } | |
2174 | ||
2175 | static int pc_apic_cmp(const void *a, const void *b) | |
2176 | { | |
2177 | CPUArchId *apic_a = (CPUArchId *)a; | |
2178 | CPUArchId *apic_b = (CPUArchId *)b; | |
2179 | ||
2180 | return apic_a->arch_id - apic_b->arch_id; | |
2181 | } | |
2182 | ||
2183 | /* returns pointer to CPUArchId descriptor that matches CPU's apic_id | |
2184 | * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no | |
2185 | * entry corresponding to CPU's apic_id returns NULL. | |
2186 | */ | |
2187 | static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) | |
2188 | { | |
2189 | CPUArchId apic_id, *found_cpu; | |
2190 | ||
2191 | apic_id.arch_id = id; | |
2192 | found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, | |
2193 | ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), | |
2194 | pc_apic_cmp); | |
2195 | if (found_cpu && idx) { | |
2196 | *idx = found_cpu - ms->possible_cpus->cpus; | |
2197 | } | |
2198 | return found_cpu; | |
2199 | } | |
2200 | ||
2201 | static void pc_cpu_plug(HotplugHandler *hotplug_dev, | |
2202 | DeviceState *dev, Error **errp) | |
2203 | { | |
2204 | CPUArchId *found_cpu; | |
2205 | Error *local_err = NULL; | |
2206 | X86CPU *cpu = X86_CPU(dev); | |
2207 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
2208 | ||
2209 | if (pcms->acpi_dev) { | |
2210 | hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
2211 | if (local_err) { | |
2212 | goto out; | |
2213 | } | |
2214 | } | |
2215 | ||
2216 | /* increment the number of CPUs */ | |
2217 | pcms->boot_cpus++; | |
2218 | if (pcms->rtc) { | |
2219 | rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); | |
2220 | } | |
2221 | if (pcms->fw_cfg) { | |
2222 | fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); | |
2223 | } | |
2224 | ||
2225 | found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); | |
2226 | found_cpu->cpu = OBJECT(dev); | |
2227 | out: | |
2228 | error_propagate(errp, local_err); | |
2229 | } | |
2230 | static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, | |
2231 | DeviceState *dev, Error **errp) | |
2232 | { | |
2233 | int idx = -1; | |
2234 | Error *local_err = NULL; | |
2235 | X86CPU *cpu = X86_CPU(dev); | |
2236 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
2237 | ||
2238 | if (!pcms->acpi_dev) { | |
2239 | error_setg(&local_err, "CPU hot unplug not supported without ACPI"); | |
2240 | goto out; | |
2241 | } | |
2242 | ||
2243 | pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); | |
2244 | assert(idx != -1); | |
2245 | if (idx == 0) { | |
2246 | error_setg(&local_err, "Boot CPU is unpluggable"); | |
2247 | goto out; | |
2248 | } | |
2249 | ||
2250 | hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, | |
2251 | &local_err); | |
2252 | if (local_err) { | |
2253 | goto out; | |
2254 | } | |
2255 | ||
2256 | out: | |
2257 | error_propagate(errp, local_err); | |
2258 | ||
2259 | } | |
2260 | ||
2261 | static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, | |
2262 | DeviceState *dev, Error **errp) | |
2263 | { | |
2264 | CPUArchId *found_cpu; | |
2265 | Error *local_err = NULL; | |
2266 | X86CPU *cpu = X86_CPU(dev); | |
2267 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
2268 | ||
2269 | hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
2270 | if (local_err) { | |
2271 | goto out; | |
2272 | } | |
2273 | ||
2274 | found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); | |
2275 | found_cpu->cpu = NULL; | |
2276 | object_property_set_bool(OBJECT(dev), false, "realized", NULL); | |
2277 | ||
2278 | /* decrement the number of CPUs */ | |
2279 | pcms->boot_cpus--; | |
2280 | /* Update the number of CPUs in CMOS */ | |
2281 | rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); | |
2282 | fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); | |
2283 | out: | |
2284 | error_propagate(errp, local_err); | |
2285 | } | |
2286 | ||
2287 | static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, | |
2288 | DeviceState *dev, Error **errp) | |
2289 | { | |
2290 | int idx; | |
2291 | CPUState *cs; | |
2292 | CPUArchId *cpu_slot; | |
2293 | X86CPUTopoInfo topo; | |
2294 | X86CPU *cpu = X86_CPU(dev); | |
2295 | MachineState *ms = MACHINE(hotplug_dev); | |
2296 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
2297 | unsigned int smp_cores = ms->smp.cores; | |
2298 | unsigned int smp_threads = ms->smp.threads; | |
2299 | ||
2300 | if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { | |
2301 | error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", | |
2302 | ms->cpu_type); | |
2303 | return; | |
2304 | } | |
2305 | ||
2306 | /* | |
2307 | * If APIC ID is not set, | |
2308 | * set it based on socket/die/core/thread properties. | |
2309 | */ | |
2310 | if (cpu->apic_id == UNASSIGNED_APIC_ID) { | |
2311 | int max_socket = (ms->smp.max_cpus - 1) / | |
2312 | smp_threads / smp_cores / pcms->smp_dies; | |
2313 | ||
2314 | if (cpu->socket_id < 0) { | |
2315 | error_setg(errp, "CPU socket-id is not set"); | |
2316 | return; | |
2317 | } else if (cpu->socket_id > max_socket) { | |
2318 | error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", | |
2319 | cpu->socket_id, max_socket); | |
2320 | return; | |
2321 | } | |
2322 | if (cpu->core_id < 0) { | |
2323 | error_setg(errp, "CPU core-id is not set"); | |
2324 | return; | |
2325 | } else if (cpu->core_id > (smp_cores - 1)) { | |
2326 | error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", | |
2327 | cpu->core_id, smp_cores - 1); | |
2328 | return; | |
2329 | } | |
2330 | if (cpu->thread_id < 0) { | |
2331 | error_setg(errp, "CPU thread-id is not set"); | |
2332 | return; | |
2333 | } else if (cpu->thread_id > (smp_threads - 1)) { | |
2334 | error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", | |
2335 | cpu->thread_id, smp_threads - 1); | |
2336 | return; | |
2337 | } | |
2338 | ||
2339 | topo.pkg_id = cpu->socket_id; | |
2340 | topo.core_id = cpu->core_id; | |
2341 | topo.smt_id = cpu->thread_id; | |
2342 | cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo); | |
2343 | } | |
2344 | ||
2345 | cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); | |
2346 | if (!cpu_slot) { | |
2347 | MachineState *ms = MACHINE(pcms); | |
2348 | ||
2349 | x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); | |
2350 | error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with" | |
2351 | " APIC ID %" PRIu32 ", valid index range 0:%d", | |
2352 | topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id, | |
2353 | ms->possible_cpus->len - 1); | |
2354 | return; | |
2355 | } | |
2356 | ||
2357 | if (cpu_slot->cpu) { | |
2358 | error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", | |
2359 | idx, cpu->apic_id); | |
2360 | return; | |
2361 | } | |
2362 | ||
2363 | /* if 'address' properties socket-id/core-id/thread-id are not set, set them | |
2364 | * so that machine_query_hotpluggable_cpus would show correct values | |
2365 | */ | |
2366 | /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() | |
2367 | * once -smp refactoring is complete and there will be CPU private | |
2368 | * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ | |
2369 | x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); | |
2370 | if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { | |
2371 | error_setg(errp, "property socket-id: %u doesn't match set apic-id:" | |
2372 | " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); | |
2373 | return; | |
2374 | } | |
2375 | cpu->socket_id = topo.pkg_id; | |
2376 | ||
2377 | if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { | |
2378 | error_setg(errp, "property core-id: %u doesn't match set apic-id:" | |
2379 | " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); | |
2380 | return; | |
2381 | } | |
2382 | cpu->core_id = topo.core_id; | |
2383 | ||
2384 | if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { | |
2385 | error_setg(errp, "property thread-id: %u doesn't match set apic-id:" | |
2386 | " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); | |
2387 | return; | |
2388 | } | |
2389 | cpu->thread_id = topo.smt_id; | |
2390 | ||
2391 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && | |
2392 | !kvm_hv_vpindex_settable()) { | |
2393 | error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); | |
2394 | return; | |
2395 | } | |
2396 | ||
2397 | cs = CPU(cpu); | |
2398 | cs->cpu_index = idx; | |
2399 | ||
2400 | numa_cpu_pre_plug(cpu_slot, dev, errp); | |
2401 | } | |
2402 | ||
2403 | static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev, | |
2404 | DeviceState *dev, Error **errp) | |
2405 | { | |
2406 | HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); | |
2407 | Error *local_err = NULL; | |
2408 | ||
2409 | if (!hotplug_dev2) { | |
2410 | /* | |
2411 | * Without a bus hotplug handler, we cannot control the plug/unplug | |
2412 | * order. This should never be the case on x86, however better add | |
2413 | * a safety net. | |
2414 | */ | |
2415 | error_setg(errp, "virtio-pmem-pci not supported on this bus."); | |
2416 | return; | |
2417 | } | |
2418 | /* | |
2419 | * First, see if we can plug this memory device at all. If that | |
2420 | * succeeds, branch of to the actual hotplug handler. | |
2421 | */ | |
2422 | memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, | |
2423 | &local_err); | |
2424 | if (!local_err) { | |
2425 | hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); | |
2426 | } | |
2427 | error_propagate(errp, local_err); | |
2428 | } | |
2429 | ||
2430 | static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev, | |
2431 | DeviceState *dev, Error **errp) | |
2432 | { | |
2433 | HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); | |
2434 | Error *local_err = NULL; | |
2435 | ||
2436 | /* | |
2437 | * Plug the memory device first and then branch off to the actual | |
2438 | * hotplug handler. If that one fails, we can easily undo the memory | |
2439 | * device bits. | |
2440 | */ | |
2441 | memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); | |
2442 | hotplug_handler_plug(hotplug_dev2, dev, &local_err); | |
2443 | if (local_err) { | |
2444 | memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); | |
2445 | } | |
2446 | error_propagate(errp, local_err); | |
2447 | } | |
2448 | ||
2449 | static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev, | |
2450 | DeviceState *dev, Error **errp) | |
2451 | { | |
2452 | /* We don't support virtio pmem hot unplug */ | |
2453 | error_setg(errp, "virtio pmem device unplug not supported."); | |
2454 | } | |
2455 | ||
2456 | static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev, | |
2457 | DeviceState *dev, Error **errp) | |
2458 | { | |
2459 | /* We don't support virtio pmem hot unplug */ | |
2460 | } | |
2461 | ||
2462 | static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, | |
2463 | DeviceState *dev, Error **errp) | |
2464 | { | |
2465 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
2466 | pc_memory_pre_plug(hotplug_dev, dev, errp); | |
2467 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
2468 | pc_cpu_pre_plug(hotplug_dev, dev, errp); | |
2469 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { | |
2470 | pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp); | |
2471 | } | |
2472 | } | |
2473 | ||
2474 | static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, | |
2475 | DeviceState *dev, Error **errp) | |
2476 | { | |
2477 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
2478 | pc_memory_plug(hotplug_dev, dev, errp); | |
2479 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
2480 | pc_cpu_plug(hotplug_dev, dev, errp); | |
2481 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { | |
2482 | pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp); | |
2483 | } | |
2484 | } | |
2485 | ||
2486 | static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, | |
2487 | DeviceState *dev, Error **errp) | |
2488 | { | |
2489 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
2490 | pc_memory_unplug_request(hotplug_dev, dev, errp); | |
2491 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
2492 | pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); | |
2493 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { | |
2494 | pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp); | |
2495 | } else { | |
2496 | error_setg(errp, "acpi: device unplug request for not supported device" | |
2497 | " type: %s", object_get_typename(OBJECT(dev))); | |
2498 | } | |
2499 | } | |
2500 | ||
2501 | static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, | |
2502 | DeviceState *dev, Error **errp) | |
2503 | { | |
2504 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
2505 | pc_memory_unplug(hotplug_dev, dev, errp); | |
2506 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
2507 | pc_cpu_unplug_cb(hotplug_dev, dev, errp); | |
2508 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { | |
2509 | pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp); | |
2510 | } else { | |
2511 | error_setg(errp, "acpi: device unplug for not supported device" | |
2512 | " type: %s", object_get_typename(OBJECT(dev))); | |
2513 | } | |
2514 | } | |
2515 | ||
2516 | static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, | |
2517 | DeviceState *dev) | |
2518 | { | |
2519 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || | |
2520 | object_dynamic_cast(OBJECT(dev), TYPE_CPU) || | |
2521 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { | |
2522 | return HOTPLUG_HANDLER(machine); | |
2523 | } | |
2524 | ||
2525 | return NULL; | |
2526 | } | |
2527 | ||
2528 | static void | |
2529 | pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, | |
2530 | const char *name, void *opaque, | |
2531 | Error **errp) | |
2532 | { | |
2533 | MachineState *ms = MACHINE(obj); | |
2534 | int64_t value = memory_region_size(&ms->device_memory->mr); | |
2535 | ||
2536 | visit_type_int(v, name, &value, errp); | |
2537 | } | |
2538 | ||
2539 | static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, | |
2540 | const char *name, void *opaque, | |
2541 | Error **errp) | |
2542 | { | |
2543 | PCMachineState *pcms = PC_MACHINE(obj); | |
2544 | uint64_t value = pcms->max_ram_below_4g; | |
2545 | ||
2546 | visit_type_size(v, name, &value, errp); | |
2547 | } | |
2548 | ||
2549 | static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, | |
2550 | const char *name, void *opaque, | |
2551 | Error **errp) | |
2552 | { | |
2553 | PCMachineState *pcms = PC_MACHINE(obj); | |
2554 | Error *error = NULL; | |
2555 | uint64_t value; | |
2556 | ||
2557 | visit_type_size(v, name, &value, &error); | |
2558 | if (error) { | |
2559 | error_propagate(errp, error); | |
2560 | return; | |
2561 | } | |
2562 | if (value > 4 * GiB) { | |
2563 | error_setg(&error, | |
2564 | "Machine option 'max-ram-below-4g=%"PRIu64 | |
2565 | "' expects size less than or equal to 4G", value); | |
2566 | error_propagate(errp, error); | |
2567 | return; | |
2568 | } | |
2569 | ||
2570 | if (value < 1 * MiB) { | |
2571 | warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," | |
2572 | "BIOS may not work with less than 1MiB", value); | |
2573 | } | |
2574 | ||
2575 | pcms->max_ram_below_4g = value; | |
2576 | } | |
2577 | ||
2578 | static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, | |
2579 | void *opaque, Error **errp) | |
2580 | { | |
2581 | PCMachineState *pcms = PC_MACHINE(obj); | |
2582 | OnOffAuto vmport = pcms->vmport; | |
2583 | ||
2584 | visit_type_OnOffAuto(v, name, &vmport, errp); | |
2585 | } | |
2586 | ||
2587 | static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, | |
2588 | void *opaque, Error **errp) | |
2589 | { | |
2590 | PCMachineState *pcms = PC_MACHINE(obj); | |
2591 | ||
2592 | visit_type_OnOffAuto(v, name, &pcms->vmport, errp); | |
2593 | } | |
2594 | ||
2595 | bool pc_machine_is_smm_enabled(PCMachineState *pcms) | |
2596 | { | |
2597 | bool smm_available = false; | |
2598 | ||
2599 | if (pcms->smm == ON_OFF_AUTO_OFF) { | |
2600 | return false; | |
2601 | } | |
2602 | ||
2603 | if (tcg_enabled() || qtest_enabled()) { | |
2604 | smm_available = true; | |
2605 | } else if (kvm_enabled()) { | |
2606 | smm_available = kvm_has_smm(); | |
2607 | } | |
2608 | ||
2609 | if (smm_available) { | |
2610 | return true; | |
2611 | } | |
2612 | ||
2613 | if (pcms->smm == ON_OFF_AUTO_ON) { | |
2614 | error_report("System Management Mode not supported by this hypervisor."); | |
2615 | exit(1); | |
2616 | } | |
2617 | return false; | |
2618 | } | |
2619 | ||
2620 | static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, | |
2621 | void *opaque, Error **errp) | |
2622 | { | |
2623 | PCMachineState *pcms = PC_MACHINE(obj); | |
2624 | OnOffAuto smm = pcms->smm; | |
2625 | ||
2626 | visit_type_OnOffAuto(v, name, &smm, errp); | |
2627 | } | |
2628 | ||
2629 | static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, | |
2630 | void *opaque, Error **errp) | |
2631 | { | |
2632 | PCMachineState *pcms = PC_MACHINE(obj); | |
2633 | ||
2634 | visit_type_OnOffAuto(v, name, &pcms->smm, errp); | |
2635 | } | |
2636 | ||
2637 | static bool pc_machine_get_smbus(Object *obj, Error **errp) | |
2638 | { | |
2639 | PCMachineState *pcms = PC_MACHINE(obj); | |
2640 | ||
2641 | return pcms->smbus_enabled; | |
2642 | } | |
2643 | ||
2644 | static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) | |
2645 | { | |
2646 | PCMachineState *pcms = PC_MACHINE(obj); | |
2647 | ||
2648 | pcms->smbus_enabled = value; | |
2649 | } | |
2650 | ||
2651 | static bool pc_machine_get_sata(Object *obj, Error **errp) | |
2652 | { | |
2653 | PCMachineState *pcms = PC_MACHINE(obj); | |
2654 | ||
2655 | return pcms->sata_enabled; | |
2656 | } | |
2657 | ||
2658 | static void pc_machine_set_sata(Object *obj, bool value, Error **errp) | |
2659 | { | |
2660 | PCMachineState *pcms = PC_MACHINE(obj); | |
2661 | ||
2662 | pcms->sata_enabled = value; | |
2663 | } | |
2664 | ||
2665 | static bool pc_machine_get_pit(Object *obj, Error **errp) | |
2666 | { | |
2667 | PCMachineState *pcms = PC_MACHINE(obj); | |
2668 | ||
2669 | return pcms->pit_enabled; | |
2670 | } | |
2671 | ||
2672 | static void pc_machine_set_pit(Object *obj, bool value, Error **errp) | |
2673 | { | |
2674 | PCMachineState *pcms = PC_MACHINE(obj); | |
2675 | ||
2676 | pcms->pit_enabled = value; | |
2677 | } | |
2678 | ||
2679 | static void pc_machine_initfn(Object *obj) | |
2680 | { | |
2681 | PCMachineState *pcms = PC_MACHINE(obj); | |
2682 | ||
2683 | pcms->max_ram_below_4g = 0; /* use default */ | |
2684 | pcms->smm = ON_OFF_AUTO_AUTO; | |
2685 | pcms->vmport = ON_OFF_AUTO_AUTO; | |
2686 | /* acpi build is enabled by default if machine supports it */ | |
2687 | pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; | |
2688 | pcms->smbus_enabled = true; | |
2689 | pcms->sata_enabled = true; | |
2690 | pcms->pit_enabled = true; | |
2691 | pcms->smp_dies = 1; | |
2692 | ||
2693 | pc_system_flash_create(pcms); | |
2694 | } | |
2695 | ||
2696 | static void pc_machine_reset(MachineState *machine) | |
2697 | { | |
2698 | CPUState *cs; | |
2699 | X86CPU *cpu; | |
2700 | ||
2701 | qemu_devices_reset(); | |
2702 | ||
2703 | /* Reset APIC after devices have been reset to cancel | |
2704 | * any changes that qemu_devices_reset() might have done. | |
2705 | */ | |
2706 | CPU_FOREACH(cs) { | |
2707 | cpu = X86_CPU(cs); | |
2708 | ||
2709 | if (cpu->apic_state) { | |
2710 | device_reset(cpu->apic_state); | |
2711 | } | |
2712 | } | |
2713 | } | |
2714 | ||
2715 | static CpuInstanceProperties | |
2716 | pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index) | |
2717 | { | |
2718 | MachineClass *mc = MACHINE_GET_CLASS(ms); | |
2719 | const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); | |
2720 | ||
2721 | assert(cpu_index < possible_cpus->len); | |
2722 | return possible_cpus->cpus[cpu_index].props; | |
2723 | } | |
2724 | ||
2725 | static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) | |
2726 | { | |
2727 | X86CPUTopoInfo topo; | |
2728 | ||
2729 | assert(idx < ms->possible_cpus->len); | |
2730 | x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, | |
2731 | ms->smp.cores, ms->smp.threads, &topo); | |
2732 | return topo.pkg_id % nb_numa_nodes; | |
2733 | } | |
2734 | ||
2735 | static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) | |
2736 | { | |
2737 | PCMachineState *pcms = PC_MACHINE(ms); | |
2738 | int i; | |
2739 | unsigned int max_cpus = ms->smp.max_cpus; | |
2740 | ||
2741 | if (ms->possible_cpus) { | |
2742 | /* | |
2743 | * make sure that max_cpus hasn't changed since the first use, i.e. | |
2744 | * -smp hasn't been parsed after it | |
2745 | */ | |
2746 | assert(ms->possible_cpus->len == max_cpus); | |
2747 | return ms->possible_cpus; | |
2748 | } | |
2749 | ||
2750 | ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + | |
2751 | sizeof(CPUArchId) * max_cpus); | |
2752 | ms->possible_cpus->len = max_cpus; | |
2753 | for (i = 0; i < ms->possible_cpus->len; i++) { | |
2754 | X86CPUTopoInfo topo; | |
2755 | ||
2756 | ms->possible_cpus->cpus[i].type = ms->cpu_type; | |
2757 | ms->possible_cpus->cpus[i].vcpus_count = 1; | |
2758 | ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms, i); | |
2759 | x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, | |
2760 | ms->smp.cores, ms->smp.threads, &topo); | |
2761 | ms->possible_cpus->cpus[i].props.has_socket_id = true; | |
2762 | ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id; | |
2763 | ms->possible_cpus->cpus[i].props.has_core_id = true; | |
2764 | ms->possible_cpus->cpus[i].props.core_id = topo.core_id; | |
2765 | ms->possible_cpus->cpus[i].props.has_thread_id = true; | |
2766 | ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; | |
2767 | } | |
2768 | return ms->possible_cpus; | |
2769 | } | |
2770 | ||
2771 | static void x86_nmi(NMIState *n, int cpu_index, Error **errp) | |
2772 | { | |
2773 | /* cpu index isn't used */ | |
2774 | CPUState *cs; | |
2775 | ||
2776 | CPU_FOREACH(cs) { | |
2777 | X86CPU *cpu = X86_CPU(cs); | |
2778 | ||
2779 | if (!cpu->apic_state) { | |
2780 | cpu_interrupt(cs, CPU_INTERRUPT_NMI); | |
2781 | } else { | |
2782 | apic_deliver_nmi(cpu->apic_state); | |
2783 | } | |
2784 | } | |
2785 | } | |
2786 | ||
2787 | static void pc_machine_class_init(ObjectClass *oc, void *data) | |
2788 | { | |
2789 | MachineClass *mc = MACHINE_CLASS(oc); | |
2790 | PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); | |
2791 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); | |
2792 | NMIClass *nc = NMI_CLASS(oc); | |
2793 | ||
2794 | pcmc->pci_enabled = true; | |
2795 | pcmc->has_acpi_build = true; | |
2796 | pcmc->rsdp_in_ram = true; | |
2797 | pcmc->smbios_defaults = true; | |
2798 | pcmc->smbios_uuid_encoded = true; | |
2799 | pcmc->gigabyte_align = true; | |
2800 | pcmc->has_reserved_memory = true; | |
2801 | pcmc->kvmclock_enabled = true; | |
2802 | pcmc->enforce_aligned_dimm = true; | |
2803 | /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported | |
2804 | * to be used at the moment, 32K should be enough for a while. */ | |
2805 | pcmc->acpi_data_size = 0x20000 + 0x8000; | |
2806 | pcmc->save_tsc_khz = true; | |
2807 | pcmc->linuxboot_dma_enabled = true; | |
2808 | pcmc->pvh_enabled = true; | |
2809 | assert(!mc->get_hotplug_handler); | |
2810 | mc->get_hotplug_handler = pc_get_hotplug_handler; | |
2811 | mc->cpu_index_to_instance_props = pc_cpu_index_to_props; | |
2812 | mc->get_default_cpu_node_id = pc_get_default_cpu_node_id; | |
2813 | mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; | |
2814 | mc->auto_enable_numa_with_memhp = true; | |
2815 | mc->has_hotpluggable_cpus = true; | |
2816 | mc->default_boot_order = "cad"; | |
2817 | mc->hot_add_cpu = pc_hot_add_cpu; | |
2818 | mc->block_default_type = IF_IDE; | |
2819 | mc->max_cpus = 255; | |
2820 | mc->reset = pc_machine_reset; | |
2821 | hc->pre_plug = pc_machine_device_pre_plug_cb; | |
2822 | hc->plug = pc_machine_device_plug_cb; | |
2823 | hc->unplug_request = pc_machine_device_unplug_request_cb; | |
2824 | hc->unplug = pc_machine_device_unplug_cb; | |
2825 | nc->nmi_monitor_handler = x86_nmi; | |
2826 | mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; | |
2827 | mc->nvdimm_supported = true; | |
2828 | ||
2829 | object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", | |
2830 | pc_machine_get_device_memory_region_size, NULL, | |
2831 | NULL, NULL, &error_abort); | |
2832 | ||
2833 | object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", | |
2834 | pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, | |
2835 | NULL, NULL, &error_abort); | |
2836 | ||
2837 | object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, | |
2838 | "Maximum ram below the 4G boundary (32bit boundary)", &error_abort); | |
2839 | ||
2840 | object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", | |
2841 | pc_machine_get_smm, pc_machine_set_smm, | |
2842 | NULL, NULL, &error_abort); | |
2843 | object_class_property_set_description(oc, PC_MACHINE_SMM, | |
2844 | "Enable SMM (pc & q35)", &error_abort); | |
2845 | ||
2846 | object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", | |
2847 | pc_machine_get_vmport, pc_machine_set_vmport, | |
2848 | NULL, NULL, &error_abort); | |
2849 | object_class_property_set_description(oc, PC_MACHINE_VMPORT, | |
2850 | "Enable vmport (pc & q35)", &error_abort); | |
2851 | ||
2852 | object_class_property_add_bool(oc, PC_MACHINE_SMBUS, | |
2853 | pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); | |
2854 | ||
2855 | object_class_property_add_bool(oc, PC_MACHINE_SATA, | |
2856 | pc_machine_get_sata, pc_machine_set_sata, &error_abort); | |
2857 | ||
2858 | object_class_property_add_bool(oc, PC_MACHINE_PIT, | |
2859 | pc_machine_get_pit, pc_machine_set_pit, &error_abort); | |
2860 | } | |
2861 | ||
2862 | static const TypeInfo pc_machine_info = { | |
2863 | .name = TYPE_PC_MACHINE, | |
2864 | .parent = TYPE_MACHINE, | |
2865 | .abstract = true, | |
2866 | .instance_size = sizeof(PCMachineState), | |
2867 | .instance_init = pc_machine_initfn, | |
2868 | .class_size = sizeof(PCMachineClass), | |
2869 | .class_init = pc_machine_class_init, | |
2870 | .interfaces = (InterfaceInfo[]) { | |
2871 | { TYPE_HOTPLUG_HANDLER }, | |
2872 | { TYPE_NMI }, | |
2873 | { } | |
2874 | }, | |
2875 | }; | |
2876 | ||
2877 | static void pc_machine_register_types(void) | |
2878 | { | |
2879 | type_register_static(&pc_machine_info); | |
2880 | } | |
2881 | ||
2882 | type_init(pc_machine_register_types) |