dev->irq_state = 0;
pci_update_irq_status(dev);
pci_device_deassert_intx(dev);
- /* Clear all writeable bits */
+ /* Clear all writable bits */
pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
pci_get_word(dev->wmask + PCI_COMMAND) |
pci_get_word(dev->w1cmask + PCI_COMMAND));
wmask = ~(size - 1);
addr = pci_bar(pci_dev, region_num);
if (region_num == PCI_ROM_SLOT) {
- /* ROM enable bit is writeable */
+ /* ROM enable bit is writable */
wmask |= PCI_ROM_ADDRESS_ENABLE;
}
pci_set_long(pci_dev->config + addr, type);
pci_patch_ids(pdev, ptr, size);
}
+ qemu_put_ram_ptr(ptr);
+
pci_register_bar(pdev, PCI_ROM_SLOT, size,
0, pci_map_option_rom);
if (!offset)
return;
pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
- /* Make capability writeable again */
+ /* Make capability writable again */
memset(pdev->wmask + offset, 0xff, size);
memset(pdev->w1cmask + offset, 0, size);
/* Clear cmask as device-specific registers can't be checked */