* THE SOFTWARE.
*/
#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qemu/error-report.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_bus.h"
-#include "hw/pci-host/apb.h"
-#include "hw/i386/pc.h"
+#include "hw/pci/pci_host.h"
+#include "hw/pci-host/sabre.h"
#include "hw/char/serial.h"
+#include "hw/char/parallel.h"
#include "hw/timer/m48t59.h"
+#include "hw/input/i8042.h"
#include "hw/block/fdc.h"
#include "net/net.h"
#include "qemu/timer.h"
#include "hw/ide.h"
#include "hw/ide/pci.h"
#include "hw/loader.h"
+#include "hw/fw-path-provider.h"
#include "elf.h"
-#include "qemu/cutils.h"
-
-//#define DEBUG_EBUS
-
-#ifdef DEBUG_EBUS
-#define EBUS_DPRINTF(fmt, ...) \
- do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define EBUS_DPRINTF(fmt, ...)
-#endif
+#include "trace.h"
#define KERNEL_LOAD_ADDR 0x00404000
#define CMDLINE_ADDR 0x003ff000
-#define PROM_SIZE_MAX (4 * 1024 * 1024)
+#define PROM_SIZE_MAX (4 * MiB)
#define PROM_VADDR 0x000ffd00000ULL
-#define APB_SPECIAL_BASE 0x1fe00000000ULL
-#define APB_MEM_BASE 0x1ff00000000ULL
-#define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL)
+#define PBM_SPECIAL_BASE 0x1fe00000000ULL
+#define PBM_MEM_BASE 0x1ff00000000ULL
+#define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL)
#define PROM_FILENAME "openbios-sparc64"
#define NVRAM_SIZE 0x2000
#define MAX_IDE_BUS 2
PCIDevice parent_obj;
ISABus *isa_bus;
+ qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
uint64_t console_serial_base;
MemoryRegion bar0;
MemoryRegion bar1;
#define TYPE_EBUS "ebus"
#define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS)
-void DMA_init(ISABus *bus, int high_page_enable)
+const char *fw_cfg_arch_key_name(uint16_t key)
{
+ static const struct {
+ uint16_t key;
+ const char *name;
+ } fw_cfg_arch_wellknown_keys[] = {
+ {FW_CFG_SPARC64_WIDTH, "width"},
+ {FW_CFG_SPARC64_HEIGHT, "height"},
+ {FW_CFG_SPARC64_DEPTH, "depth"},
+ };
+
+ for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
+ if (fw_cfg_arch_wellknown_keys[i].key == key) {
+ return fw_cfg_arch_wellknown_keys[i].name;
+ }
+ }
+ return NULL;
}
static void fw_cfg_boot_set(void *opaque, const char *boot_device,
unsigned int i;
long kernel_size;
uint8_t *ptr;
- uint64_t kernel_top;
+ uint64_t kernel_top = 0;
linux_boot = (kernel_filename != NULL);
#else
bswap_needed = 0;
#endif
- kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry,
+ kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry,
kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0);
if (kernel_size < 0) {
*kernel_addr = KERNEL_LOAD_ADDR;
RAM_size - KERNEL_LOAD_ADDR);
}
if (kernel_size < 0) {
- fprintf(stderr, "qemu: could not load kernel '%s'\n",
- kernel_filename);
+ error_report("could not load kernel '%s'", kernel_filename);
exit(1);
}
/* load initrd above kernel */
*initrd_size = 0;
- if (initrd_filename) {
+ if (initrd_filename && kernel_top) {
*initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
*initrd_size = load_image_targphys(initrd_filename,
*initrd_addr,
RAM_size - *initrd_addr);
if ((int)*initrd_size < 0) {
- fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
- initrd_filename);
+ error_report("could not load initial ram disk '%s'",
+ initrd_filename);
exit(1);
}
}
if (*initrd_size > 0) {
for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
- ptr = rom_ptr(*kernel_addr + i);
- if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
+ ptr = rom_ptr(*kernel_addr + i, 32);
+ if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
stl_p(ptr + 24, *initrd_addr + *kernel_addr);
stl_p(ptr + 28, *initrd_size);
break;
uint64_t prom_addr;
} ResetData;
-static void isa_irq_handler(void *opaque, int n, int level)
+#define TYPE_SUN4U_POWER "power"
+#define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER)
+
+typedef struct PowerDevice {
+ SysBusDevice parent_obj;
+
+ MemoryRegion power_mmio;
+} PowerDevice;
+
+/* Power */
+static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size)
{
- static const int isa_irq_to_ivec[16] = {
- [1] = 0x29, /* keyboard */
- [4] = 0x2b, /* serial */
- [6] = 0x27, /* floppy */
- [7] = 0x22, /* parallel */
- [12] = 0x2a, /* mouse */
- };
- qemu_irq *irqs = opaque;
- int ivec;
-
- assert(n < ARRAY_SIZE(isa_irq_to_ivec));
- ivec = isa_irq_to_ivec[n];
- EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec);
- if (ivec) {
- qemu_set_irq(irqs[ivec], level);
+ return 0;
+}
+
+static void power_mem_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ /* According to a real Ultra 5, bit 24 controls the power */
+ if (val & 0x1000000) {
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+ }
+}
+
+static const MemoryRegionOps power_mem_ops = {
+ .read = power_mem_read,
+ .write = power_mem_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static void power_realize(DeviceState *dev, Error **errp)
+{
+ PowerDevice *d = SUN4U_POWER(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d,
+ "power", sizeof(uint32_t));
+
+ sysbus_init_mmio(sbd, &d->power_mmio);
+}
+
+static void power_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = power_realize;
+}
+
+static const TypeInfo power_info = {
+ .name = TYPE_SUN4U_POWER,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(PowerDevice),
+ .class_init = power_class_init,
+};
+
+static void ebus_isa_irq_handler(void *opaque, int n, int level)
+{
+ EbusState *s = EBUS(opaque);
+ qemu_irq irq = s->isa_bus_irqs[n];
+
+ /* Pass ISA bus IRQs onto their gpio equivalent */
+ trace_ebus_isa_irq_handler(n, level);
+ if (irq) {
+ qemu_set_irq(irq, level);
}
}
static void ebus_realize(PCIDevice *pci_dev, Error **errp)
{
EbusState *s = EBUS(pci_dev);
- APBState *apb;
+ SysBusDevice *sbd;
DeviceState *dev;
qemu_irq *isa_irq;
DriveInfo *fd[MAX_FD];
return;
}
- apb = APB_DEVICE(object_resolve_path_type("", TYPE_APB, NULL));
- if (!apb) {
- error_setg(errp, "unable to locate APB PCI host bridge");
- return;
- }
-
- isa_irq = qemu_allocate_irqs(isa_irq_handler, apb->pbm_irqs, 16);
+ /* ISA bus */
+ isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
isa_bus_irqs(s->isa_bus, isa_irq);
+ qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
+ ISA_NUM_IRQS);
/* Serial ports */
i = 0;
if (s->console_serial_base) {
serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
- 0, NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
+ 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN);
i++;
}
- serial_hds_isa_init(s->isa_bus, i, MAX_SERIAL_PORTS);
+ serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS);
/* Parallel ports */
parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
qdev_prop_set_uint32(dev, "dma", -1);
qdev_init_nofail(dev);
+ /* Power */
+ dev = qdev_create(NULL, TYPE_SUN4U_POWER);
+ qdev_init_nofail(dev);
+ sbd = SYS_BUS_DEVICE(dev);
+ memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
+ sysbus_mmio_get_region(sbd, 0));
+
/* PCI */
pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
pci_dev->config[0x05] = 0x00;
0, 0x1000000);
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
- 0, 0x4000);
+ 0, 0x8000);
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
}
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
- ret = load_elf(filename, translate_prom_address, &addr,
+ ret = load_elf(filename, NULL, translate_prom_address, &addr,
NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
if (ret < 0 || ret > PROM_SIZE_MAX) {
ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
ret = -1;
}
if (ret < 0 || ret > PROM_SIZE_MAX) {
- fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
+ error_report("could not load prom '%s'", bios_name);
exit(1);
}
}
-static void prom_init1(Object *obj)
+static void prom_realize(DeviceState *ds, Error **errp)
{
- PROMState *s = OPENPROM(obj);
- SysBusDevice *dev = SYS_BUS_DEVICE(obj);
+ PROMState *s = OPENPROM(ds);
+ SysBusDevice *dev = SYS_BUS_DEVICE(ds);
+ Error *local_err = NULL;
+
+ memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
+ PROM_SIZE_MAX, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
- memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX,
- &error_fatal);
vmstate_register_ram_global(&s->prom);
memory_region_set_readonly(&s->prom, true);
sysbus_init_mmio(dev, &s->prom);
DeviceClass *dc = DEVICE_CLASS(klass);
dc->props = prom_properties;
+ dc->realize = prom_realize;
}
static const TypeInfo prom_info = {
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PROMState),
.class_init = prom_class_init,
- .instance_init = prom_init1,
};
Nvram *nvram;
unsigned int i;
uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
- APBState *apb;
+ SabreState *sabre;
PCIBus *pci_bus, *pci_busA, *pci_busB;
PCIDevice *ebus, *pci_dev;
SysBusDevice *s;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
- DeviceState *dev;
+ DeviceState *iommu, *dev;
FWCfgState *fw_cfg;
NICInfo *nd;
MACAddr macaddr;
/* init CPUs */
cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
+ /* IOMMU */
+ iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU);
+ qdev_init_nofail(iommu);
+
/* set up devices */
ram_init(0, machine->ram_size);
prom_init(hwdef->prom_addr, bios_name);
- /* Init APB (PCI host bridge) */
- apb = APB_DEVICE(qdev_create(NULL, TYPE_APB));
- qdev_prop_set_uint64(DEVICE(apb), "special-base", APB_SPECIAL_BASE);
- qdev_prop_set_uint64(DEVICE(apb), "mem-base", APB_MEM_BASE);
- qdev_init_nofail(DEVICE(apb));
+ /* Init sabre (PCI host bridge) */
+ sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
+ qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
+ qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
+ object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
+ &error_abort);
+ qdev_init_nofail(DEVICE(sabre));
/* Wire up PCI interrupts to CPU */
for (i = 0; i < IVEC_MAX; i++) {
- qdev_connect_gpio_out_named(DEVICE(apb), "ivec-irq", i,
+ qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
}
- pci_bus = PCI_HOST_BRIDGE(apb)->bus;
- pci_busA = pci_bridge_get_sec_bus(apb->bridgeA);
- pci_busB = pci_bridge_get_sec_bus(apb->bridgeB);
+ pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
+ pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
+ pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
- /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is
+ /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
reserved (leaving no slots free after on-board devices) however slots
0-3 are free on busB */
pci_bus->slot_reserved_mask = 0xfffffffc;
hwdef->console_serial_base);
qdev_init_nofail(DEVICE(ebus));
- pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
+ /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
+ qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
+ qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
+ qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
+ qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
+ qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
+ qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
+ qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
+ qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
+ qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
+ qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
+
+ switch (vga_interface_type) {
+ case VGA_STD:
+ pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
+ break;
+ case VGA_NONE:
+ break;
+ default:
+ abort(); /* Should not happen - types are checked in vl.c already */
+ }
memset(&macaddr, 0, sizeof(MACAddr));
onboard_nic = false;
&FW_CFG_IO(dev)->comb_iomem);
fw_cfg = FW_CFG(dev);
- fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
- fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
sun4v_id = 64,
};
+/*
+ * Implementation of an interface to adjust firmware path
+ * for the bootindex property handling.
+ */
+static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus,
+ DeviceState *dev)
+{
+ PCIDevice *pci;
+ IDEBus *ide_bus;
+ IDEState *ide_s;
+ int bus_id;
+
+ if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) {
+ pci = PCI_DEVICE(dev);
+
+ if (PCI_FUNC(pci->devfn)) {
+ return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn),
+ PCI_FUNC(pci->devfn));
+ } else {
+ return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn));
+ }
+ }
+
+ if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) {
+ ide_bus = IDE_BUS(qdev_get_parent_bus(dev));
+ ide_s = idebus_active_if(ide_bus);
+ bus_id = ide_bus->bus_id;
+
+ if (ide_s->drive_kind == IDE_CD) {
+ return g_strdup_printf("ide@%x/cdrom", bus_id);
+ }
+
+ return g_strdup_printf("ide@%x/disk", bus_id);
+ }
+
+ if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
+ return g_strdup("disk");
+ }
+
+ if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
+ return g_strdup("cdrom");
+ }
+
+ if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
+ return g_strdup("disk");
+ }
+
+ return NULL;
+}
+
static const struct hwdef hwdefs[] = {
/* Sun4u generic PC-like machine */
{
static void sun4u_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+ FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
mc->desc = "Sun4u platform";
mc->init = sun4u_init;
mc->is_default = 1;
mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
+ mc->ignore_boot_device_suffixes = true;
+ mc->default_display = "std";
+ fwc->get_dev_path = sun4u_fw_dev_path;
}
static const TypeInfo sun4u_type = {
.name = MACHINE_TYPE_NAME("sun4u"),
.parent = TYPE_MACHINE,
.class_init = sun4u_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_FW_PATH_PROVIDER },
+ { }
+ },
};
static void sun4v_class_init(ObjectClass *oc, void *data)
mc->max_cpus = 1; /* XXX for now */
mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
+ mc->default_display = "std";
}
static const TypeInfo sun4v_type = {
static void sun4u_register_types(void)
{
+ type_register_static(&power_info);
type_register_static(&ebus_info);
type_register_static(&prom_info);
type_register_static(&ram_info);
projects / mirror_qemu.git / blobdiff