#include "hw/i386/ioapic.h"
#include "hw/pci/msi.h"
#include "hw/sysbus.h"
+#include "qemu/iova-tree.h"
#define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
#define INTEL_IOMMU_DEVICE(obj) \
OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE)
+#define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region"
+
/* DMAR Hardware Unit Definition address (IOMMU unit) */
#define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL
#define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff)
#define DMAR_REG_SIZE 0x230
-#define VTD_HOST_ADDRESS_WIDTH 39
-#define VTD_HAW_MASK ((1ULL << VTD_HOST_ADDRESS_WIDTH) - 1)
+#define VTD_HOST_AW_39BIT 39
+#define VTD_HOST_AW_48BIT 48
+#define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_39BIT
+#define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1)
#define DMAR_REPORT_F_INTR (1)
typedef struct VTDBus VTDBus;
typedef union VTD_IR_TableEntry VTD_IR_TableEntry;
typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
-typedef struct VTDIrq VTDIrq;
-typedef struct VTD_MSIMessage VTD_MSIMessage;
+typedef struct VTDPASIDDirEntry VTDPASIDDirEntry;
+typedef struct VTDPASIDEntry VTDPASIDEntry;
/* Context-Entry */
struct VTDContextEntry {
- uint64_t lo;
- uint64_t hi;
+ union {
+ struct {
+ uint64_t lo;
+ uint64_t hi;
+ };
+ struct {
+ uint64_t val[4];
+ };
+ };
};
struct VTDContextCacheEntry {
struct VTDContextEntry context_entry;
};
+/* PASID Directory Entry */
+struct VTDPASIDDirEntry {
+ uint64_t val;
+};
+
+/* PASID Table Entry */
+struct VTDPASIDEntry {
+ uint64_t val[8];
+};
+
struct VTDAddressSpace {
PCIBus *bus;
uint8_t devfn;
AddressSpace as;
- MemoryRegion iommu;
+ IOMMUMemoryRegion iommu;
+ MemoryRegion root;
+ MemoryRegion sys_alias;
MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */
IntelIOMMUState *iommu_state;
VTDContextCacheEntry context_cache_entry;
+ QLIST_ENTRY(VTDAddressSpace) next;
+ /* Superset of notifier flags that this address space has */
+ IOMMUNotifierFlag notifier_flags;
+ IOVATree *iova_tree; /* Traces mapped IOVA ranges */
};
struct VTDBus {
uint16_t domain_id;
uint64_t slpte;
uint64_t mask;
- bool read_flags;
- bool write_flags;
+ uint8_t access_flags;
};
/* VT-d Source-ID Qualifier types */
union VTD_IR_TableEntry {
struct {
#ifdef HOST_WORDS_BIGENDIAN
- uint32_t dest_id:32; /* Destination ID */
uint32_t __reserved_1:8; /* Reserved 1 */
uint32_t vector:8; /* Interrupt Vector */
uint32_t irte_mode:1; /* IRTE Mode */
uint32_t irte_mode:1; /* IRTE Mode */
uint32_t vector:8; /* Interrupt Vector */
uint32_t __reserved_1:8; /* Reserved 1 */
- uint32_t dest_id:32; /* Destination ID */
#endif
- uint16_t source_id:16; /* Source-ID */
+ uint32_t dest_id; /* Destination ID */
+ uint16_t source_id; /* Source-ID */
#ifdef HOST_WORDS_BIGENDIAN
uint64_t __reserved_2:44; /* Reserved 2 */
uint64_t sid_vtype:2; /* Source-ID Validation Type */
uint32_t data;
};
-/* Generic IRQ entry information */
-struct VTDIrq {
- /* Used by both IOAPIC/MSI interrupt remapping */
- uint8_t trigger_mode;
- uint8_t vector;
- uint8_t delivery_mode;
- uint32_t dest;
- uint8_t dest_mode;
-
- /* only used by MSI interrupt remapping */
- uint8_t redir_hint;
- uint8_t msi_addr_last_bits;
-};
-
-struct VTD_MSIMessage {
- union {
- struct {
-#ifdef HOST_WORDS_BIGENDIAN
- uint32_t __addr_head:12; /* 0xfee */
- uint32_t dest:8;
- uint32_t __reserved:8;
- uint32_t redir_hint:1;
- uint32_t dest_mode:1;
- uint32_t __not_used:2;
-#else
- uint32_t __not_used:2;
- uint32_t dest_mode:1;
- uint32_t redir_hint:1;
- uint32_t __reserved:8;
- uint32_t dest:8;
- uint32_t __addr_head:12; /* 0xfee */
-#endif
- uint32_t __addr_hi:32;
- } QEMU_PACKED;
- uint64_t msi_addr;
- };
- union {
- struct {
-#ifdef HOST_WORDS_BIGENDIAN
- uint16_t trigger_mode:1;
- uint16_t level:1;
- uint16_t __resved:3;
- uint16_t delivery_mode:3;
- uint16_t vector:8;
-#else
- uint16_t vector:8;
- uint16_t delivery_mode:3;
- uint16_t __resved:3;
- uint16_t level:1;
- uint16_t trigger_mode:1;
-#endif
- uint16_t __resved1:16;
- } QEMU_PACKED;
- uint32_t msi_data;
- };
-};
-
/* When IR is enabled, all MSI/MSI-X data bits should be zero */
#define VTD_IR_MSI_DATA (0)
uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */
uint32_t version;
+ bool caching_mode; /* RO - is cap CM enabled? */
+
dma_addr_t root; /* Current root table pointer */
bool root_extended; /* Type of root table (extended or not) */
+ bool root_scalable; /* Type of root table (scalable or not) */
bool dmar_enabled; /* Set if DMA remapping is enabled */
uint16_t iq_head; /* Current invalidation queue head */
uint32_t context_cache_gen; /* Should be in [1,MAX] */
GHashTable *iotlb; /* IOTLB */
- MemoryRegionIOMMUOps iommu_ops;
GHashTable *vtd_as_by_busptr; /* VTDBus objects indexed by PCIBus* reference */
VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */
+ /* list of registered notifiers */
+ QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers;
/* interrupt remapping */
bool intr_enabled; /* Whether guest enabled IR */
bool intr_eime; /* Extended interrupt mode enabled */
OnOffAuto intr_eim; /* Toggle for EIM cabability */
bool buggy_eim; /* Force buggy EIM unless eim=off */
+ uint8_t aw_bits; /* Host/IOVA address width (in bits) */
+ bool dma_drain; /* Whether DMA r/w draining enabled */
+
+ /*
+ * Protects IOMMU states in general. Currently it protects the
+ * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace.
+ */
+ QemuMutex iommu_lock;
};
/* Find the VTD Address space associated with the given bus pointer,
projects / mirror_qemu.git / blobdiff