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hw/misc: Add a basic Aspeed LPC controller model
authorCédric Le Goater <clg@kaod.org>
Tue, 9 Mar 2021 11:01:28 +0000 (12:01 +0100)
committerCédric Le Goater <clg@kaod.org>
Tue, 9 Mar 2021 11:01:28 +0000 (12:01 +0100)
commit2ecf17264debe1bc3399fe587690c78d03e8401b
tree792d6d3331647aff8e0d1e5a587b240bcb0d19dctree
parent6820588efa4fbab9ab6f0457f2c83c3bc7498ae3commit | diff
hw/misc: Add a basic Aspeed LPC controller model

This is a very minimal framework to access registers which are used to
configure the AHB memory mapping of the flash chips on the LPC HC
Firmware address space.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Message-Id: <20210302014317.915120-5-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
docs/system/arm/aspeed.rst diff | blob | blame | history
hw/arm/aspeed_ast2600.c diff | blob | blame | history
hw/arm/aspeed_soc.c diff | blob | blame | history
hw/misc/aspeed_lpc.c [new file with mode: 0644] blob
hw/misc/meson.build diff | blob | blame | history
include/hw/arm/aspeed_soc.h diff | blob | blame | history
include/hw/misc/aspeed_lpc.h [new file with mode: 0644] blob
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