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target-xtensa: better control rsr/wsr/xsr access to SRs
authorMax Filippov <jcmvbkbc@gmail.com>
Wed, 5 Dec 2012 03:15:23 +0000 (07:15 +0400)
committerBlue Swirl <blauwirbel@gmail.com>
Sat, 8 Dec 2012 18:48:26 +0000 (18:48 +0000)
commit53593e90d13264dc88b3281ddf75ceaa641df05a
tree1012b37c8cf0e93b93130060cddbb8d4f7028f6btree
parentfe0bd475aa31e60674f7f53b85dc293108026202commit | diff
target-xtensa: better control rsr/wsr/xsr access to SRs

There are read-only (DEBUGCAUSE, PRID) and write-only (INTCLEAR) SRs,
and INTERRUPT/INTSET SR allows rsr/wsr, but not xsr. Raise illeagal
opcode exception on illegal access to these SRs.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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