]> git.proxmox.com Git - mirror_qemu.git/commit
target/riscv: Merge argument decode for RVC shifti
authorRichard Henderson <richard.henderson@linaro.org>
Mon, 1 Apr 2019 03:11:51 +0000 (10:11 +0700)
committerPalmer Dabbelt <palmer@sifive.com>
Fri, 24 May 2019 19:09:22 +0000 (12:09 -0700)
commit6cafec92f1c862a9754ef6a28be68ba7178a284d
tree56b09514f750e95317e80bb2fed7188c2edf7b40
parente1d455dd91c935c714412dafeb24db947429a929
target/riscv: Merge argument decode for RVC shifti

Special handling for IMM==0 is the only difference between
RVC shifti and RVI shifti.  This can be handled with !function.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
target/riscv/insn16.decode
target/riscv/insn_trans/trans_rvc.inc.c
target/riscv/translate.c