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target/riscv: Add Hypervisor CSR macros
authorAlistair Francis <Alistair.Francis@wdc.com>
Sat, 20 Apr 2019 02:27:26 +0000 (02:27 +0000)
committerPalmer Dabbelt <palmer@sifive.com>
Fri, 24 May 2019 19:09:24 +0000 (12:09 -0700)
commit71f09a5bb48d0c51b87e70158407ec2db4a9c6e2
tree8019927aac73fad6576f765013ee38df7c6f8c00tree
parent1f0419cb0475eebdbefea67483e85287f3af07a7commit | diff
target/riscv: Add Hypervisor CSR macros

Add the 1.10.1 Hypervisor CSRs and remove the 1.9.1 spec versions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
target/riscv/cpu_bits.h diff | blob | blame | history
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