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(parent: c670970) | patch
RISC-V: Fixes to CSR_* register macros.
authorJim Wilson <jimw@sifive.com>
Fri, 15 Mar 2019 10:26:57 +0000 (03:26 -0700)
committerPalmer Dabbelt <palmer@sifive.com>
Tue, 19 Mar 2019 12:13:24 +0000 (05:13 -0700)
commit8e73df6aa3f2f0e5c26c03a94a88406616291815
tree52760acfd6aa2efd6843157d3d2fdea401b09214tree
parentc670970dc069ebaf941a786f0608fca701dcf7d0commit | diff
RISC-V: Fixes to CSR_* register macros.

This adds some missing CSR_* register macros, and documents some as being
priv v1.9.1 specific.

Signed-off-by: Jim Wilson <jimw@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190212230830.9160-1-jimw@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
target/riscv/cpu_bits.h diff | blob | blame | history
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