]> git.proxmox.com Git - mirror_qemu.git/commit
ppc/xive: hardwire the Physical CAM line of the thread context
authorCédric Le Goater <clg@kaod.org>
Wed, 6 Mar 2019 08:50:06 +0000 (09:50 +0100)
committerDavid Gibson <david@gibson.dropbear.id.au>
Tue, 12 Mar 2019 03:33:04 +0000 (14:33 +1100)
commitd514c48d41fba59ac492433071bad70c445db566
treecad9568114e4f36c4986a097cd22df529cf438a6
parent7abb479c7abd1f03da09f34cd77d25ecf66aac82
ppc/xive: hardwire the Physical CAM line of the thread context

By default on P9, the HW CAM line (23bits) is hardwired to :

      0x000||0b1||4Bit chip number||7Bit Thread number.

When the block group mode is enabled at the controller level (PowerNV),
the CAM line is changed for CAM compares to :

      4Bit chip number||0x001||7Bit Thread number

This will require changes in xive_presenter_tctx_match() possibly.
This is a lowlevel functionality of the HW controller and it is not
strictly needed. Leave it for later.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190306085032.15744-2-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
hw/intc/xive.c