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(parent: f50a164) | patch
target-xtensa: add 64-bit floating point registers
authorMax Filippov <jcmvbkbc@gmail.com>
Mon, 29 Jun 2015 07:50:03 +0000 (10:50 +0300)
committerMax Filippov <jcmvbkbc@gmail.com>
Mon, 6 Jul 2015 10:25:11 +0000 (13:25 +0300)
commitddd44279fdbc545a9182cb642645af8a4672c267
tree2419cab26d887b77965daef5fdf552356523c589tree
parentf50a1640fb82708a5d528dee1ace42a224b95b15commit | diff
target-xtensa: add 64-bit floating point registers

Xtensa ISA got specification for 64-bit floating point registers and
opcodes, see ISA, 4.3.11 "Floating point coprocessor option".

Add 64-bit FP registers.

Although 64-bit floating point is currently not supported by xtensa
translator, these registers need to be reported to gdb with proper size,
otherwise it wouldn't find other registers.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa/cpu.h diff | blob | blame | history
target-xtensa/gdbstub.c diff | blob | blame | history
target-xtensa/overlay_tool.h diff | blob | blame | history
target-xtensa/translate.c diff | blob | blame | history
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