fsdev/p9array.h: check scalar type in P9ARRAY_NEW()
Make sure at compile time that the scalar type of the array
requested to be created via P9ARRAY_NEW() matches the scalar
type of the passed auto reference variable (unique pointer).
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Message-Id: <c1965e2a096835dc9e1d4d659dfb15d96755cbe0.1633097129.git.qemu_oss@crudebyte.com>
Implements deep auto free of arrays while retaining common C-style
squared bracket access. Main purpose of this API is to get rid of
error prone individual array deallocation pathes in user code, i.e.
turning something like this:
void doSomething(size_t n) {
Foo *foos = malloc(n * sizeof(Foo));
for (...) {
foos[i].s = malloc(...);
if (...) {
goto out;
}
}
out:
if (...) {
for (...) {
/* deep deallocation */
free(foos[i].s);
}
/* array deallocation */
free(foos);
}
}
into something more simple and safer like:
void doSomething(size_t n) {
P9ARRAY_REF(Foo) foos = NULL;
P9ARRAY_NEW(Foo, foos, n);
for (...) {
foos[i].s = malloc(...);
if (...) {
return; /* array auto freed here */
}
}
/* array auto freed here */
}
Unlike GArray, P9Array does not require special macros, function
calls or struct member dereferencing to access the individual array
elements:
So existing C-style array code can be retained with only very little
changes; basically limited to replacing array allocation call and of
course removing individual array deallocation pathes.
In this initial version P9Array only supports the concept of unique
pointers, i.e. it does not support reference counting. The array (and
all dynamically allocated memory of individual array elements) is auto
freed once execution leaves the scope of the reference variable (unique
pointer) associated with the array.
Internally a flex array struct is used in combination with macros
spanned over a continuous memory space for both the array's meta data
(private) and the actual C-array user data (public):
struct P9Array##scalar_type {
size_t len; /* private, hidden from user code */
scalar_type first[]; /* public, directly exposed to user code */
};
Which has the advantage that the compiler automatically takes care
about correct padding, alignment and overall size for all scalar data
types on all systems and that the user space exposed pointer can
directly be translated back and forth between user space C-array
pointer and internal P9Array struct whenever needed, in a type-safe
manner.
This header file is released under MIT license, to allow this file
being used in other C-projects as well. The common QEMU license
GPL2+ might have construed a conflict for other projects.
Use QEMU_ALIGN_DOWN() macro to reduce code and to make it
more human readable.
Suggested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <b84eb324d2ebdcc6f9c442c97b5b4d01eecb4f43.1632758315.git.qemu_oss@crudebyte.com>
When client sent a 9p Tgetattr request then the wrong I/O block
size value was returned by 9p server; instead of host file
system's I/O block size it should rather return an I/O block
size according to 9p session's 'msize' value, because the value
returned to client should be an "optimum" block size for I/O
(i.e. to maximize performance), it should not reflect the actual
physical block size of the underlying storage media.
The I/O block size of a host filesystem is typically 4k, so the
value returned was far too low for good 9p I/O performance.
This patch adds stat_to_iounit() with a similar approach as the
existing get_iounit() function.
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Greg Kurz <groug@kaod.org>
Message-Id: <E1mT2Js-0000DW-OH@lizzy.crudebyte.com>
Merge remote-tracking branch 'remotes/dagrh/tags/pull-virtiofs-20211026' into staging
Virtiofsd pull 2021-10-26
New 'unsupported' feature for xattr mapping
Good for hiding selinux
Plus some tidy ups and error handling. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
# gpg: Signature made Tue 26 Oct 2021 03:28:44 AM PDT
# gpg: using RSA key 45F5C71B4A0CB7FB977A9FA90516331EBC5BFDE7
# gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" [full]
* remotes/dagrh/tags/pull-virtiofs-20211026:
virtiofsd: Error on bad socket group name
virtiofsd: Add a helper to stop all queues
virtiofsd: Add a helper to send element on virtqueue
virtiofsd: Remove unused virtio_fs_config definition
virtiofsd: xattr mapping add a new type "unsupported"
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Make the '--socket-group=' option fail if the group name is unknown:
./tools/virtiofsd/virtiofsd .... --socket-group=zaphod
vhost socket: unable to find group 'zaphod'
Reported-by: Xiaoling Gao <xiagao@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-Id: <20211014122554.34599-1-dgilbert@redhat.com> Reviewed-by: Vivek Goyal <vgoyal@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Use a helper to stop all the queues. Later in the patch series I am
planning to use this helper at one more place later in the patch series.
Signed-off-by: Vivek Goyal <vgoyal@redhat.com>
Message-Id: <20210930153037.1194279-6-vgoyal@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
virtiofsd: Add a helper to send element on virtqueue
We have open coded logic to take locks and push element on virtqueue at
three places. Add a helper and use it everywhere. Code is easier to read and
less number of lines of code.
Signed-off-by: Vivek Goyal <vgoyal@redhat.com>
Message-Id: <20210930153037.1194279-5-vgoyal@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
"struct virtio_fs_config" definition seems to be unused in fuse_virtio.c.
Remove it.
Signed-off-by: Vivek Goyal <vgoyal@redhat.com>
Message-Id: <20210930153037.1194279-4-vgoyal@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
virtiofsd: xattr mapping add a new type "unsupported"
Right now for xattr remapping, we support types of "prefix", "ok" or "bad".
Type "bad" returns -EPERM on setxattr and hides xattr in listxattr. For
getxattr, mapping code returns -EPERM but getxattr code converts it to -ENODATA.
I need a new semantics where if an xattr is unsupported, then
getxattr()/setxattr() return -ENOTSUP and listxattr() should hide the xattr.
This is needed to simulate that security.selinux is not supported by
virtiofs filesystem and in that case client falls back to some default
label specified by policy.
So add a new type "unsupported" which returns -ENOTSUP on getxattr() and
setxattr() and hides xattrs in listxattr().
For example, one can use following mapping rule to not support
security.selinux xattr and allow others.
Suggested-by: "Dr. David Alan Gilbert" <dgilbert@redhat.com> Signed-off-by: Vivek Goyal <vgoyal@redhat.com>
Message-Id: <YUt9qbmgAfCFfg5t@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
When we try to use 'analyze-migration.py -x' with python3,
we have the following errors:
Traceback (most recent call last):
File "scripts/analyze-migration.py", line 593, in <module>
f.write(jsonenc.encode(dump.vmsd_desc))
TypeError: a bytes-like object is required, not 'str'
Traceback (most recent call last):
File "scripts/analyze-migration.py", line 601, in <module>
f.write(jsonenc.encode(dict))
TypeError: a bytes-like object is required, not 'str'
This happens because the file 'f' is open in binary mode while
jsonenc.encode() returns a string.
The results are human-readable files, 'desc.json' and 'state.json',
so there is no reason to use the binary mode.
Tong Ho [Fri, 15 Oct 2021 20:35:32 +0000 (13:35 -0700)]
hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse device
Signed-off-by: Tong Ho <tong.ho@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211015203532.2463705-4-tong.ho@xilinx.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Tong Ho [Fri, 15 Oct 2021 20:35:31 +0000 (13:35 -0700)]
hw/nvram: Fix Memory Leak in Xilinx Versal eFuse device
Signed-off-by: Tong Ho <tong.ho@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211015203532.2463705-3-tong.ho@xilinx.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Tong Ho [Fri, 15 Oct 2021 20:35:30 +0000 (13:35 -0700)]
hw/nvram: Fix Memory Leak in Xilinx eFuse QOM
Signed-off-by: Tong Ho <tong.ho@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211015203532.2463705-2-tong.ho@xilinx.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Commit 9458a9a1df1a4c719e24512394d548c1fc7abd22 added synchronization
of vCPU and migration operations through calling run_on_cpu operation.
However, in replay mode this synchronization is unneeded, because
I/O and vCPU threads are already synchronized.
This patch disables such synchronization for record/replay mode.
Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <163429018454.1146856.3429437540871060739.stgit@bahia.huguette> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-20211022-2' into staging
Fourth RISC-V PR for QEMU 6.2
- Vector extension bug fixes
- Bit manipulation extension bug fix
- Support vhost-user and numa mem options on all boards
- Rationalise XLEN and operand lengths
- Bump the OpenTitan FPGA support
- Remove the Ibex PLIC
- General code cleanup
# gpg: Signature made Fri 22 Oct 2021 06:36:10 AM PDT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
* remotes/alistair23/tags/pull-riscv-to-apply-20211022-2: (33 commits)
hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
hw/intc: sifive_plic: Cleanup the irq_request function
hw/intc: sifive_plic: Cleanup the realize function
hw/intc: sifive_plic: Move the properties
hw/intc: Remove the Ibex PLIC
hw/riscv: opentitan: Update to the latest build
target/riscv: Compute mstatus.sd on demand
target/riscv: Use riscv_csrrw_debug for cpu_dump
target/riscv: Use gen_shift*_per_ol for RVB, RVI
target/riscv: Use gen_unary_per_ol for RVB
target/riscv: Adjust trans_rev8_32 for riscv64
target/riscv: Use gen_arith_per_ol for RVM
target/riscv: Replace DisasContext.w with DisasContext.ol
target/riscv: Replace is_32bit with get_xl/get_xlen
target/riscv: Properly check SEW in amo_op
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Since commit 12b6e9b27d4 ("disas: Clean up CPUDebug initialization")
the disassemble_info->bfd_endian enum is set for all targets in
target_disas(). We can directly call print_insn_nios2() and simplify.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20210807110939.95853-3-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Merge remote-tracking branch 'remotes/clg/tags/pull-aspeed-20211022' into staging
Aspeed patches :
* New fp5280g2-bmc board (John)
* Small cleanup in Aspeed SMC model (Cedric)
# gpg: Signature made Fri 22 Oct 2021 12:55:18 AM PDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [marginal]
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg: It is not certain that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* remotes/clg/tags/pull-aspeed-20211022:
speed/sdhci: Add trace events
aspeed/smc: Use a container for the flash mmio address space
aspeed: Add support for the fp5280g2-bmc board
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
# gpg: Signature made Fri 22 Oct 2021 12:16:29 AM PDT
# gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg: issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
* remotes/vivier-m68k/tags/q800-pull-request:
q800: drop 8-bit graphic_depth check for Apple 21 inch display
q800: add NMI handler
q800: wire up remaining IRQs in classic mode
q800: route SONIC on-board Ethernet IRQ via nubus IRQ 9 in classic mode
q800: wire up auxmode GPIO to GLUE
mac_via: add GPIO for A/UX mode
q800: use GLUE IRQ numbers instead of IRQ level for GLUE IRQs
q800: move VIA1 IRQ from level 1 to level 6
mac_via: update comment for VIA1B_vMystery bit
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Bin Meng [Wed, 20 Oct 2021 01:41:12 +0000 (09:41 +0800)]
hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211020014112.7336-7-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Bin Meng [Wed, 20 Oct 2021 01:41:11 +0000 (09:41 +0800)]
hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211020014112.7336-6-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Bin Meng [Wed, 20 Oct 2021 01:41:10 +0000 (09:41 +0800)]
hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
While at it add check for user supplied RAM size and error out if it
mismatches board expected value.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20211020014112.7336-5-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Bin Meng [Wed, 20 Oct 2021 01:41:09 +0000 (09:41 +0800)]
hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211020014112.7336-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Bin Meng [Wed, 20 Oct 2021 01:41:08 +0000 (09:41 +0800)]
hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
While at it add check for user supplied RAM size and error out if it
mismatches board expected value.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20211020014112.7336-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Bin Meng [Wed, 20 Oct 2021 01:41:07 +0000 (09:41 +0800)]
hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20211020014112.7336-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
The position of this read-only field is dependent on the current xlen.
Rather than having to compute that difference in many places, compute
it only on read.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-16-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Use the official debug read interface to the csrs,
rather than referencing the env slots directly.
Put the list of csrs to dump into a table.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-15-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Most shift instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-14-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
The count zeros instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-13-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-12-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
The multiply high-part instructions require a separate
implementation for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-11-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Gerd Hoffmann [Fri, 22 Oct 2021 10:19:16 +0000 (12:19 +0200)]
update seabios to master branch snapshot
A new seabios release is planned for november.
Update to a master branch snapshot, to
(a) increase test coverage of the changes.
(b) make the delta smaller when updating to the final
release during the qemu 6.2 freeze.
Most noteworthy this fixes the nvme boot regression caused
by adding namespace support to the qemu nvme emulation.
seabios shortlog
================
Alex Martens via SeaBIOS (1):
nvme: fix missing newline on sq full print
Alexander Graf (4):
nvme: Record maximum allowed request size
nvme: Allow to set PRP2
nvme: Pass large I/O requests as PRP lists
nvme: Split requests by maximum allowed size
Daniel P. Berrangé (1):
smbios: avoid integer overflow when adding SMBIOS type 0 table
David Woodhouse (1):
nvme: Clean up nvme_cmd_readwrite()
Gerd Hoffmann (9):
output: add support for uppercase hex numbers
dsdt: add support for pnp ids as strings
usb: add boot prio support for mmio host adapters
usb/xhci: split xhci setup into generic and pci parts
usb/xhci: add support for mmio host adapters (via acpi).
usb boot: add xhci mmio example
nvme: improve namespace allocation
nvme: drive desc should not include the newline
Increase BUILD_MIN_BIOSTABLE for large roms
Matt DeVillier (1):
usb.c: Fix devices using non-primary interface descriptor
Mike Banon (1):
Support booting USB drives with a write protect switch enabled
Sergei Trofimovich (1):
vgasrc: ignore .node.gnu.property (binutils-2.36 support)
Stefan Berger (4):
tcgbios: Fix details in log entries
Add implementations for sha256, sha384, and sha512
tcgbios: Use The proper sha function for each PCR bank
tcgbios: Disable platform hierarchy in case of failure
Stefan Ott via SeaBIOS (1):
usb-hid: Increase MAX_KBD_EVENT
Volker Rümelin (2):
stacks: call check_irqs() in run_thread()
stacks: call check_irqs() after switch_next()
weitaowang-oc@zhaoxin.com (1):
USB:Fix xHCI initail fail by using longer reset and CNR clear timeout value
Cédric Le Goater [Fri, 22 Oct 2021 07:52:17 +0000 (09:52 +0200)]
speed/sdhci: Add trace events
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20211018132609.160008-6-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Cédric Le Goater [Fri, 22 Oct 2021 07:52:17 +0000 (09:52 +0200)]
aspeed/smc: Use a container for the flash mmio address space
Because AddressSpaces must not be sysbus-mapped, commit e9c568dbc225
("hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use
alias") introduced an alias for the flash mmio region.
Using a container is cleaner.
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20211018132609.160008-5-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: John Wang <wangzhiqiang02@inspur.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211014064548.934799-1-wangzhiqiang02@inspur.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
target/riscv: Replace DisasContext.w with DisasContext.ol
In preparation for RV128, consider more than just "w" for
operand size modification. This will be used for the "d"
insns from RV128 as well.
Rename oper_len to get_olen to better match get_xlen.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-10-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv: Replace is_32bit with get_xl/get_xlen
In preparation for RV128, replace a simple predicate
with a more versatile test.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-9-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
We're currently assuming SEW <= 3, and the "else" from
the SEW == 3 must be less. Use a switch and explicitly
bound both SEW and SEQ for all cases.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-8-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Use the same REQUIRE_64BIT check that we use elsewhere,
rather than open-coding the use of is_32bit.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-7-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Begin adding support for switching XLEN at runtime. Extract the
effective XLEN from MISA and MSTATUS and store for use during translation.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-6-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
Shortly, the set of supported XL will not be just 32 and 64,
and representing that properly using the enumeration will be
imperative.
Two places, booting and gdb, intentionally use misa_mxl_max
to emphasize the use of the reset value of misa.mxl, and not
the current cpu state.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-5-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
The hw representation of misa.mxl is at the high bits of the
misa csr. Representing this in the same way inside QEMU
results in overly complex code trying to check that field.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-4-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-3-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv: Move cpu_get_tb_cpu_state out of line
Move the function to cpu_helper.c, as it is large and growing.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-2-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Alistair Francis [Mon, 18 Oct 2021 04:32:15 +0000 (14:32 +1000)]
target/riscv: Organise the CPU properties
Organise the CPU properties so that standard extensions come first
then followed by experimental extensions.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: b6598570f60c5ee7f402be56d837bb44b289cc4d.1634531504.git.alistair.francis@wdc.com
Alistair Francis [Mon, 18 Oct 2021 04:32:00 +0000 (14:32 +1000)]
target/riscv: Remove some unused macros
Since commit 1a9540d1f1a
("target/riscv: Drop support for ISA spec version 1.09.1")
these definitions are unused, remove them.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: f4d8a7a035f39c0a35d44c1e371c5c99cc2fa15a.1634531504.git.alistair.francis@wdc.com
Frank Chang [Fri, 15 Oct 2021 07:45:02 +0000 (15:45 +0800)]
target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
commit: c445593, but other TB_FLAGS bits for rvv and rvh were
not shift as well so these bits may overlap with each other when
rvv is enabled.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211015074627.3957162-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Mingwang Li [Sat, 16 Oct 2021 03:09:08 +0000 (11:09 +0800)]
hw/riscv: virt: Use machine->ram as the system memory
If default main_mem is used to be registered as the system memory,
other memory cannot be initialized. Therefore, the system memory
should be initialized to the machine->ram, which consists of the
default main_mem and other possible memory required by applications,
such as shared hugepage memory in DPDK.
Also, the mc->defaul_ram_id should be set to the default main_mem,
such as "riscv_virt_board.ram" for the virt machine.
Signed-off-by: Mingwang Li <limingwang@huawei.com> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211016030908.40480-1-limingwang@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Philipp Tomsich [Wed, 13 Oct 2021 18:41:25 +0000 (20:41 +0200)]
target/riscv: Fix orc.b implementation
The earlier implementation fell into a corner case for bytes that were
0x01, giving a wrong result (but not affecting our application test
cases for strings, as an ASCII value 0x01 is rare in those...).
This changes the algorithm to:
1. Mask out the high-bit of each bytes (so that each byte is <= 127).
2. Add 127 to each byte (i.e. if the low 7 bits are not 0, this will overflow
into the highest bit of each byte).
3. Bitwise-or the original value back in (to cover those cases where the
source byte was exactly 128) to saturate the high-bit.
4. Shift-and-mask (implemented as a mask-and-shift) to extract the MSB of
each byte into its LSB.
5. Multiply with 0xff to fan out the LSB to all bits of each byte.
Fixes: d7a4fcb034 ("target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci") Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reported-by: Vincent Palatin <vpalatin@rivosinc.com> Tested-by: Vincent Palatin <vpalatin@rivosinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211013184125.2010897-1-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Thu, 7 Oct 2021 08:17:41 +0000 (16:17 +0800)]
target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
oprsz and maxsz are passed with the same value in commit: eee2d61e202.
However, vmv.v.v was missed in that commit and should pass the same
value as well in its tcg_gen_gvec_2_ptr() call.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211007081803.1705656-1-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Merge remote-tracking branch 'remotes/rth/tags/pull-arm-20211021' into staging
Introduce cpu topology support
Generate DBG2 table
Switch to ssize_t for elf loader return type
Fixed sbsa cpu type error message typo
Only initialize required submodules for edk2
Dont create device-tree node for empty NUMA node
# gpg: Signature made Thu 21 Oct 2021 08:22:32 AM PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* remotes/rth/tags/pull-arm-20211021:
tests/data/acpi/virt: Update the empty expected file for PPTT
hw/arm/virt-acpi-build: Generate PPTT table
tests/data/acpi/virt: Add an empty expected file for PPTT
hw/acpi/aml-build: Add PPTT table
hw/acpi/aml-build: Add Processor hierarchy node structure
hw/arm/virt: Add cpu-map to device tree
device_tree: Add qemu_fdt_add_path
hw/arm/virt: Only describe cpu topology since virt-6.2
bios-tables-test: Generate reference table for virt/DBG2
hw/arm/virt_acpi_build: Generate DBG2 table
tests/acpi: Add void table for virt/DBG2 bios-tables-test
hw/elf_ops.h: switch to ssize_t for elf loader return type
hw/arm/sbsa-ref: Fixed cpu type error message typo.
roms/edk2: Only initialize required submodules
roms/edk2: Only init brotli submodule to build BaseTools
hw/arm/virt: Don't create device-tree node for empty NUMA node
tests/acpi: Generate reference blob for IORT rev E.b
hw/arm/virt-acpi-build: IORT upgrade up to revision E.b
tests/acpi: Get prepared for IORT E.b revision upgrade
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-6.2-20211021' into staging
ppc patch queue 2021-10-21
Here's the next batch of ppc target related patches for qemu-6.2.
Highlights are:
* Some fixes and minimal tests for old embedded ppc platforms
* The beginnings of PMU emulation in TCG from Daniel Barboza
* Some improvements to the pegasos2 platform
* A number of TCG bugfixes from the folks at the El Dorado Institute
* A few other assorted bugfixes and cleanups
* remotes/dgibson/tags/ppc-for-6.2-20211021: (25 commits)
hw/ppc/ppc4xx_pci: Fix ppc4xx_pci_map_irq() for recent Linux kernels
target/ppc: adding user read/write functions for PMCs
target/ppc: add user read/write functions for MMCR2
target/ppc: add user read/write functions for MMCR0
target/ppc: add MMCR0 PMCC bits to hflags
target/ppc: Filter mtmsr[d] input before setting MSR
tests/acceptance: Add a test for the bamboo ppc board
ppc/pegasos2: Implement power-off RTAS function with VOF
ppc/pegasos2: Add constants for PCI config addresses
ppc/pegasos2: Access MV64361 registers via their memory region
ppc/pegasos2: Implement get-time-of-day RTAS function with VOF
ppc/pegasos2: Warn when using VOF but no kernel is specified
ppc/pegasos2: Restrict memory to 2 gigabytes
target/ppc: Fix XER access in monitor
linux-user: Fix XER access in ppc version of elf_core_copy_regs
target/ppc: Fix XER access in gdbstub
linux-user/ppc: Fix XER access in save/restore_user_regs
tests/acceptance: Add tests for the ppc405 boards
hw/ppc: Fix iothread locking in the 405 code
spapr/xive: Use xive_esb_rw() to trigger interrupts
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Message-Id: <20211020142125.7516-9-wangyanan55@huawei.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Yanan Wang [Wed, 20 Oct 2021 14:21:24 +0000 (22:21 +0800)]
hw/arm/virt-acpi-build: Generate PPTT table
Generate the Processor Properties Topology Table (PPTT) for ARM
virt machines supporting it (>= 6.2).
Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-Id: <20211020142125.7516-8-wangyanan55@huawei.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Yanan Wang [Wed, 20 Oct 2021 14:21:23 +0000 (22:21 +0800)]
tests/data/acpi/virt: Add an empty expected file for PPTT
Add a generic empty binary file for the new introduced PPTT table
under tests/data/acpi/virt, and list it as files to be changed in
tests/qtest/bios-tables-test-allowed-diff.h
Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-Id: <20211020142125.7516-7-wangyanan55@huawei.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Andrew Jones [Wed, 20 Oct 2021 14:21:22 +0000 (22:21 +0800)]
hw/acpi/aml-build: Add PPTT table
Add the Processor Properties Topology Table (PPTT) used to
describe CPU topology information to ACPI guests.
Note, a DT-boot Linux guest with a non-flat CPU topology will
see socket and core IDs being sequential integers starting
from zero, which is different from ACPI-boot Linux guest,
e.g. with -smp 4,sockets=2,cores=2,threads=1
1) DT cpu nodes do not have an equivalent field to what the PPTT
ACPI Processor ID must be, i.e. something equal to the MADT CPU
UID or equal to the UID of an ACPI processor container. In both
ACPI cases those are platform dependant IDs assigned by the
vendor.
2) While QEMU is the vendor for a guest, if the topology specifies
SMT (> 1 thread), then, with ACPI, it is impossible to assign a
core-id the same value as a package-id, thus it is not possible
to have package-id=0 and core-id=0. This is because package and
core containers must be in the same ACPI namespace and therefore
must have unique UIDs.
3) ACPI processor containers are not mandatorily required for PPTT
tables to be used and, due to the limitations of which IDs are
selected described above in (2), they are not helpful for QEMU,
so we don't build them with this patch. In the absence of them,
Linux assigns its own unique IDs. The maintainers have chosen not
to use counters from zero, but rather ACPI table offsets, which
explains why the numbers are so much larger than with DT.
4) When there is no SMT (threads=1) the core IDs for ACPI boot guests
match the logical CPU IDs, because these IDs must be equal to the
MADT CPU UID (as no processor containers are present), and QEMU
uses the logical CPU ID for these MADT IDs.
So in summary, with QEMU as the vendor for the guests, we simply
use sequential integers starting from zero for the non-leaf nodes
but with ID-valid flag unset, so that guest will ignore them and
use table offsets as unique container IDs. And we use logical CPU
IDs for the leaf nodes with the ID-valid flag set, which will be
consistent with MADT.
Currently the implementation of PPTT generation complies with ACPI
specification 5.2.29 (Revision 6.3). The 6.3 spec can be found at:
https://uefi.org/sites/default/files/resources/ACPI_6_3_May16.pdf
Reviewed-by: Eric Auger <eric.auger@redhat.com> Co-developed-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20211020142125.7516-6-wangyanan55@huawei.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Add a generic API to build Processor hierarchy node structure (Type 0),
which is strictly consistent with descriptions in ACPI 6.3: 5.2.29.1.
This function will be used to build ACPI PPTT table for cpu topology.
Co-developed-by: Ying Fang <fangying1@huawei.com> Co-developed-by: Henglong Fan <fanhenglong@huawei.com> Co-developed-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-Id: <20211020142125.7516-5-wangyanan55@huawei.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Andrew Jones [Wed, 20 Oct 2021 14:21:20 +0000 (22:21 +0800)]
hw/arm/virt: Add cpu-map to device tree
Support device tree CPU topology descriptions.
In accordance with the Devicetree Specification, the Linux Doc
"arm/cpus.yaml" requires that cpus and cpu nodes in the DT are
present. And we have already met the requirement by generating
/cpus/cpu@* nodes for members within ms->smp.cpus. Accordingly,
we should also create subnodes in cpu-map for the present cpus,
each of which relates to an unique cpu node.
The Linux Doc "cpu/cpu-topology.txt" states that the hierarchy
of CPUs in a SMP system is defined through four entities and
they are socket/cluster/core/thread. It is also required that
a socket node's child nodes must be one or more cluster nodes.
Given that currently we are only provided with information of
socket/core/thread, we assume there is one cluster child node
in each socket node when creating cpu-map.
Co-developed-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Message-Id: <20211020142125.7516-4-wangyanan55@huawei.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Yanan Wang [Wed, 20 Oct 2021 14:21:19 +0000 (22:21 +0800)]
device_tree: Add qemu_fdt_add_path
qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except it
also adds all missing subnodes from the given path. We'll use it
in a coming patch where we will add cpu-map to the device tree.
And we also tweak an error message of qemu_fdt_add_subnode().
Co-developed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Andrew Jones <drjones@redhat.com> Cc: David Gibson <david@gibson.dropbear.id.au> Cc: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211020142125.7516-3-wangyanan55@huawei.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Yanan Wang [Wed, 20 Oct 2021 14:21:18 +0000 (22:21 +0800)]
hw/arm/virt: Only describe cpu topology since virt-6.2
On existing older machine types, without cpu topology described
in ACPI or DT, the guest will populate one by default. With the
topology described, it will read the information and set up its
topology as instructed, but that may not be the same as what was
getting used by default. It's possible that an user application
has a dependency on the default topology and if the default one
gets changed it will probably behave differently.
Based on above consideration we'd better only describe topology
information to the guest on 6.2 and later machine types.
Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-Id: <20211020142125.7516-2-wangyanan55@huawei.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Eric Auger [Tue, 19 Oct 2021 08:00:37 +0000 (10:00 +0200)]
bios-tables-test: Generate reference table for virt/DBG2
Add the DBG2 table generated with
tests/data/acpi/rebuild-expected-aml.sh
Signed-off-by: Eric Auger <eric.auger@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20211019080037.930641-4-eric.auger@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Eric Auger [Tue, 19 Oct 2021 08:00:36 +0000 (10:00 +0200)]
hw/arm/virt_acpi_build: Generate DBG2 table
ARM SBBR specification mandates DBG2 table (Debug Port Table 2)
since v1.0 (ARM DEN0044F 8.3.1.7 DBG2).
The DBG2 table allows to describe one or more debug ports.
Generate an DBG2 table featuring a single debug port, the PL011.
The DBG2 specification can be found at
"Microsoft Debug Port Table 2 (DBG2)"
https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table?redirectedfrom=MSDN
Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20211019080037.930641-3-eric.auger@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Eric Auger [Tue, 19 Oct 2021 08:00:35 +0000 (10:00 +0200)]
tests/acpi: Add void table for virt/DBG2 bios-tables-test
Add placeholders for DBG2 reference table for
virt tests and ignore till reference blob is added.
Signed-off-by: Eric Auger <eric.auger@redhat.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20211019080037.930641-2-eric.auger@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Thomas Huth [Tue, 19 Oct 2021 09:18:17 +0000 (11:18 +0200)]
hw/ppc/ppc4xx_pci: Fix ppc4xx_pci_map_irq() for recent Linux kernels
Recent Linux kernels are accessing the PCI device in slot 0 that
represents the PCI host bridge. This causes ppc4xx_pci_map_irq()
to return -1 which causes an assert() later:
Thus we should allocate an IRQ line for the device in slot 0, too.
To avoid changes to the outside of ppc4xx_pci.c, we map it to
the internal IRQ number 4 which will then happily be ignored since
ppc440_bamboo.c does not wire it up.
With these changes it is now possible again to use recent Linux
kernels for the bamboo board.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20211019091817.469003-1-thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
target/ppc: adding user read/write functions for PMCs
Problem state needs to be able to read and write the PMU counters,
otherwise it won't be aware of any sampling result that the PMU produces
after a Perf run.
This patch does that in a similar fashion as already done in the
previous patches. PMCs 5 and 6 have a special condition, aside from the
constraints that are common with PMCs 1-4, where they are not part of the
PMU if MMCR0_PMCC is 0b11.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211018010133.315842-5-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
target/ppc: add user read/write functions for MMCR2
Similar to the previous patch, let's add problem state read/write access to
the MMCR2 SPR, which is also a group A PMU SPR that needs to be filtered
to be read/written by userspace.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211018010133.315842-4-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Gustavo Romero [Mon, 18 Oct 2021 01:01:20 +0000 (22:01 -0300)]
target/ppc: add user read/write functions for MMCR0
Userspace need access to PMU SPRs to be able to operate the PMU. One of
such SPRs is MMCR0.
MMCR0, as defined by PowerISA v3.1, is classified as a 'group A' PMU
register. This class of registers has common read/write rules that are
governed by MMCR0 PMCC bits. MMCR0 is also not fully exposed to problem
state: only MMCR0_FC, MMCR0_PMAO and MMCR0_PMAE bits are
readable/writable in this case.
This patch exposes MMCR0 to userspace by doing the following:
- two new callbacks, spr_read_MMCR0_ureg() and spr_write_MMCR0_ureg(),
are added to be used as problem state read/write callbacks of UMMCR0.
Both callbacks filters the amount of bits userspace is able to
read/write by using a MMCR0_UREG_MASK;
- problem state access control is done by the spr_groupA_read_allowed()
and spr_groupA_write_allowed() helpers. These helpers will read the
current PMCC bits from DisasContext and check whether the read/write
MMCR0 operation is valid or noti;
- to avoid putting exclusive PMU logic into the already loaded
translate.c file, let's create a new 'power8-pmu-regs.c.inc' file that
will hold all the spr_read/spr_write functions of PMU registers.
The 'power8' name of this new file intends to hint about the proven
support of the PMU logic to be added. The code has been tested with the
IBM POWER chip family, POWER8 being the oldest version tested. This
doesn't mean that the PMU logic will break with any other PPC64 chip
that implements Book3s, but rather that we can't assert that it works
properly with any Book3s compliant chip.
CC: Gustavo Romero <gustavo.romero@linaro.org> Signed-off-by: Gustavo Romero <gromero@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211018010133.315842-3-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
We're going to add PMU support for TCG PPC64 chips, based on IBM POWER8+
emulation and following PowerISA v3.1. This requires several PMU related
registers to be exposed to userspace (problem state). PowerISA v3.1
dictates that the PMCC bits of the MMCR0 register controls the level of
access of the PMU registers to problem state.
This patch start things off by exposing both PMCC bits to hflags,
allowing us to access them via DisasContext in the read/write callbacks
that we're going to add next.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211018010133.315842-2-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Matheus Ferst [Fri, 15 Oct 2021 18:19:40 +0000 (15:19 -0300)]
target/ppc: Filter mtmsr[d] input before setting MSR
PowerISA says that mtmsr[d] "does not alter MSR[HV], MSR[S], MSR[ME], or
MSR[LE]", but the current code only filters the GPR-provided value if
L=1. This behavior caused some problems in FreeBSD, and a build option
was added to work around the issue [1], but it seems that the bug was
not reported in launchpad/gitlab. This patch address the issue in qemu,
so the option on FreeBSD should no longer be required.
Thomas Huth [Fri, 15 Oct 2021 09:00:08 +0000 (11:00 +0200)]
tests/acceptance: Add a test for the bamboo ppc board
The kernel and initrd from the "Aboriginal Linux" project can be
used to run some tests on the bamboo ppc machine.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20211015090008.1299609-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
BALATON Zoltan [Thu, 14 Oct 2021 19:50:19 +0000 (21:50 +0200)]
ppc/pegasos2: Access MV64361 registers via their memory region
Instead of relying on the mapped address of the MV64361 registers
access them via their memory region. This is not a problem at reset
time when these registers are mapped at the default address but the
guest could change this later and then the RTAS calls accessing PCI
config registers could fail. None of the guests actually do this so
this only avoids a theoretical problem not seen in practice.
BALATON Zoltan [Thu, 14 Oct 2021 19:50:19 +0000 (21:50 +0200)]
ppc/pegasos2: Warn when using VOF but no kernel is specified
Issue a warning when using VOF (which is the default) but no -kernel
option given to let users know that it will likely fail as the guest
has nothing to run. It is not a hard error because it may still be
useful to start the machine without further options for testing or
inspecting it from monitor without actually booting it.
BALATON Zoltan [Thu, 14 Oct 2021 19:50:19 +0000 (21:50 +0200)]
ppc/pegasos2: Restrict memory to 2 gigabytes
The CHRP spec this board confirms to only allows 2 GiB of system
memory below 4 GiB as the high 2 GiB is allocated to IO and system
resources. To avoid problems with memory overlapping these areas
restrict RAM to 2 GiB similar to mac_newworld.
Matheus Ferst [Thu, 14 Oct 2021 22:32:34 +0000 (19:32 -0300)]
target/ppc: Fix XER access in monitor
We can't read env->xer directly, as it does not contain some bits of
XER. Instead, we should have a callback that uses cpu_read_xer to read
the complete register.
Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER") Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211014223234.127012-5-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Matheus Ferst [Thu, 14 Oct 2021 22:32:33 +0000 (19:32 -0300)]
linux-user: Fix XER access in ppc version of elf_core_copy_regs
env->xer doesn't hold some bits of XER, like OV and CA. To write the
complete register in the core dump we should read XER value with
cpu_read_xer.
Reported-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER") Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211014223234.127012-4-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Matheus Ferst [Thu, 14 Oct 2021 22:32:32 +0000 (19:32 -0300)]
target/ppc: Fix XER access in gdbstub
The value of XER is split in multiple fields of CPUPPCState, like
env->xer and env->so. To get/set the whole register from gdb, we should
use cpu_read_xer/cpu_write_xer.
Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER") Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211014223234.127012-3-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Matheus Ferst [Thu, 14 Oct 2021 22:32:31 +0000 (19:32 -0300)]
linux-user/ppc: Fix XER access in save/restore_user_regs
We should use cpu_read_xer/cpu_write_xer to save/restore the complete
register since some of its bits are in other fields of CPUPPCState. A
test is added to prevent future regressions.
Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER") Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211014223234.127012-2-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Thomas Huth [Mon, 11 Oct 2021 12:59:30 +0000 (14:59 +0200)]
tests/acceptance: Add tests for the ppc405 boards
Using the U-Boot firmware, we can check that at least the serial console
of the ppc405 boards is still usable.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20211011125930.750217-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
[dwg: Added an extra tag at Philippe's suggestion] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Running QEMU with "-d in_asm" shows that the crash happens when writing
to SPR 0x3f2, so we are missing to lock the iothread in the code path
here.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20211006071140.565952-1-thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit 962104f0448 ("hw/ppc: moved hcalls that depend on softmmu")
introduced a lot of unnecessary #include directives. Remove them.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20211006170801.178023-1-philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
projects / mirror_qemu.git / log