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b3901d54 CM |
1 | /* |
2 | * Based on arch/arm/include/asm/mmu_context.h | |
3 | * | |
4 | * Copyright (C) 1996 Russell King. | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #ifndef __ASM_MMU_CONTEXT_H | |
20 | #define __ASM_MMU_CONTEXT_H | |
21 | ||
38fd94b0 CC |
22 | #define FALKOR_RESERVED_ASID 1 |
23 | ||
24 | #ifndef __ASSEMBLY__ | |
25 | ||
b3901d54 CM |
26 | #include <linux/compiler.h> |
27 | #include <linux/sched.h> | |
ef8bd77f | 28 | #include <linux/sched/hotplug.h> |
589ee628 | 29 | #include <linux/mm_types.h> |
b3901d54 CM |
30 | |
31 | #include <asm/cacheflush.h> | |
39bc88e5 | 32 | #include <asm/cpufeature.h> |
b3901d54 CM |
33 | #include <asm/proc-fns.h> |
34 | #include <asm-generic/mm_hooks.h> | |
35 | #include <asm/cputype.h> | |
36 | #include <asm/pgtable.h> | |
adf75899 | 37 | #include <asm/sysreg.h> |
9e8e865b | 38 | #include <asm/tlbflush.h> |
b3901d54 | 39 | |
ec45d1cf WD |
40 | static inline void contextidr_thread_switch(struct task_struct *next) |
41 | { | |
d3ea42aa MR |
42 | if (!IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR)) |
43 | return; | |
44 | ||
adf75899 MR |
45 | write_sysreg(task_pid_nr(next), contextidr_el1); |
46 | isb(); | |
ec45d1cf | 47 | } |
ec45d1cf | 48 | |
b3901d54 CM |
49 | /* |
50 | * Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0. | |
51 | */ | |
52 | static inline void cpu_set_reserved_ttbr0(void) | |
53 | { | |
2077be67 | 54 | unsigned long ttbr = __pa_symbol(empty_zero_page); |
b3901d54 | 55 | |
adf75899 MR |
56 | write_sysreg(ttbr, ttbr0_el1); |
57 | isb(); | |
b3901d54 CM |
58 | } |
59 | ||
b46aeeb3 WD |
60 | static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm) |
61 | { | |
62 | BUG_ON(pgd == swapper_pg_dir); | |
63 | cpu_set_reserved_ttbr0(); | |
64 | cpu_do_switch_mm(virt_to_phys(pgd),mm); | |
65 | } | |
66 | ||
dd006da2 AB |
67 | /* |
68 | * TCR.T0SZ value to use when the ID map is active. Usually equals | |
69 | * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in | |
70 | * physical memory, in which case it will be smaller. | |
71 | */ | |
72 | extern u64 idmap_t0sz; | |
73 | ||
74 | static inline bool __cpu_uses_extended_idmap(void) | |
75 | { | |
76 | return (!IS_ENABLED(CONFIG_ARM64_VA_BITS_48) && | |
77 | unlikely(idmap_t0sz != TCR_T0SZ(VA_BITS))); | |
78 | } | |
79 | ||
dd006da2 AB |
80 | /* |
81 | * Set TCR.T0SZ to its default value (based on VA_BITS) | |
82 | */ | |
609116d2 | 83 | static inline void __cpu_set_tcr_t0sz(unsigned long t0sz) |
dd006da2 | 84 | { |
c51e97d8 WD |
85 | unsigned long tcr; |
86 | ||
87 | if (!__cpu_uses_extended_idmap()) | |
88 | return; | |
89 | ||
adf75899 MR |
90 | tcr = read_sysreg(tcr_el1); |
91 | tcr &= ~TCR_T0SZ_MASK; | |
92 | tcr |= t0sz << TCR_T0SZ_OFFSET; | |
93 | write_sysreg(tcr, tcr_el1); | |
94 | isb(); | |
dd006da2 AB |
95 | } |
96 | ||
609116d2 MR |
97 | #define cpu_set_default_tcr_t0sz() __cpu_set_tcr_t0sz(TCR_T0SZ(VA_BITS)) |
98 | #define cpu_set_idmap_tcr_t0sz() __cpu_set_tcr_t0sz(idmap_t0sz) | |
99 | ||
9e8e865b MR |
100 | /* |
101 | * Remove the idmap from TTBR0_EL1 and install the pgd of the active mm. | |
102 | * | |
103 | * The idmap lives in the same VA range as userspace, but uses global entries | |
104 | * and may use a different TCR_EL1.T0SZ. To avoid issues resulting from | |
105 | * speculative TLB fetches, we must temporarily install the reserved page | |
106 | * tables while we invalidate the TLBs and set up the correct TCR_EL1.T0SZ. | |
107 | * | |
108 | * If current is a not a user task, the mm covers the TTBR1_EL1 page tables, | |
109 | * which should not be installed in TTBR0_EL1. In this case we can leave the | |
110 | * reserved page tables in place. | |
111 | */ | |
112 | static inline void cpu_uninstall_idmap(void) | |
113 | { | |
114 | struct mm_struct *mm = current->active_mm; | |
115 | ||
116 | cpu_set_reserved_ttbr0(); | |
117 | local_flush_tlb_all(); | |
118 | cpu_set_default_tcr_t0sz(); | |
119 | ||
39bc88e5 | 120 | if (mm != &init_mm && !system_uses_ttbr0_pan()) |
9e8e865b MR |
121 | cpu_switch_mm(mm->pgd, mm); |
122 | } | |
123 | ||
609116d2 MR |
124 | static inline void cpu_install_idmap(void) |
125 | { | |
126 | cpu_set_reserved_ttbr0(); | |
127 | local_flush_tlb_all(); | |
128 | cpu_set_idmap_tcr_t0sz(); | |
129 | ||
2077be67 | 130 | cpu_switch_mm(lm_alias(idmap_pg_dir), &init_mm); |
609116d2 MR |
131 | } |
132 | ||
50e1881d MR |
133 | /* |
134 | * Atomically replaces the active TTBR1_EL1 PGD with a new VA-compatible PGD, | |
135 | * avoiding the possibility of conflicting TLB entries being allocated. | |
136 | */ | |
137 | static inline void cpu_replace_ttbr1(pgd_t *pgd) | |
138 | { | |
139 | typedef void (ttbr_replace_func)(phys_addr_t); | |
140 | extern ttbr_replace_func idmap_cpu_replace_ttbr1; | |
141 | ttbr_replace_func *replace_phys; | |
142 | ||
143 | phys_addr_t pgd_phys = virt_to_phys(pgd); | |
144 | ||
2077be67 | 145 | replace_phys = (void *)__pa_symbol(idmap_cpu_replace_ttbr1); |
50e1881d MR |
146 | |
147 | cpu_install_idmap(); | |
148 | replace_phys(pgd_phys); | |
149 | cpu_uninstall_idmap(); | |
150 | } | |
151 | ||
5aec715d WD |
152 | /* |
153 | * It would be nice to return ASIDs back to the allocator, but unfortunately | |
154 | * that introduces a race with a generation rollover where we could erroneously | |
155 | * free an ASID allocated in a future generation. We could workaround this by | |
156 | * freeing the ASID from the context of the dying mm (e.g. in arch_exit_mmap), | |
157 | * but we'd then need to make sure that we didn't dirty any TLBs afterwards. | |
158 | * Setting a reserved TTBR0 or EPD0 would work, but it all gets ugly when you | |
159 | * take CPU migration into account. | |
160 | */ | |
b3901d54 | 161 | #define destroy_context(mm) do { } while(0) |
5aec715d | 162 | void check_and_switch_context(struct mm_struct *mm, unsigned int cpu); |
b3901d54 | 163 | |
65da0a8e | 164 | #define init_new_context(tsk,mm) ({ atomic64_set(&(mm)->context.id, 0); 0; }) |
b3901d54 | 165 | |
39bc88e5 CM |
166 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
167 | static inline void update_saved_ttbr0(struct task_struct *tsk, | |
168 | struct mm_struct *mm) | |
b3901d54 | 169 | { |
82dcf928 WD |
170 | u64 ttbr; |
171 | ||
172 | if (!system_uses_ttbr0_pan()) | |
173 | return; | |
174 | ||
175 | if (mm == &init_mm) | |
176 | ttbr = __pa_symbol(empty_zero_page); | |
177 | else | |
178 | ttbr = virt_to_phys(mm->pgd) | ASID(mm) << 48; | |
179 | ||
180 | task_thread_info(tsk)->ttbr0 = ttbr; | |
39bc88e5 CM |
181 | } |
182 | #else | |
183 | static inline void update_saved_ttbr0(struct task_struct *tsk, | |
184 | struct mm_struct *mm) | |
185 | { | |
186 | } | |
187 | #endif | |
b3901d54 | 188 | |
142802be WD |
189 | static inline void |
190 | enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) | |
191 | { | |
192 | /* | |
193 | * We don't actually care about the ttbr0 mapping, so point it at the | |
194 | * zero page. | |
195 | */ | |
196 | update_saved_ttbr0(tsk, &init_mm); | |
197 | } | |
198 | ||
39bc88e5 CM |
199 | static inline void __switch_mm(struct mm_struct *next) |
200 | { | |
201 | unsigned int cpu = smp_processor_id(); | |
c2775b2e | 202 | |
e53f21bc CM |
203 | /* |
204 | * init_mm.pgd does not contain any user mappings and it is always | |
205 | * active for kernel addresses in TTBR1. Just set the reserved TTBR0. | |
206 | */ | |
207 | if (next == &init_mm) { | |
208 | cpu_set_reserved_ttbr0(); | |
209 | return; | |
210 | } | |
211 | ||
c2775b2e | 212 | check_and_switch_context(next, cpu); |
b3901d54 CM |
213 | } |
214 | ||
39bc88e5 CM |
215 | static inline void |
216 | switch_mm(struct mm_struct *prev, struct mm_struct *next, | |
217 | struct task_struct *tsk) | |
218 | { | |
219 | if (prev != next) | |
220 | __switch_mm(next); | |
221 | ||
222 | /* | |
223 | * Update the saved TTBR0_EL1 of the scheduled-in task as the previous | |
224 | * value may have not been initialised yet (activate_mm caller) or the | |
225 | * ASID has changed since the last run (following the context switch | |
82dcf928 | 226 | * of another thread of the same process). |
39bc88e5 | 227 | */ |
82dcf928 | 228 | update_saved_ttbr0(tsk, next); |
39bc88e5 CM |
229 | } |
230 | ||
b3901d54 | 231 | #define deactivate_mm(tsk,mm) do { } while (0) |
39bc88e5 | 232 | #define activate_mm(prev,next) switch_mm(prev, next, current) |
b3901d54 | 233 | |
13f417f3 SP |
234 | void verify_cpu_asid_bits(void); |
235 | ||
38fd94b0 CC |
236 | #endif /* !__ASSEMBLY__ */ |
237 | ||
238 | #endif /* !__ASM_MMU_CONTEXT_H */ |