[mirror_ubuntu-artful-kernel.git] / arch / arm64 / kernel / cpu_errata.c

/*
 * Contains CPU specific errata definitions
 *
 * Copyright (C) 2014 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/types.h>
#include <asm/cpu.h>
#include <asm/cputype.h>
#include <asm/cpufeature.h>

static bool __maybe_unused
is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
{
	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
	return MIDR_IS_CPU_MODEL_RANGE(read_cpuid_id(), entry->midr_model,
				       entry->midr_range_min,
				       entry->midr_range_max);
}

static bool __maybe_unused
is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
{
	u32 model;

	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());

	model = read_cpuid_id();
	model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
		 MIDR_ARCHITECTURE_MASK;

	return model == entry->midr_model;
}

static bool
has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,
				int scope)
{
	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
	return (read_cpuid_cachetype() & arm64_ftr_reg_ctrel0.strict_mask) !=
		(arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask);
}

static int cpu_enable_trap_ctr_access(void *__unused)
{
	/* Clear SCTLR_EL1.UCT */
	config_sctlr_el1(SCTLR_EL1_UCT, 0);
	return 0;
}

#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>

DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);

#ifdef CONFIG_KVM
extern char __qcom_hyp_sanitize_link_stack_start[];
extern char __qcom_hyp_sanitize_link_stack_end[];
extern char __smccc_workaround_1_smc_start[];
extern char __smccc_workaround_1_smc_end[];
extern char __smccc_workaround_1_hvc_start[];
extern char __smccc_workaround_1_hvc_end[];

static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
				const char *hyp_vecs_end)
{
	void *dst = lm_alias(__bp_harden_hyp_vecs_start + slot * SZ_2K);
	int i;

	for (i = 0; i < SZ_2K; i += 0x80)
		memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start);

	flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K);
}

static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
				      const char *hyp_vecs_start,
				      const char *hyp_vecs_end)
{
	static int last_slot = -1;
	static DEFINE_SPINLOCK(bp_lock);
	int cpu, slot = -1;

	spin_lock(&bp_lock);
	for_each_possible_cpu(cpu) {
		if (per_cpu(bp_hardening_data.fn, cpu) == fn) {
			slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu);
			break;
		}
	}

	if (slot == -1) {
		last_slot++;
		BUG_ON(((__bp_harden_hyp_vecs_end - __bp_harden_hyp_vecs_start)
			/ SZ_2K) <= last_slot);
		slot = last_slot;
		__copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
	}

	__this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
	__this_cpu_write(bp_hardening_data.fn, fn);
	spin_unlock(&bp_lock);
}
#else
#define __qcom_hyp_sanitize_link_stack_start	NULL
#define __qcom_hyp_sanitize_link_stack_end	NULL
#define __smccc_workaround_1_smc_start		NULL
#define __smccc_workaround_1_smc_end		NULL
#define __smccc_workaround_1_hvc_start		NULL
#define __smccc_workaround_1_hvc_end		NULL

static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
				      const char *hyp_vecs_start,
				      const char *hyp_vecs_end)
{
	__this_cpu_write(bp_hardening_data.fn, fn);
}
#endif	/* CONFIG_KVM */

static void  install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry,
				     bp_hardening_cb_t fn,
				     const char *hyp_vecs_start,
				     const char *hyp_vecs_end)
{
	u64 pfr0;

	if (!entry->matches(entry, SCOPE_LOCAL_CPU))
		return;

	pfr0 = read_cpuid(ID_AA64PFR0_EL1);
	if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT))
		return;

	__install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end);
}

#include <uapi/linux/psci.h>
#include <linux/arm-smccc.h>
#include <linux/psci.h>

static void call_smc_arch_workaround_1(void)
{
	arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
}

static void call_hvc_arch_workaround_1(void)
{
	arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
}

static int enable_smccc_arch_workaround_1(void *data)
{
	const struct arm64_cpu_capabilities *entry = data;
	bp_hardening_cb_t cb;
	void *smccc_start, *smccc_end;
	struct arm_smccc_res res;

	if (!entry->matches(entry, SCOPE_LOCAL_CPU))
		return 0;

	if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
		return 0;

	switch (psci_ops.conduit) {
	case PSCI_CONDUIT_HVC:
		arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
				  ARM_SMCCC_ARCH_WORKAROUND_1, &res);
		if (res.a0)
			return 0;
		cb = call_hvc_arch_workaround_1;
		smccc_start = __smccc_workaround_1_hvc_start;
		smccc_end = __smccc_workaround_1_hvc_end;
		break;

	case PSCI_CONDUIT_SMC:
		arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
				  ARM_SMCCC_ARCH_WORKAROUND_1, &res);
		if (res.a0)
			return 0;
		cb = call_smc_arch_workaround_1;
		smccc_start = __smccc_workaround_1_smc_start;
		smccc_end = __smccc_workaround_1_smc_end;
		break;

	default:
		return 0;
	}

	install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);

	return 0;
}

static void qcom_link_stack_sanitization(void)
{
	u64 tmp;

	asm volatile("mov	%0, x30		\n"
		     ".rept	16		\n"
		     "bl	. + 4		\n"
		     ".endr			\n"
		     "mov	x30, %0		\n"
		     : "=&r" (tmp));
}

static int qcom_enable_link_stack_sanitization(void *data)
{
	const struct arm64_cpu_capabilities *entry = data;

	install_bp_hardening_cb(entry, qcom_link_stack_sanitization,
				__qcom_hyp_sanitize_link_stack_start,
				__qcom_hyp_sanitize_link_stack_end);

	return 0;
}
#endif	/* CONFIG_HARDEN_BRANCH_PREDICTOR */

#define MIDR_RANGE(model, min, max) \
	.def_scope = SCOPE_LOCAL_CPU, \
	.matches = is_affected_midr_range, \
	.midr_model = model, \
	.midr_range_min = min, \
	.midr_range_max = max

#define MIDR_ALL_VERSIONS(model) \
	.def_scope = SCOPE_LOCAL_CPU, \
	.matches = is_affected_midr_range, \
	.midr_model = model, \
	.midr_range_min = 0, \
	.midr_range_max = (MIDR_VARIANT_MASK | MIDR_REVISION_MASK)

const struct arm64_cpu_capabilities arm64_errata[] = {
#if	defined(CONFIG_ARM64_ERRATUM_826319) || \
	defined(CONFIG_ARM64_ERRATUM_827319) || \
	defined(CONFIG_ARM64_ERRATUM_824069)
	{
	/* Cortex-A53 r0p[012] */
		.desc = "ARM errata 826319, 827319, 824069",
		.capability = ARM64_WORKAROUND_CLEAN_CACHE,
		MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
		.enable = cpu_enable_cache_maint_trap,
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_819472
	{
	/* Cortex-A53 r0p[01] */
		.desc = "ARM errata 819472",
		.capability = ARM64_WORKAROUND_CLEAN_CACHE,
		MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01),
		.enable = cpu_enable_cache_maint_trap,
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_832075
	{
	/* Cortex-A57 r0p0 - r1p2 */
		.desc = "ARM erratum 832075",
		.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
		MIDR_RANGE(MIDR_CORTEX_A57,
			   MIDR_CPU_VAR_REV(0, 0),
			   MIDR_CPU_VAR_REV(1, 2)),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_834220
	{
	/* Cortex-A57 r0p0 - r1p2 */
		.desc = "ARM erratum 834220",
		.capability = ARM64_WORKAROUND_834220,
		MIDR_RANGE(MIDR_CORTEX_A57,
			   MIDR_CPU_VAR_REV(0, 0),
			   MIDR_CPU_VAR_REV(1, 2)),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_845719
	{
	/* Cortex-A53 r0p[01234] */
		.desc = "ARM erratum 845719",
		.capability = ARM64_WORKAROUND_845719,
		MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
	},
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_23154
	{
	/* Cavium ThunderX, pass 1.x */
		.desc = "Cavium erratum 23154",
		.capability = ARM64_WORKAROUND_CAVIUM_23154,
		MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
	},
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_27456
	{
	/* Cavium ThunderX, T88 pass 1.x - 2.1 */
		.desc = "Cavium erratum 27456",
		.capability = ARM64_WORKAROUND_CAVIUM_27456,
		MIDR_RANGE(MIDR_THUNDERX,
			   MIDR_CPU_VAR_REV(0, 0),
			   MIDR_CPU_VAR_REV(1, 1)),
	},
	{
	/* Cavium ThunderX, T81 pass 1.0 */
		.desc = "Cavium erratum 27456",
		.capability = ARM64_WORKAROUND_CAVIUM_27456,
		MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),
	},
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_30115
	{
	/* Cavium ThunderX, T88 pass 1.x - 2.2 */
		.desc = "Cavium erratum 30115",
		.capability = ARM64_WORKAROUND_CAVIUM_30115,
		MIDR_RANGE(MIDR_THUNDERX, 0x00,
			   (1 << MIDR_VARIANT_SHIFT) | 2),
	},
	{
	/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
		.desc = "Cavium erratum 30115",
		.capability = ARM64_WORKAROUND_CAVIUM_30115,
		MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x02),
	},
	{
	/* Cavium ThunderX, T83 pass 1.0 */
		.desc = "Cavium erratum 30115",
		.capability = ARM64_WORKAROUND_CAVIUM_30115,
		MIDR_RANGE(MIDR_THUNDERX_83XX, 0x00, 0x00),
	},
#endif
	{
		.desc = "Mismatched cache line size",
		.capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
		.matches = has_mismatched_cache_line_size,
		.def_scope = SCOPE_LOCAL_CPU,
		.enable = cpu_enable_trap_ctr_access,
	},
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
	{
		.desc = "Qualcomm Technologies Falkor erratum 1003",
		.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
		MIDR_RANGE(MIDR_QCOM_FALKOR_V1,
			   MIDR_CPU_VAR_REV(0, 0),
			   MIDR_CPU_VAR_REV(0, 0)),
	},
	{
		.desc = "Qualcomm Technologies Kryo erratum 1003",
		.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
		.def_scope = SCOPE_LOCAL_CPU,
		.midr_model = MIDR_QCOM_KRYO,
		.matches = is_kryo_midr,
	},
#endif
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
	{
		.desc = "Qualcomm Technologies Falkor erratum 1009",
		.capability = ARM64_WORKAROUND_REPEAT_TLBI,
		MIDR_RANGE(MIDR_QCOM_FALKOR_V1,
			   MIDR_CPU_VAR_REV(0, 0),
			   MIDR_CPU_VAR_REV(0, 0)),
	},
#endif
#ifdef CONFIG_ARM64_ERRATUM_858921
	{
	/* Cortex-A73 all versions */
		.desc = "ARM erratum 858921",
		.capability = ARM64_WORKAROUND_858921,
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
	},
#endif
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
	{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
		.enable = enable_smccc_arch_workaround_1,
	},
	{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
		.enable = enable_smccc_arch_workaround_1,
	},
	{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
		.enable = enable_smccc_arch_workaround_1,
	},
	{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
		.enable = enable_smccc_arch_workaround_1,
	},
	{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
		.enable = qcom_enable_link_stack_sanitization,
	},
	{
		.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
		MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
	},
	{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
		.enable = enable_smccc_arch_workaround_1,
	},
	{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
		.enable = enable_smccc_arch_workaround_1,
	},
#endif
	{
	}
};

/*
 * The CPU Errata work arounds are detected and applied at boot time
 * and the related information is freed soon after. If the new CPU requires
 * an errata not detected at boot, fail this CPU.
 */
void verify_local_cpu_errata_workarounds(void)
{
	const struct arm64_cpu_capabilities *caps = arm64_errata;

	for (; caps->matches; caps++) {
		if (cpus_have_cap(caps->capability)) {
			if (caps->enable)
				caps->enable((void *)caps);
		} else if (caps->matches(caps, SCOPE_LOCAL_CPU)) {
			pr_crit("CPU%d: Requires work around for %s, not detected"
					" at boot time\n",
				smp_processor_id(),
				caps->desc ? : "an erratum");
			cpu_die_early();
		}
	}
}

void update_cpu_errata_workarounds(void)
{
	update_cpu_capabilities(arm64_errata, "enabling workaround for");
}

void __init enable_errata_workarounds(void)
{
	enable_cpu_capabilities(arm64_errata);
}
Commit	Line	Data
e116a375 AP	1	/*
	2	* Contains CPU specific errata definitions
	3	*
	4	* Copyright (C) 2014 ARM Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
e116a375 AP	19	#include <linux/types.h>
	20	#include <asm/cpu.h>
	21	#include <asm/cputype.h>
	22	#include <asm/cpufeature.h>
	23
301bcfac	24	static bool __maybe_unused
92406f0c	25	is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
301bcfac	26	{
92406f0c	27	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
d5370f75 WD	28	return MIDR_IS_CPU_MODEL_RANGE(read_cpuid_id(), entry->midr_model,
	29	entry->midr_range_min,
	30	entry->midr_range_max);
301bcfac AP	31	}
301bcfac AP	32
b3af3364 SB	33	static bool __maybe_unused
	34	is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
	35	{
	36	u32 model;
	37
	38	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
	39
	40	model = read_cpuid_id();
	41	model &= MIDR_IMPLEMENTOR_MASK \| (0xf00 << MIDR_PARTNUM_SHIFT) \|
	42	MIDR_ARCHITECTURE_MASK;
	43
	44	return model == entry->midr_model;
	45	}
	46
116c81f4 SP	47	static bool
	48	has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,
	49	int scope)
	50	{
	51	WARN_ON(scope != SCOPE_LOCAL_CPU \|\| preemptible());
	52	return (read_cpuid_cachetype() & arm64_ftr_reg_ctrel0.strict_mask) !=
	53	(arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask);
	54	}
	55
2a6dcb2b	56	static int cpu_enable_trap_ctr_access(void *__unused)
116c81f4 SP	57	{
	58	/* Clear SCTLR_EL1.UCT */
	59	config_sctlr_el1(SCTLR_EL1_UCT, 0);
2a6dcb2b	60	return 0;
116c81f4 SP	61	}
116c81f4 SP	62
ec52ee18 WD	63	#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
	64	#include <asm/mmu_context.h>
	65	#include <asm/cacheflush.h>
	66
	67	DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
	68
	69	#ifdef CONFIG_KVM
a516894a SD	70	extern char __qcom_hyp_sanitize_link_stack_start[];
a516894a SD	71	extern char __qcom_hyp_sanitize_link_stack_end[];
a23a1a7e MZ	72	extern char __smccc_workaround_1_smc_start[];
	73	extern char __smccc_workaround_1_smc_end[];
	74	extern char __smccc_workaround_1_hvc_start[];
	75	extern char __smccc_workaround_1_hvc_end[];
f2f427ad	76
ec52ee18 WD	77	static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
	78	const char *hyp_vecs_end)
	79	{
	80	void dst = lm_alias(__bp_harden_hyp_vecs_start + slot SZ_2K);
	81	int i;
	82
	83	for (i = 0; i < SZ_2K; i += 0x80)
	84	memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start);
	85
	86	flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K);
	87	}
	88
	89	static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
	90	const char *hyp_vecs_start,
	91	const char *hyp_vecs_end)
	92	{
	93	static int last_slot = -1;
	94	static DEFINE_SPINLOCK(bp_lock);
	95	int cpu, slot = -1;
	96
	97	spin_lock(&bp_lock);
	98	for_each_possible_cpu(cpu) {
	99	if (per_cpu(bp_hardening_data.fn, cpu) == fn) {
	100	slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu);
	101	break;
	102	}
	103	}
	104
	105	if (slot == -1) {
	106	last_slot++;
	107	BUG_ON(((__bp_harden_hyp_vecs_end - __bp_harden_hyp_vecs_start)
	108	/ SZ_2K) <= last_slot);
	109	slot = last_slot;
	110	__copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
	111	}
	112
	113	__this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
	114	__this_cpu_write(bp_hardening_data.fn, fn);
	115	spin_unlock(&bp_lock);
	116	}
	117	#else
a516894a SD	118	#define __qcom_hyp_sanitize_link_stack_start NULL
a516894a SD	119	#define __qcom_hyp_sanitize_link_stack_end NULL
a23a1a7e MZ	120	#define __smccc_workaround_1_smc_start NULL
	121	#define __smccc_workaround_1_smc_end NULL
	122	#define __smccc_workaround_1_hvc_start NULL
	123	#define __smccc_workaround_1_hvc_end NULL
f2f427ad	124
ec52ee18 WD	125	static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
	126	const char *hyp_vecs_start,
	127	const char *hyp_vecs_end)
	128	{
	129	__this_cpu_write(bp_hardening_data.fn, fn);
	130	}
	131	#endif /* CONFIG_KVM */
	132
	133	static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry,
	134	bp_hardening_cb_t fn,
	135	const char *hyp_vecs_start,
	136	const char *hyp_vecs_end)
	137	{
	138	u64 pfr0;
	139
	140	if (!entry->matches(entry, SCOPE_LOCAL_CPU))
	141	return;
	142
	143	pfr0 = read_cpuid(ID_AA64PFR0_EL1);
	144	if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT))
	145	return;
	146
	147	__install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end);
	148	}
f2f427ad	149
a23a1a7e MZ	150	#include <uapi/linux/psci.h>
a23a1a7e MZ	151	#include <linux/arm-smccc.h>
f2f427ad WD	152	#include <linux/psci.h>
f2f427ad WD	153
a23a1a7e MZ	154	static void call_smc_arch_workaround_1(void)
	155	{
	156	arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
	157	}
	158
	159	static void call_hvc_arch_workaround_1(void)
	160	{
	161	arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
	162	}
	163
2408c4e2	164	static int enable_smccc_arch_workaround_1(void *data)
a23a1a7e	165	{
2408c4e2	166	const struct arm64_cpu_capabilities *entry = data;
a23a1a7e MZ	167	bp_hardening_cb_t cb;
	168	void smccc_start, smccc_end;
	169	struct arm_smccc_res res;
	170
	171	if (!entry->matches(entry, SCOPE_LOCAL_CPU))
2408c4e2	172	return 0;
a23a1a7e MZ	173
a23a1a7e MZ	174	if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
2408c4e2	175	return 0;
a23a1a7e MZ	176
	177	switch (psci_ops.conduit) {
	178	case PSCI_CONDUIT_HVC:
	179	arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
	180	ARM_SMCCC_ARCH_WORKAROUND_1, &res);
	181	if (res.a0)
2408c4e2	182	return 0;
a23a1a7e MZ	183	cb = call_hvc_arch_workaround_1;
	184	smccc_start = __smccc_workaround_1_hvc_start;
	185	smccc_end = __smccc_workaround_1_hvc_end;
	186	break;
	187
	188	case PSCI_CONDUIT_SMC:
	189	arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
	190	ARM_SMCCC_ARCH_WORKAROUND_1, &res);
	191	if (res.a0)
2408c4e2	192	return 0;
a23a1a7e MZ	193	cb = call_smc_arch_workaround_1;
	194	smccc_start = __smccc_workaround_1_smc_start;
	195	smccc_end = __smccc_workaround_1_smc_end;
	196	break;
	197
	198	default:
2408c4e2	199	return 0;
a23a1a7e MZ	200	}
	201
	202	install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);
	203
f2f427ad WD	204	return 0;
f2f427ad WD	205	}
a516894a SD	206
	207	static void qcom_link_stack_sanitization(void)
	208	{
	209	u64 tmp;
	210
	211	asm volatile("mov %0, x30 \n"
	212	".rept 16 \n"
	213	"bl . + 4 \n"
	214	".endr \n"
	215	"mov x30, %0 \n"
	216	: "=&r" (tmp));
	217	}
	218
	219	static int qcom_enable_link_stack_sanitization(void *data)
	220	{
	221	const struct arm64_cpu_capabilities *entry = data;
	222
	223	install_bp_hardening_cb(entry, qcom_link_stack_sanitization,
	224	__qcom_hyp_sanitize_link_stack_start,
	225	__qcom_hyp_sanitize_link_stack_end);
	226
	227	return 0;
	228	}
ec52ee18 WD	229	#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
ec52ee18 WD	230
301bcfac	231	#define MIDR_RANGE(model, min, max) \
92406f0c	232	.def_scope = SCOPE_LOCAL_CPU, \
359b7064	233	.matches = is_affected_midr_range, \
301bcfac AP	234	.midr_model = model, \
	235	.midr_range_min = min, \
	236	.midr_range_max = max
	237
06f1494f MZ	238	#define MIDR_ALL_VERSIONS(model) \
	239	.def_scope = SCOPE_LOCAL_CPU, \
	240	.matches = is_affected_midr_range, \
	241	.midr_model = model, \
	242	.midr_range_min = 0, \
	243	.midr_range_max = (MIDR_VARIANT_MASK \| MIDR_REVISION_MASK)
	244
359b7064	245	const struct arm64_cpu_capabilities arm64_errata[] = {
c0a01b84 AP	246	#if defined(CONFIG_ARM64_ERRATUM_826319) \|\| \
	247	defined(CONFIG_ARM64_ERRATUM_827319) \|\| \
	248	defined(CONFIG_ARM64_ERRATUM_824069)
301bcfac AP	249	{
	250	/* Cortex-A53 r0p[012] */
	251	.desc = "ARM errata 826319, 827319, 824069",
	252	.capability = ARM64_WORKAROUND_CLEAN_CACHE,
	253	MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
7dd01aef	254	.enable = cpu_enable_cache_maint_trap,
301bcfac	255	},
c0a01b84 AP	256	#endif
	257	#ifdef CONFIG_ARM64_ERRATUM_819472
	258	{
	259	/* Cortex-A53 r0p[01] */
	260	.desc = "ARM errata 819472",
	261	.capability = ARM64_WORKAROUND_CLEAN_CACHE,
	262	MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01),
7dd01aef	263	.enable = cpu_enable_cache_maint_trap,
c0a01b84 AP	264	},
	265	#endif
	266	#ifdef CONFIG_ARM64_ERRATUM_832075
301bcfac	267	{
5afaa1fc AP	268	/* Cortex-A57 r0p0 - r1p2 */
	269	.desc = "ARM erratum 832075",
	270	.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
fa5ce3d1 RR	271	MIDR_RANGE(MIDR_CORTEX_A57,
	272	MIDR_CPU_VAR_REV(0, 0),
	273	MIDR_CPU_VAR_REV(1, 2)),
5afaa1fc	274	},
905e8c5d	275	#endif
498cd5c3 MZ	276	#ifdef CONFIG_ARM64_ERRATUM_834220
	277	{
	278	/* Cortex-A57 r0p0 - r1p2 */
	279	.desc = "ARM erratum 834220",
	280	.capability = ARM64_WORKAROUND_834220,
fa5ce3d1 RR	281	MIDR_RANGE(MIDR_CORTEX_A57,
	282	MIDR_CPU_VAR_REV(0, 0),
	283	MIDR_CPU_VAR_REV(1, 2)),
498cd5c3 MZ	284	},
498cd5c3 MZ	285	#endif
905e8c5d WD	286	#ifdef CONFIG_ARM64_ERRATUM_845719
	287	{
	288	/* Cortex-A53 r0p[01234] */
	289	.desc = "ARM erratum 845719",
	290	.capability = ARM64_WORKAROUND_845719,
	291	MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
	292	},
6d4e11c5 RR	293	#endif
	294	#ifdef CONFIG_CAVIUM_ERRATUM_23154
	295	{
	296	/* Cavium ThunderX, pass 1.x */
	297	.desc = "Cavium erratum 23154",
	298	.capability = ARM64_WORKAROUND_CAVIUM_23154,
	299	MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
	300	},
104a0c02 AP	301	#endif
	302	#ifdef CONFIG_CAVIUM_ERRATUM_27456
	303	{
	304	/* Cavium ThunderX, T88 pass 1.x - 2.1 */
	305	.desc = "Cavium erratum 27456",
	306	.capability = ARM64_WORKAROUND_CAVIUM_27456,
fa5ce3d1 RR	307	MIDR_RANGE(MIDR_THUNDERX,
	308	MIDR_CPU_VAR_REV(0, 0),
	309	MIDR_CPU_VAR_REV(1, 1)),
104a0c02	310	},
47c459be GK	311	{
	312	/* Cavium ThunderX, T81 pass 1.0 */
	313	.desc = "Cavium erratum 27456",
	314	.capability = ARM64_WORKAROUND_CAVIUM_27456,
	315	MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),
	316	},
690a3415 DD	317	#endif
	318	#ifdef CONFIG_CAVIUM_ERRATUM_30115
	319	{
	320	/* Cavium ThunderX, T88 pass 1.x - 2.2 */
	321	.desc = "Cavium erratum 30115",
	322	.capability = ARM64_WORKAROUND_CAVIUM_30115,
	323	MIDR_RANGE(MIDR_THUNDERX, 0x00,
	324	(1 << MIDR_VARIANT_SHIFT) \| 2),
	325	},
	326	{
	327	/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
	328	.desc = "Cavium erratum 30115",
	329	.capability = ARM64_WORKAROUND_CAVIUM_30115,
	330	MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x02),
	331	},
	332	{
	333	/* Cavium ThunderX, T83 pass 1.0 */
	334	.desc = "Cavium erratum 30115",
	335	.capability = ARM64_WORKAROUND_CAVIUM_30115,
	336	MIDR_RANGE(MIDR_THUNDERX_83XX, 0x00, 0x00),
	337	},
c0a01b84	338	#endif
116c81f4 SP	339	{
	340	.desc = "Mismatched cache line size",
	341	.capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
	342	.matches = has_mismatched_cache_line_size,
	343	.def_scope = SCOPE_LOCAL_CPU,
	344	.enable = cpu_enable_trap_ctr_access,
	345	},
38fd94b0 CC	346	#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
	347	{
	348	.desc = "Qualcomm Technologies Falkor erratum 1003",
	349	.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
	350	MIDR_RANGE(MIDR_QCOM_FALKOR_V1,
	351	MIDR_CPU_VAR_REV(0, 0),
	352	MIDR_CPU_VAR_REV(0, 0)),
	353	},
b3af3364 SB	354	{
	355	.desc = "Qualcomm Technologies Kryo erratum 1003",
	356	.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
	357	.def_scope = SCOPE_LOCAL_CPU,
	358	.midr_model = MIDR_QCOM_KRYO,
	359	.matches = is_kryo_midr,
	360	},
38fd94b0	361	#endif
d9ff80f8 CC	362	#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
	363	{
	364	.desc = "Qualcomm Technologies Falkor erratum 1009",
	365	.capability = ARM64_WORKAROUND_REPEAT_TLBI,
	366	MIDR_RANGE(MIDR_QCOM_FALKOR_V1,
	367	MIDR_CPU_VAR_REV(0, 0),
	368	MIDR_CPU_VAR_REV(0, 0)),
	369	},
eeb1efbc MZ	370	#endif
	371	#ifdef CONFIG_ARM64_ERRATUM_858921
	372	{
	373	/* Cortex-A73 all versions */
	374	.desc = "ARM erratum 858921",
	375	.capability = ARM64_WORKAROUND_858921,
	376	MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
	377	},
f2f427ad WD	378	#endif
	379	#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
	380	{
	381	.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
	382	MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
2408c4e2	383	.enable = enable_smccc_arch_workaround_1,
f2f427ad WD	384	},
	385	{
	386	.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
	387	MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
2408c4e2	388	.enable = enable_smccc_arch_workaround_1,
f2f427ad WD	389	},
	390	{
	391	.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
	392	MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
2408c4e2	393	.enable = enable_smccc_arch_workaround_1,
f2f427ad WD	394	},
	395	{
	396	.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
	397	MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
2408c4e2	398	.enable = enable_smccc_arch_workaround_1,
f2f427ad	399	},
a516894a SD	400	{
	401	.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
	402	MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
	403	.enable = qcom_enable_link_stack_sanitization,
	404	},
	405	{
	406	.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
	407	MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
	408	},
91ea0fd6 J	409	{
	410	.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
	411	MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
2408c4e2	412	.enable = enable_smccc_arch_workaround_1,
91ea0fd6 J	413	},
	414	{
	415	.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
	416	MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
2408c4e2	417	.enable = enable_smccc_arch_workaround_1,
91ea0fd6	418	},
d9ff80f8	419	#endif
5afaa1fc	420	{
301bcfac	421	}
e116a375 AP	422	};
e116a375 AP	423
6a6efbb4 SP	424	/*
	425	* The CPU Errata work arounds are detected and applied at boot time
	426	* and the related information is freed soon after. If the new CPU requires
	427	* an errata not detected at boot, fail this CPU.
	428	*/
89ba2645	429	void verify_local_cpu_errata_workarounds(void)
6a6efbb4 SP	430	{
	431	const struct arm64_cpu_capabilities *caps = arm64_errata;
	432
5d2e2eb5 SP	433	for (; caps->matches; caps++) {
	434	if (cpus_have_cap(caps->capability)) {
	435	if (caps->enable)
	436	caps->enable((void *)caps);
	437	} else if (caps->matches(caps, SCOPE_LOCAL_CPU)) {
6a6efbb4 SP	438	pr_crit("CPU%d: Requires work around for %s, not detected"
	439	" at boot time\n",
	440	smp_processor_id(),
	441	caps->desc ? : "an erratum");
	442	cpu_die_early();
	443	}
5d2e2eb5	444	}
6a6efbb4 SP	445	}
6a6efbb4 SP	446
89ba2645	447	void update_cpu_errata_workarounds(void)
e116a375	448	{
ce8b602c	449	update_cpu_capabilities(arm64_errata, "enabling workaround for");
e116a375	450	}
8e231852 AP	451
	452	void __init enable_errata_workarounds(void)
	453	{
	454	enable_cpu_capabilities(arm64_errata);
	455	}