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arm64: cleanup {COMPAT_,}SET_PERSONALITY() macro
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CommitLineData
b3901d54
CM
1/*
2 * Based on arch/arm/kernel/process.c
3 *
4 * Original Copyright (C) 1995 Linus Torvalds
5 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
6 * Copyright (C) 2012 ARM Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <stdarg.h>
22
fd92d4a5 23#include <linux/compat.h>
60c0d45a 24#include <linux/efi.h>
b3901d54
CM
25#include <linux/export.h>
26#include <linux/sched.h>
b17b0153 27#include <linux/sched/debug.h>
29930025 28#include <linux/sched/task.h>
68db0cf1 29#include <linux/sched/task_stack.h>
b3901d54
CM
30#include <linux/kernel.h>
31#include <linux/mm.h>
32#include <linux/stddef.h>
33#include <linux/unistd.h>
34#include <linux/user.h>
35#include <linux/delay.h>
36#include <linux/reboot.h>
37#include <linux/interrupt.h>
38#include <linux/kallsyms.h>
39#include <linux/init.h>
40#include <linux/cpu.h>
41#include <linux/elfcore.h>
42#include <linux/pm.h>
43#include <linux/tick.h>
44#include <linux/utsname.h>
45#include <linux/uaccess.h>
46#include <linux/random.h>
47#include <linux/hw_breakpoint.h>
48#include <linux/personality.h>
49#include <linux/notifier.h>
096b3224 50#include <trace/events/power.h>
c02433dd 51#include <linux/percpu.h>
b3901d54 52
57f4959b 53#include <asm/alternative.h>
b3901d54
CM
54#include <asm/compat.h>
55#include <asm/cacheflush.h>
d0854412 56#include <asm/exec.h>
ec45d1cf
WD
57#include <asm/fpsimd.h>
58#include <asm/mmu_context.h>
b3901d54
CM
59#include <asm/processor.h>
60#include <asm/stacktrace.h>
b3901d54 61
c0c264ae
LA
62#ifdef CONFIG_CC_STACKPROTECTOR
63#include <linux/stackprotector.h>
64unsigned long __stack_chk_guard __read_mostly;
65EXPORT_SYMBOL(__stack_chk_guard);
66#endif
67
b3901d54
CM
68/*
69 * Function pointers to optional machine specific functions
70 */
71void (*pm_power_off)(void);
72EXPORT_SYMBOL_GPL(pm_power_off);
73
b0946fc8 74void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
b3901d54 75
b3901d54
CM
76/*
77 * This is our default idle handler.
78 */
0087298f 79void arch_cpu_idle(void)
b3901d54
CM
80{
81 /*
82 * This should do all the clock switching and wait for interrupt
83 * tricks
84 */
096b3224 85 trace_cpu_idle_rcuidle(1, smp_processor_id());
6990566b
NP
86 cpu_do_idle();
87 local_irq_enable();
096b3224 88 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
b3901d54
CM
89}
90
9327e2c6
MR
91#ifdef CONFIG_HOTPLUG_CPU
92void arch_cpu_idle_dead(void)
93{
94 cpu_die();
95}
96#endif
97
90f51a09
AK
98/*
99 * Called by kexec, immediately prior to machine_kexec().
100 *
101 * This must completely disable all secondary CPUs; simply causing those CPUs
102 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
103 * kexec'd kernel to use any and all RAM as it sees fit, without having to
104 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
105 * functionality embodied in disable_nonboot_cpus() to achieve this.
106 */
b3901d54
CM
107void machine_shutdown(void)
108{
90f51a09 109 disable_nonboot_cpus();
b3901d54
CM
110}
111
90f51a09
AK
112/*
113 * Halting simply requires that the secondary CPUs stop performing any
114 * activity (executing tasks, handling interrupts). smp_send_stop()
115 * achieves this.
116 */
b3901d54
CM
117void machine_halt(void)
118{
b9acc49e 119 local_irq_disable();
90f51a09 120 smp_send_stop();
b3901d54
CM
121 while (1);
122}
123
90f51a09
AK
124/*
125 * Power-off simply requires that the secondary CPUs stop performing any
126 * activity (executing tasks, handling interrupts). smp_send_stop()
127 * achieves this. When the system power is turned off, it will take all CPUs
128 * with it.
129 */
b3901d54
CM
130void machine_power_off(void)
131{
b9acc49e 132 local_irq_disable();
90f51a09 133 smp_send_stop();
b3901d54
CM
134 if (pm_power_off)
135 pm_power_off();
136}
137
90f51a09
AK
138/*
139 * Restart requires that the secondary CPUs stop performing any activity
68234df4 140 * while the primary CPU resets the system. Systems with multiple CPUs must
90f51a09
AK
141 * provide a HW restart implementation, to ensure that all CPUs reset at once.
142 * This is required so that any code running after reset on the primary CPU
143 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
144 * executing pre-reset code, and using RAM that the primary CPU's code wishes
145 * to use. Implementing such co-ordination would be essentially impossible.
146 */
b3901d54
CM
147void machine_restart(char *cmd)
148{
b3901d54
CM
149 /* Disable interrupts first */
150 local_irq_disable();
b9acc49e 151 smp_send_stop();
b3901d54 152
60c0d45a
AB
153 /*
154 * UpdateCapsule() depends on the system being reset via
155 * ResetSystem().
156 */
157 if (efi_enabled(EFI_RUNTIME_SERVICES))
158 efi_reboot(reboot_mode, NULL);
159
b3901d54 160 /* Now call the architecture specific reboot code. */
aa1e8ec1 161 if (arm_pm_restart)
ff701306 162 arm_pm_restart(reboot_mode, cmd);
1c7ffc32
GR
163 else
164 do_kernel_restart(cmd);
b3901d54
CM
165
166 /*
167 * Whoops - the architecture was unable to reboot.
168 */
169 printk("Reboot failed -- System halted\n");
170 while (1);
171}
172
173void __show_regs(struct pt_regs *regs)
174{
6ca68e80
CM
175 int i, top_reg;
176 u64 lr, sp;
177
178 if (compat_user_mode(regs)) {
179 lr = regs->compat_lr;
180 sp = regs->compat_sp;
181 top_reg = 12;
182 } else {
183 lr = regs->regs[30];
184 sp = regs->sp;
185 top_reg = 29;
186 }
b3901d54 187
a43cb95d 188 show_regs_print_info(KERN_DEFAULT);
b3901d54 189 print_symbol("PC is at %s\n", instruction_pointer(regs));
6ca68e80 190 print_symbol("LR is at %s\n", lr);
b3901d54 191 printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
6ca68e80
CM
192 regs->pc, lr, regs->pstate);
193 printk("sp : %016llx\n", sp);
db4b0710
MR
194
195 i = top_reg;
196
197 while (i >= 0) {
b3901d54 198 printk("x%-2d: %016llx ", i, regs->regs[i]);
db4b0710
MR
199 i--;
200
201 if (i % 2 == 0) {
202 pr_cont("x%-2d: %016llx ", i, regs->regs[i]);
203 i--;
204 }
205
206 pr_cont("\n");
b3901d54 207 }
b3901d54
CM
208}
209
210void show_regs(struct pt_regs * regs)
211{
b3901d54 212 __show_regs(regs);
1149aad1 213 dump_backtrace(regs, NULL);
b3901d54
CM
214}
215
eb35bdd7
WD
216static void tls_thread_flush(void)
217{
adf75899 218 write_sysreg(0, tpidr_el0);
eb35bdd7
WD
219
220 if (is_compat_task()) {
221 current->thread.tp_value = 0;
222
223 /*
224 * We need to ensure ordering between the shadow state and the
225 * hardware state, so that we don't corrupt the hardware state
226 * with a stale shadow state during context switch.
227 */
228 barrier();
adf75899 229 write_sysreg(0, tpidrro_el0);
eb35bdd7
WD
230 }
231}
232
b3901d54
CM
233void flush_thread(void)
234{
235 fpsimd_flush_thread();
eb35bdd7 236 tls_thread_flush();
b3901d54
CM
237 flush_ptrace_hw_breakpoint(current);
238}
239
240void release_thread(struct task_struct *dead_task)
241{
242}
243
244int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
245{
6eb6c801
JL
246 if (current->mm)
247 fpsimd_preserve_current_state();
b3901d54
CM
248 *dst = *src;
249 return 0;
250}
251
252asmlinkage void ret_from_fork(void) asm("ret_from_fork");
253
254int copy_thread(unsigned long clone_flags, unsigned long stack_start,
afa86fc4 255 unsigned long stk_sz, struct task_struct *p)
b3901d54
CM
256{
257 struct pt_regs *childregs = task_pt_regs(p);
b3901d54 258
c34501d2 259 memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
b3901d54 260
9ac08002
AV
261 if (likely(!(p->flags & PF_KTHREAD))) {
262 *childregs = *current_pt_regs();
c34501d2 263 childregs->regs[0] = 0;
d00a3810
WD
264
265 /*
266 * Read the current TLS pointer from tpidr_el0 as it may be
267 * out-of-sync with the saved value.
268 */
adf75899 269 *task_user_tls(p) = read_sysreg(tpidr_el0);
d00a3810
WD
270
271 if (stack_start) {
272 if (is_compat_thread(task_thread_info(p)))
e0fd18ce 273 childregs->compat_sp = stack_start;
d00a3810 274 else
e0fd18ce 275 childregs->sp = stack_start;
c34501d2 276 }
d00a3810 277
b3901d54 278 /*
c34501d2
CM
279 * If a TLS pointer was passed to clone (4th argument), use it
280 * for the new thread.
b3901d54 281 */
c34501d2 282 if (clone_flags & CLONE_SETTLS)
d00a3810 283 p->thread.tp_value = childregs->regs[3];
c34501d2
CM
284 } else {
285 memset(childregs, 0, sizeof(struct pt_regs));
286 childregs->pstate = PSR_MODE_EL1h;
57f4959b 287 if (IS_ENABLED(CONFIG_ARM64_UAO) &&
a4023f68 288 cpus_have_const_cap(ARM64_HAS_UAO))
57f4959b 289 childregs->pstate |= PSR_UAO_BIT;
c34501d2
CM
290 p->thread.cpu_context.x19 = stack_start;
291 p->thread.cpu_context.x20 = stk_sz;
b3901d54 292 }
b3901d54 293 p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
c34501d2 294 p->thread.cpu_context.sp = (unsigned long)childregs;
b3901d54
CM
295
296 ptrace_hw_copy_thread(p);
297
298 return 0;
299}
300
936eb65c
DM
301void tls_preserve_current_state(void)
302{
303 *task_user_tls(current) = read_sysreg(tpidr_el0);
304}
305
b3901d54
CM
306static void tls_thread_switch(struct task_struct *next)
307{
308 unsigned long tpidr, tpidrro;
309
936eb65c 310 tls_preserve_current_state();
b3901d54 311
d00a3810
WD
312 tpidr = *task_user_tls(next);
313 tpidrro = is_compat_thread(task_thread_info(next)) ?
314 next->thread.tp_value : 0;
b3901d54 315
adf75899
MR
316 write_sysreg(tpidr, tpidr_el0);
317 write_sysreg(tpidrro, tpidrro_el0);
b3901d54
CM
318}
319
57f4959b 320/* Restore the UAO state depending on next's addr_limit */
d0854412 321void uao_thread_switch(struct task_struct *next)
57f4959b 322{
e950631e
CM
323 if (IS_ENABLED(CONFIG_ARM64_UAO)) {
324 if (task_thread_info(next)->addr_limit == KERNEL_DS)
325 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO));
326 else
327 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO));
328 }
57f4959b
JM
329}
330
c02433dd
MR
331/*
332 * We store our current task in sp_el0, which is clobbered by userspace. Keep a
333 * shadow copy so that we can restore this upon entry from userspace.
334 *
335 * This is *only* for exception entry from EL0, and is not valid until we
336 * __switch_to() a user task.
337 */
338DEFINE_PER_CPU(struct task_struct *, __entry_task);
339
340static void entry_task_switch(struct task_struct *next)
341{
342 __this_cpu_write(__entry_task, next);
343}
344
b3901d54
CM
345/*
346 * Thread switching.
347 */
8f4b326d 348__notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev,
b3901d54
CM
349 struct task_struct *next)
350{
351 struct task_struct *last;
352
353 fpsimd_thread_switch(next);
354 tls_thread_switch(next);
355 hw_breakpoint_thread_switch(next);
3325732f 356 contextidr_thread_switch(next);
c02433dd 357 entry_task_switch(next);
57f4959b 358 uao_thread_switch(next);
b3901d54 359
5108c67c
CM
360 /*
361 * Complete any pending TLB or cache maintenance on this CPU in case
362 * the thread migrates to a different CPU.
363 */
98f7685e 364 dsb(ish);
b3901d54
CM
365
366 /* the actual thread switch */
367 last = cpu_switch_to(prev, next);
368
369 return last;
370}
371
b3901d54
CM
372unsigned long get_wchan(struct task_struct *p)
373{
374 struct stackframe frame;
9bbd4c56 375 unsigned long stack_page, ret = 0;
b3901d54
CM
376 int count = 0;
377 if (!p || p == current || p->state == TASK_RUNNING)
378 return 0;
379
9bbd4c56
MR
380 stack_page = (unsigned long)try_get_task_stack(p);
381 if (!stack_page)
382 return 0;
383
b3901d54 384 frame.fp = thread_saved_fp(p);
b3901d54 385 frame.pc = thread_saved_pc(p);
20380bb3
AT
386#ifdef CONFIG_FUNCTION_GRAPH_TRACER
387 frame.graph = p->curr_ret_stack;
388#endif
b3901d54 389 do {
91f62af8 390 if (unwind_frame(p, &frame))
9bbd4c56
MR
391 goto out;
392 if (!in_sched_functions(frame.pc)) {
393 ret = frame.pc;
394 goto out;
395 }
b3901d54 396 } while (count ++ < 16);
9bbd4c56
MR
397
398out:
399 put_task_stack(p);
400 return ret;
b3901d54
CM
401}
402
403unsigned long arch_align_stack(unsigned long sp)
404{
405 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
406 sp -= get_random_int() & ~PAGE_MASK;
407 return sp & ~0xf;
408}
409
b3901d54
CM
410unsigned long arch_randomize_brk(struct mm_struct *mm)
411{
61462c8a 412 if (is_compat_task())
ffe3d1e4 413 return randomize_page(mm->brk, SZ_32M);
61462c8a 414 else
ffe3d1e4 415 return randomize_page(mm->brk, SZ_1G);
b3901d54 416}
d924dedb
YN
417
418/*
419 * Called from setup_new_exec() after (COMPAT_)SET_PERSONALITY.
420 */
421void arch_setup_new_exec(void)
422{
423 current->mm->context.flags = is_compat_task() ? MMCF_AARCH32 : 0;
424}