[mirror_ubuntu-artful-kernel.git] / arch / ia64 / include / asm / futex.h

#ifndef _ASM_FUTEX_H
#define _ASM_FUTEX_H

#include <linux/futex.h>
#include <linux/uaccess.h>
#include <asm/errno.h>

#define __futex_atomic_op1(insn, ret, oldval, uaddr, oparg) \
do {									\
	register unsigned long r8 __asm ("r8") = 0;			\
	__asm__ __volatile__(						\
		"	mf;;					\n"	\
		"[1:] "	insn ";;				\n"	\
		"	.xdata4 \"__ex_table\", 1b-., 2f-.	\n"	\
		"[2:]"							\
		: "+r" (r8), "=r" (oldval)				\
		: "r" (uaddr), "r" (oparg)				\
		: "memory");						\
	ret = r8;							\
} while (0)

#define __futex_atomic_op2(insn, ret, oldval, uaddr, oparg) \
do {									\
	register unsigned long r8 __asm ("r8") = 0;			\
	int val, newval;						\
	do {								\
		__asm__ __volatile__(					\
			"	mf;;				  \n"	\
			"[1:]	ld4 %3=[%4];;			  \n"	\
			"	mov %2=%3			  \n"	\
				insn	";;			  \n"	\
			"	mov ar.ccv=%2;;			  \n"	\
			"[2:]	cmpxchg4.acq %1=[%4],%3,ar.ccv;;  \n"	\
			"	.xdata4 \"__ex_table\", 1b-., 3f-.\n"	\
			"	.xdata4 \"__ex_table\", 2b-., 3f-.\n"	\
			"[3:]"						\
			: "+r" (r8), "=r" (val), "=&r" (oldval),	\
			   "=&r" (newval)				\
			: "r" (uaddr), "r" (oparg)			\
			: "memory");					\
		if (unlikely (r8))					\
			break;						\
	} while (unlikely (val != oldval));				\
	ret = r8;							\
} while (0)

static inline int
arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
{
	int oldval = 0, ret;

	pagefault_disable();

	switch (op) {
	case FUTEX_OP_SET:
		__futex_atomic_op1("xchg4 %1=[%2],%3", ret, oldval, uaddr,
				   oparg);
		break;
	case FUTEX_OP_ADD:
		__futex_atomic_op2("add %3=%3,%5", ret, oldval, uaddr, oparg);
		break;
	case FUTEX_OP_OR:
		__futex_atomic_op2("or %3=%3,%5", ret, oldval, uaddr, oparg);
		break;
	case FUTEX_OP_ANDN:
		__futex_atomic_op2("and %3=%3,%5", ret, oldval, uaddr,
				   ~oparg);
		break;
	case FUTEX_OP_XOR:
		__futex_atomic_op2("xor %3=%3,%5", ret, oldval, uaddr, oparg);
		break;
	default:
		ret = -ENOSYS;
	}

	pagefault_enable();

	if (!ret)
		*oval = oldval;

	return ret;
}

static inline int
futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
			      u32 oldval, u32 newval)
{
	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
		return -EFAULT;

	{
		register unsigned long r8 __asm ("r8") = 0;
		unsigned long prev;
		__asm__ __volatile__(
			"	mf;;					\n"
			"	mov ar.ccv=%4;;				\n"
			"[1:]	cmpxchg4.acq %1=[%2],%3,ar.ccv		\n"
			"	.xdata4 \"__ex_table\", 1b-., 2f-.	\n"
			"[2:]"
			: "+r" (r8), "=&r" (prev)
			: "r" (uaddr), "r" (newval),
			  "rO" ((long) (unsigned) oldval)
			: "memory");
		*uval = prev;
		return r8;
	}
}

#endif /* _ASM_FUTEX_H */
Commit	Line	Data
4732efbe JJ	1	#ifndef _ASM_FUTEX_H
	2	#define _ASM_FUTEX_H
	3
a192dc16	4	#include <linux/futex.h>
730f412c	5	#include <linux/uaccess.h>
a192dc16	6	#include <asm/errno.h>
4732efbe	7
a192dc16 JJ	8	#define __futex_atomic_op1(insn, ret, oldval, uaddr, oparg) \
	9	do { \
	10	register unsigned long r8 __asm ("r8") = 0; \
	11	__asm__ __volatile__( \
	12	" mf;; \n" \
	13	"[1:] " insn ";; \n" \
	14	" .xdata4 \"__ex_table\", 1b-., 2f-. \n" \
	15	"[2:]" \
	16	: "+r" (r8), "=r" (oldval) \
	17	: "r" (uaddr), "r" (oparg) \
	18	: "memory"); \
	19	ret = r8; \
	20	} while (0)
	21
	22	#define __futex_atomic_op2(insn, ret, oldval, uaddr, oparg) \
	23	do { \
	24	register unsigned long r8 __asm ("r8") = 0; \
	25	int val, newval; \
	26	do { \
	27	__asm__ __volatile__( \
	28	" mf;; \n" \
	29	"[1:] ld4 %3=[%4];; \n" \
	30	" mov %2=%3 \n" \
	31	insn ";; \n" \
	32	" mov ar.ccv=%2;; \n" \
	33	"[2:] cmpxchg4.acq %1=[%4],%3,ar.ccv;; \n" \
	34	" .xdata4 \"__ex_table\", 1b-., 3f-.\n" \
	35	" .xdata4 \"__ex_table\", 2b-., 3f-.\n" \
	36	"[3:]" \
	37	: "+r" (r8), "=r" (val), "=&r" (oldval), \
	38	"=&r" (newval) \
	39	: "r" (uaddr), "r" (oparg) \
	40	: "memory"); \
	41	if (unlikely (r8)) \
	42	break; \
	43	} while (unlikely (val != oldval)); \
	44	ret = r8; \
	45	} while (0)
	46
	47	static inline int
5961958c	48	arch_futex_atomic_op_inuser(int op, int oparg, int oval, u32 __user uaddr)
a192dc16	49	{
a192dc16	50	int oldval = 0, ret;
a192dc16	51
a866374a	52	pagefault_disable();
a192dc16 JJ	53
	54	switch (op) {
	55	case FUTEX_OP_SET:
	56	__futex_atomic_op1("xchg4 %1=[%2],%3", ret, oldval, uaddr,
	57	oparg);
	58	break;
	59	case FUTEX_OP_ADD:
	60	__futex_atomic_op2("add %3=%3,%5", ret, oldval, uaddr, oparg);
	61	break;
	62	case FUTEX_OP_OR:
	63	__futex_atomic_op2("or %3=%3,%5", ret, oldval, uaddr, oparg);
	64	break;
	65	case FUTEX_OP_ANDN:
	66	__futex_atomic_op2("and %3=%3,%5", ret, oldval, uaddr,
	67	~oparg);
	68	break;
	69	case FUTEX_OP_XOR:
	70	__futex_atomic_op2("xor %3=%3,%5", ret, oldval, uaddr, oparg);
	71	break;
	72	default:
	73	ret = -ENOSYS;
	74	}
	75
a866374a	76	pagefault_enable();
a192dc16	77
5961958c JS	78	if (!ret)
	79	*oval = oldval;
	80
a192dc16 JJ	81	return ret;
	82	}
	83
	84	static inline int
8d7718aa ML	85	futex_atomic_cmpxchg_inatomic(u32 uval, u32 __user uaddr,
8d7718aa ML	86	u32 oldval, u32 newval)
a192dc16	87	{
8d7718aa	88	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
a192dc16 JJ	89	return -EFAULT;
	90
	91	{
136f39dd	92	register unsigned long r8 __asm ("r8") = 0;
37a9d912	93	unsigned long prev;
a192dc16 JJ	94	__asm__ __volatile__(
a192dc16 JJ	95	" mf;; \n"
c76f39bd TL	96	" mov ar.ccv=%4;; \n"
c76f39bd TL	97	"[1:] cmpxchg4.acq %1=[%2],%3,ar.ccv \n"
a192dc16 JJ	98	" .xdata4 \"__ex_table\", 1b-., 2f-. \n"
a192dc16 JJ	99	"[2:]"
136f39dd	100	: "+r" (r8), "=&r" (prev)
a192dc16 JJ	101	: "r" (uaddr), "r" (newval),
	102	"rO" ((long) (unsigned) oldval)
	103	: "memory");
37a9d912	104	*uval = prev;
a192dc16 JJ	105	return r8;
	106	}
	107	}
	108
	109	#endif /* _ASM_FUTEX_H */